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2021-07-28ec/roda/it8518/acpi: Use mathematical operatorsFelix Singer
Use mathematical operators instead of their equivalent methods. Change-Id: I5b1d5d9882eae5e8bcf2d97bcefaeea1a7ad8f4d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56607 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Use bit-wise and logical operatorsFelix Singer
Use bit-wise and logical operators instead of their equivalent methods. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I30807e14b2a9a8203a76d418f586423bcaec2a3a Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28ec/roda/it8518/acpi: Make use of the assignment operatorFelix Singer
Replace `Store()` with the assignment operator. Change-Id: I2931a3e1b9a55198ec4dacc9218b6c9028052631 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Get rid of `Index()`Felix Singer
Use `FOOO[1337]` instead of `Index(FOOO, 1337)`. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4f5d5cb8ce8c3ae37dc44ca87bd67596af9feee8 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Use decimal integers for accessing indexesFelix Singer
Change-Id: I7d4fb69a223e3b48a790e9144d2682619c18d513 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Make use of `Printf("...")`Felix Singer
Replace `Store("...", Debug)` with `Printf("...")`. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: Ie1a1f7320ef2850e4f861b1426240e6940036844 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Don't hard-code GPE offsetNico Huber
The GPE offset of 16 is PCH specific. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-16ec/kontron/kempld: Add minimal GPIO driverMaxim Polyakov
The patch adds an interface for configuring GPIOs inside the Kontron CPLD/EC. This allows to statically define the mode for each GPIO pin in devicetree.cb of the motherboard or carrier board. For example: chip ec/kontron/kempld device gpio 0 on register "gpio[0]" = "KEMPLD_GPIO_INPUT" register "gpio[4]" = "KEMPLD_GPIO_OUTPUT_LOW" register "gpio[5]" = "KEMPLD_GPIO_OUTPUT_HIGH" register "gpio[11]" = "KEMPLD_GPIO_DEFAULT" end end In this case, <device gpio 0>, like all other devices, is not a real device inside the EC. These definitions are used to understand the EC resources and systematize configuration options, but if mark this as <off>, the initialization step will be skipped in the driver code. Use KEMPLD_GPIO_DEFAULT or skip it in devicetree.cb to not configure the GPIO and keep the default mode after CPLD reset. This work is based on code from the drivers/gpio/gpio-kempld.c linux driver. Tested on Kontron mAL-10 COMe module [1]. [1] CB:54380 , Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47595 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-30ec/google: Use EC_HOST_EVENT_NONERob Barnes
google_chromeec_get_event returns 0 for no event. Return EC_HOST_EVENT_NONE=0 to improve readability. BUG=b:184074997 TEST=Build and boot guybrush without error Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30ec/google: Sync ec_commands.hRob Barnes
This change syncs the coreboot version of google ec_commands.h with the ec_commands.h from the google ec repository. This is a straight copy except for the the copyright header. BUG=b:184074997 TEST=Build and boot guybrush BRANCH=None Change-Id: I095c3316d720328cb7b8dd1b72ffc108208b14bd Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-21ec/google/wilco: Fix comment about enclosure typeKyösti Mälkki
SYSTEM_TYPE_CONVERTIBLE is not valid SMBIOS enclosure type, but selecting it implies SMBIOS_ENCLOSURE_CONVERTIBLE. Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-21ec/purism/librem/ec.asl: Disable notification for touchpad enable/disableMatt DeVillier
Somehow, enabling the notification to the OS driver breaks the functionality it was meant to enable. Until this can be resolved, disable the driver notification, so that the key functions as intended. Test: build/boot librem_bdw and librem_skl boards, verify trackpad enable toggle via Fn+F1 works properly. Change-Id: Ic7bdb3154a87c4202b5ee1fd333281ef78db1104 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55657 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17ec/google: Fix bad return valueRob Barnes
google_chromeec_get_event returns an event number and 0 when there's no event. This function is usually called in a loop until there are no more events, so it makes sense to return 0 (i.e. no event) when there's an error. BUG=b:184074997 TEST=Boot guybrush, no ec errors Change-Id: I6c0186e4637af9ae24f45cce3638f0913227d6a7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-09ec/google/chromeec: Separate SMBIOS SKU functionsYu-Ping Wu
All functions in ec_skuid.c except google_chromeec_get_board_sku() are for SMBIOS platforms. Move these functions to a new file to allow non-SMBIOS platforms to use google_chromeec_get_board_sku() without having to declare MAINBOARD_SMBIOS_MANUFACTURER. BUG=none TEST=emerge-cherry coreboot BRANCH=none Change-Id: I8916223f5f04afe4761be4ad3313e900efae90d4 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04ec: Add Star Labs ITE 8987E supportSean Rhodes
Support for Star Labs labtop series EC Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28ec/kontron/kempld: Guard macro parametersAngel Pons
Add parentheses around macro parameters to avoid operation order issues. Change-Id: I2d4552abaeda5702619cc53e9dfae1f17b048e67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28ec/google/wilco: Extend description of `EC_GOOGLE_WILCO`Paul Menzel
Change-Id: Ia278b538a8904651d16c37d095972fa78e264288 Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/7S5OJMLQUEIU6YK36JTTRINF5OOCI66V/ Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-26ec/google/wilco/mailbox: Fix format warning by using size_t length modifierPaul Menzel
Building google/sarien with a 64-bit compiler (x86_64-linux-gnu) fails with the error below. src/ec/google/wilco/mailbox.c: In function 'wilco_ec_transfer': src/ec/google/wilco/mailbox.c:184:43: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] 184 | printk(BIOS_ERR, "%s: data too short (%lu bytes, expected %zu)", | ~~^ | | | long unsigned int | %u 185 | __func__, rs.data_size - skip_size, msg->response_size); | ~~~~~~~~~~~~~~~~~~~~~~~~ | | | size_t {aka unsigned int} `data_size` has type `uint16_t`, and `skip_size` has type `size_t`, whose size differs in 32-bit (unsigned int) and 64-bit (unsigned long). So use the length modifier `z` for a `size_t` argument. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Change-Id: Ida27323daeed9b8ff487302d0f3d6fcce0bbb705 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie
2021-05-20ec/google/chromeec: Implement support for DRIVERS_ACPI_THERMAL_ZONERaul E Rangel
This adds the required method to access temperature data from the ChromeEC. BUG=b:186166365 TEST=Boot guybrush to the OS and verify temperatures $ tail /sys/devices/virtual/thermal/thermal_zone*/temp ==> /sys/devices/virtual/thermal/thermal_zone0/temp <== 31900 ==> /sys/devices/virtual/thermal/thermal_zone1/temp <== 34900 ==> /sys/devices/virtual/thermal/thermal_zone2/temp <== 31900 ==> /sys/devices/virtual/thermal/thermal_zone3/temp <== 33900 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I418b6691a7d00a4c2d89c9c1fe8f9416602be0f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54133 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18ec/google/chromeec: Provide EC access for Retimer firmware upgradeJohn Zhao
coreboot needs to access EC RFWU entry in order to suspend and resume PD and modes setting. This change adds ec_retimer_fw_update implementation for retimer firmware upgrade. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ib937d8bd72fc39487854773573b435bf2add672a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52713 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18ec/google/chromeec: Remove ec_retimer_fw_updateJohn Zhao
Along with upstream kernel for Retimer firmware update, coreboot changes the ec_retimer_fw_update format. This change removes this API and will add implementation later once the dependent definition is complete. BUG=b:186521258 TEST=Build image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I2d074b84fb3cb87b443871104b72b6c316af5279 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-29ec/lenovo/h8/h8.c: Skip setting volume if out of rangeAngel Pons
This change is needed to update the option API to use unsigned integers. The CMOS option system does not support negative numbers. The volume field is only 8 bits long. Do not set the volume if it is out of range. Also, use an out-of-range value as fallback to skip setting the volume when it cannot be read using the option API, to preserve the current behavior. Change-Id: I7af68bb5c1ecd4489ab4b826b9a5e7999c77b1ff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-29chromeec: Fix google_chromeec_status_check timeoutRob Barnes
Rewrite google_chromeec_status_check to use stopwatch instead of a delay in a while loop. In practice the while loop ends up taking much longer than one second to timeout. Using stopwatch library will accurately timeout after one second. BUG=b:183524609 TEST=Build and run on guybrush BRANCH=None Change-Id: I363ff7453bcf81581884f92797629a6f96d42580 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-21ec/purism/librem-ec: Apply initial Purism customizationsNicole Faerber
- remove unused Kconfig options - change ACPI device name and HID - remove ACPI for unused color keyboard backlight - add support for RGB notification LED - rename Wifi LED ACPI variable - set some battery info defaults not populated by the EC Change-Id: I72eca9deb83e5a6d919d6fcbd3b354fbf6e7a925 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-21ec/purism/librem-ec: Add support for Purism Librem ECMatt DeVillier
Initial commit is a clone of ec/system76/ec with string changes; Purism-specific functionality will be added in subsequent commits. Change-Id: I8c51724e6dbfe1bc09496537f9e031643f95c755 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-21ec/kontron: Use get_int_option()Angel Pons
Change-Id: Ibca7660ed03525903a1146a1fb2937550406bee8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21ec/lenovo: Use get_int_option()Angel Pons
Change-Id: Ie5cb54b171244be71848a59a788ed8d42b3e3161 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-12chromeec: make ssfc optional in fw_configKangheui Won
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, all fw_config is invalidated. But for some platform this may not be necessary, we can treat missing SSFC as zero and use other 32 bits of firmware config. BUG=b:184809649 TEST=boot and check fw_config is not -1 even if ssfc is not set BRANCH=zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-08ec/lenovo/h8/acpi: fix wrong calculationMichael Niewöhner
The conversion to ASL 2.0 syntax in commit 81d55cf introduced a regression triggering a BUG in Linux when reading the battery current. Correct the wrongly-converted calculation. Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0") Tested-by: Andrew A. I. <aidron@yandex.ru> Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52144 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27ec/system76/ec: Add OLED screen toggleJeremy Soller
Change-Id: I667accd980da6384a7cc6a3f4eb7565b8b3b2400 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-27ec/system76/ec: Clean up/document battery ACPIJeremy Soller
Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Change-Id: I3a67008d84da614e8c8cbfa681a0fdd19ff1d77f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexey Vazhnov <vazhnov@boot-keys.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-27ec/google/chromeec: Optionally include SSFC in firmware configKarthikeyan Ramasubramanian
Fetch second source factory cache configuration (SSFC) as an optional element to the firmware config interface. Introduce a Kconfig so that it can be enabled and used on required mainboards. BUG=b:177055126 TEST=Build and Boot to OS in Magolor. Change-Id: I81137406d21e77b5d58a33f66778e13cf16c85c7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51094 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27ec/system76/ec: Preserve ECOS through suspendJeremy Soller
When the EC is reset on PLTRST this information will be lost, causing system control interrupts to potentially stop functioning. Change-Id: I137ef6c574a372601bc51f6e815158767acd0e1b Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50489 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-09src/ec/acpi/ec.asl: Convert to ASL 2.0Elyes HAOUAS
Change-Id: I078ca86cf9e948d4dd4338fca842ae3e580228ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05ec/apple: Add ACPI code for Apple MacBooksEvgeny Zinoviev
- Move ACPI code for Apple MacBooks to a separate directory to avoid its duplication in mainboards - Add AC and lid implementations for newer generations - Rewrite old code using the new ASL syntax Tested on MBA 5,2, MBP 8,1 and MBP 10,1. Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-03ec/hp/kbc1126: Wait a longer time after sendingPablo Stebler
This fixes the fan always running at full speed on ProBook 6360b, EliteBook 8470p and ProBook 640 G1 (because the fan control command was not sent). On the ProBook 6360b, the EC needs about 30 ms to process the first command on a cold boot, but other models such as the ProBook 640 G1 need more time. Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb Signed-off-by: Pablo Stebler <pablo@stebler.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-24ec/google/wilco: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/compal: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I934f9d1664f657597f15daed2d2d0c41cd124d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/acpi: Convert 'ec.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ifd85d2eabbda4e25406f20391489c0e7ad314348 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/acpi/ec.c: Use __func__Elyes HAOUAS
Change-Id: I4823b84d851d7d1f0f48be44ab28e7365b553b6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-24ec/purism/librem/acpi/ec.asl: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ic773f8404c24fc886e8420a5f4b3e00b2d752ba2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-22ec/google/chromeec: Provide EC access for Retimer firmware updateJohn Zhao
Kernel needs to access EC RFWU entry in order to retrieve from EC about port and mux info and set EC operations like modes change. This change provides EC RFWU path and update for Retimer driver usage. BUG=b:162528867 TEST=Booted to kernel and verified EC RFWU path from ACPI SSDT table. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I3817d93cfdeedf15825dab6c537b151fd063338b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49257 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware updateJohn Zhao
The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for operations. The supported operations are: RETIMER_FW_UPDATE_PORT_INFO 0 RETIMER_FW_UPDATE_PD_SUSPEND 1 RETIMER_FW_UPDATE_PD_RESUME 2 RETIMER_FW_UPDATE_GET_MUX 3 RETIMER_FW_UPDATE_SET_USB 4 RETIMER_FW_UPDATE_SET_SAFE 5 RETIMER_FW_UPDATE_SET_TBT 6 RETIMER_FW_UPDATE_DISCONNECT 7 BUG=b:162528867 TEST=Booted to kernel and verified RFWU entry from ACPI DSDT ERAM field. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49051 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ec/google/chromeec/ec_commands.h: Remove repeated wordElyes HAOUAS
Change-Id: I87d5a5fa584b4250bc8b532c046e6bd070e33e81 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18ec/google/chromeec/ec.h: Remove repeated wordElyes HAOUAS
Change-Id: I7f567f2b4c582e4b2bb102ef0e0f68c5bf6cfb9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18ec/system76/ec: Add fan and temperature reportingJeremy Soller
Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Change-Id: Iee19e7518ffaacd9a847cb6d28c839d4ec464514 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15build system: Remove flock calls from intermediate processingPatrick Georgi
Now that intermediate coreboot.pre manipulation is serialized within the build system, remove the flock calls. Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08ec/google/chromeec: add SSFC CBI supportMarco Chen
An API is added to get SSFC value from cros EC. BUG=b:174118027 BRANCH=octopus TEST=check SSFC value from EC is correct compared to value in CBI Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2021-01-08ec/google/chromeec: Check AP reset cause for watchdog resetYu-Ping Wu
Different from mt8183, mt8192 doesn't need to trigger EC reboot on HW initiated watchdog reset. Therefore, ec_reset_flags cannot be used to determine AP watchdog reset. Instead we check the cause of the last AP reset. BUG=b:174443398 TEST=emerge-asurada coreboot TEST=crash.WatchdogCrash passed on asurada BRANCH=none Cq-Depend: chromium:2607150 Change-Id: I761ecdd8811e5612b39e96c73442cc796361d0f0 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49113 Reviewed-by: Nicolas Boichat <drinkcat@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08ec/google/chromeec: Update ec_commands.hYu-Ping Wu
This change copies ec_commands.h directly from the Chromium OS EC repo at SHA afffc28f2, with the exception of changing the copyright header to SPDX format. Change-Id: Ie02e0295312050e803a7d701ec4eed1dadfa6c9a Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-08ec/system76/ec: Remove unused EC RAM fieldsJeremy Soller
These fields were originally added for compatibility with the proprietary ITE EC firmware, but the System76 EC firmware does not use them. Take the opportunity to document most of the fields as well. Change-Id: I5581437c67ec67705ce16ba20254183a0261fd83 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-08cbfstool: Use flock() when accessing CBFS filesJulius Werner
Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01ec/google/chromeec/acpi: Make OperationRegion brace alignSubrata Banik
Inject TAB to make OperationRegion closing brace align with opening brace. Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-18ec/google/chromeec: Add more wrappers for regulator controlYidi Lin
google_chromeec_regulator_enable is for enabling/disabling the regulator. google_chromeec_regulator_is_enabled is for querying if the regulator is enabled. BUG=b:168863056,b:147789962 BRANCH=none TEST=emerge-asurada coreboot Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/46686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-11-16src: Update some incorrect config options in commentsMartin Roth
This is a trivial patch to fix some comments that were generating notes in the kconfig lint test. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I26a95f17e82910f50c62215be5c29780fe98e29a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47366 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09ec/purism/librem/ec.asl: End commentBenjamin Doron
End comment that (likely mistakenly) removed an EC query method. Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-09acpi: Call acpi_fill_ssdt() only for enabled devicesKarthikeyan Ramasubramanian
Individual drivers check whether the concerned device is enabled before filling in the SSDT. Move the check before calling acpi_fill_ssdt() and remove the check in the individual drivers. BUG=None TEST=util/abuild/abuild Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-05ec/google/chromeec: Remove the check for Internal TypeC MUXKarthikeyan Ramasubramanian
Integrated TypeC MUX is used only in certain SoCs and hence the missing devicetree configuration is not an error. Remove the check for internal TypeC MUX device and the associated debug statement. BUG=b:172186858 TEST=Build and boot to OS in Drawlat. Change-Id: Ieb76e1ccfd04f1628617b2665b05be6718a25f81 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-04ec/purism/librem: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl are same for purism Librem 15 v4. Change-Id: I36cb7a2ebde1161f87e78eeab739b15e3cf88860 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-02ec/system76/ec: Add battery charging thresholdsTim Crawford
System76 EC firmware supports setting charging thresholds for a single battery. Change-Id: I3d656291c096f320d469274677e9fe6c74819d25 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45532 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02ec/system76/ec: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I83a4a3ad8a9fcb6071e0c700bf2be1676847aa9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-11-02ec/hp/kbc1126: Support using a different GPEIru Cai
HP EliteBook Folio 9480m uses the HP KBC1126 EC ACPI interface, but with a different GPE, so add a Kconfig option to support using a different GPE. Change-Id: I3b78567e1387c96bf173e4370aa3c836bbddac0b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45576 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30fw_config: Convert fw_config to a 64-bit fieldTim Wawrzynczak
We all knew this was coming, 32 bits is never enough. Doing this early so that it doesn't affect too much code yet. Take care of every usage of fw_config throughout the codebase so the conversion is all done at once. BUG=b:169668368 TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG and verify the console print contained that bit. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/tigerlake: Replace soc_get_pmc_mux_device with device pointersTim Wawrzynczak
Now that device aliases can be used in the devicetree, the hacky function 'soc_get_pmc_mux_device' can be removed and replaced with pointers to the devices the function was supposed to return (1 for each port). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie00834c79bd5304998adaccb388ae74a108192b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45747 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26ec/google/chromeec: Update ec_commands.hTim Wawrzynczak
This change copies ec_commands.h directly from the Chromium OS EC repo at SHA edd8b73e8, with the exception of changing the copyright header to SPDX format. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I97bdb12dd561bd95746cc2761397aa7406326e12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45937 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20ec/google/chromeec: Add wrappers to get/set the voltageYidi Lin
Add APIs to get and set the voltage for the target regulator. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-15ec/google/chromeec: Update ec_commands.hYidi Lin
This change copies ec_commands.h from Chromium OS EC repo at 7b6cb69db. The change also drops unneeded empty lines and coverts license header to SPDX style. BUG=b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I9816dab5edb418e76896355a0802c59307c664c4 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-14src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)Divya Sasidharan
EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIs added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST=Built coreboot image and verified that using this patch mux is being set for display during boot Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-11ec/kontron/kempld: Reflow long linesMaxim Polyakov
Change-Id: Ia5ad0715b742427dffa6c0c507269d904fe19bcb Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-11ec/kontron/kempld: add option to configure I2C frequencyMaxim Polyakov
Allows to change the I2C bus frequency by overriding i2c_frequency option from the board devicetree. Thus, the I2C controller can use Fast-mode (Fm), with a bit rate up to 400 kbit/s and Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s [1]. Tested on Kontron mAL10 COMe module with T10-TNI carrierboard [2]. [1] I2C-bus specification and user manual, doc #UM10204, Rev. 6, 4 April 2014. [2] https://review.coreboot.org/c/coreboot/+/39133 Change-Id: If0eb477af10d00eb4f17f9c01209f170b746ad3d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44476 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28ec/hp/kbc1126: Support not putting EC firmware in CBFSIru Cai
For mainboards using the HP KBC1126 EC interface, but with a different EC implementation, we don't put the EC firmware in the CBFS image. Add a Kconfig option to prevent the build system warning on not inserting the EC firmware. After this change, building coreboot for EliteBook Folio 9480m will not have a warning on not inserting the EC firmware. The build system still builds a working coreboot image for EliteBook 2560p, and gives a warning if not choosing to insert the EC firmware. Change-Id: I3be83a13d138d3623064ef2803f3e3a340207ead Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-23ec/google/chromeec: set DPTC power parameter at OS startupKevin Chiu
set DPTC power parameter per clamshell/tablet mode after EC OP region is accessible. BUG=b:157943445 BRANCH=zork TEST=1. emerge-zork coreboot 2. power on DUT in tablet mode then check "thermctl_limit" will change automatically Change-Id: Ic3e1119881790c34f5649986334b4e3cecafc02b Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17ec/google/chromeec: Add dptc interface supportChris Wang
add the dptc interface support when system in tablet mode. In some FP5/FT5 platform, which will have different power or thermal parameters depends on different form factor. BUG=b:157943445 BRANCH=Zork TEST=Build. check the setting changed. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I2be7942132cea474237f531021ad4fd9856b5050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44265 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11src/ec: Drop unneeded empty linesElyes HAOUAS
Change-Id: I1955390fcceeb42ecb644ac74541b7e9dd25320f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-07ec/system76: Add console supportJeremy Soller
This adds support for line-buffered console output to System76 EC firmware. Once the print command is received, the EC firmware multiplexes the output to any enabled console on the EC. This can be a memory ringbuffer, a parallel port (using the keyboard connector), or i2c (using the battery connector). Once the entire buffer is sent, it sets the command register to 0, indicating completion. For more information, please see: https://github.com/system76/ec/blob/master/doc/debugging.md Tested on system76/lemp9 with CONSOLE_SYSTEM76_EC enabled. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I861bf3e22f40dd6c3ec7ba1d73711b399358e332 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-14ec/google/chromeec: Add helper to request AP resetKarthikeyan Ramasubramanian
Add a helper function to initiate AP reset through Embedded Controller (EC). BUG=b:162290856 TEST=Ensure that the EC resets AP on boards where the command is supported. Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44188 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26ec/lenovo/h8: Align macro values in one columnPaul Menzel
Change-Id: I5691a582d9a195317994413fff4fd3273413b5fe Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove whitespace between 'sizeof' and '('Elyes HAOUAS
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove unneeded space in license headerElyes HAOUAS
Change-Id: Iac0f0c3d102a9a900ac168f8be907349d9a3dd42 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43565 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26ec/google/chromeec: Fix loop off-by-one error in DPTF _OSCTim Wawrzynczak
The while loop in \_SB.DPTF._OSC accidentally used <= instead of <, so there was an error indexing into IDSP. BUG=b:162043345 TEST=verify disassembled ASL, as well as no BIOS bug mentioned in /var/log/messages Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I08c4152c59cc9eb13386c825aab983681cfa88ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/43827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Remove extra lines in license headerElyes HAOUAS
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23ec/system76_ec: add support for System76 ECJeremy Soller
This adds ACPI code for System76 EC and converts system76/lemp9 to use EC_SYSTEM76_EC. Tested on system76/lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-22ec/google/chromeec: Fix Coverity Scan error (BAD_SHIFT)Tim Wawrzynczak
A recent Coverity scan found an issue with the way the EC_HOST_EVENT_MASK macro was being used. It was being passed values between 0 and 63, but since it is doing basically (1ULL << (value - 1)), this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd bit of the mask. This is fixed by incrementing the start and end conditions of the loop by 1, so the event mask ranges from bits 0 to 63, instead of -1 to 62. Found-by: Coverity CID 1430218 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18ec/google/chromeec: Fix oversights in ec_dptf_helpersTim Wawrzynczak
GTSH was 2 instead of 20 (so it's 2 degrees K hysteresis), and TSRD was accidentally defined to take 0 arguments, instead of 1. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I14d28bacf44ac65043060b8579b3fbcec758c56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18ec/google/chromeec: Fix \_SB.DPTF._OSCTim Wawrzynczak
The DPTF._OSC method incorrectly assumed that all available UUIDs would be present in the IDSP package, but this is not always the case. Instead of matching an incoming UUID against an index into IDSP, search the IDSP package for the matching UUID. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I718b6abe09152647b14f7c1405b2d0d20035726b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-07ec/google: Add function ec_fill_dptf_helpers()Tim Wawrzynczak
ec_fill_dptf_helpers() is used to generate all of the "helper" methods that DPTF requires. A system with a Chrome EC is typically in charge of fan PWM control as well as battery charging, so if DPTF needs to manipulate those, then it requires Methods provided by the EC. BUG=b:143539650 TEST=compiles Change-Id: Ib30072d1d0748b31bcab240a0fd0e2f12d34aaa4 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41894 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Drop codec.aslFurquan Shaikh
This change drops codec.asl file from Chrome EC since it is now unused. Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43043 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Add driver for audio codec deviceFurquan Shaikh
This change adds driver for audio codec device (HID `GOOG0013`) living behind Chrome EC. This driver generates the required ACPI node for the codec device. In a later change, GOOG0013 device will be dropped the .asl file. Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43041 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/KconfigFurquan Shaikh
This change moves `if EC_GOOGLE_CHROMEEC` from chromeec/Kconfig to chromeec/i2c_tunnel/Kconfig. This is done to make it clear that the Kconfig file in i2c_tunnel is sourced unconditionally, but the configs in i2c_tunnel/Kconfig are conditionally defined based on the evaluation of if condition. This change addressed the feedback received on https://review.coreboot.org/c/coreboot/+/40515/11/src/ec/google/chromeec/Kconfig#200. Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43040 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04drivers/intel/pmc_mux: Rename con driver to connTim Wawrzynczak
For historical reasons, Windows has issues with certain names being used for files and directories, 'con' or 'CON' being one of them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in order to work around this issue. TEST=built volteer (only user of this driver as of now) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-17ec/google/wilco: Suppress UCSI events in S0ixDuncan Laurie
If a UCSI event comes in when the EC is in S0ix mode then the kernel driver attempts a transaction but fails and this can leave the system in an unexpected state where the only wake source is the power button. This change will not notify the UCSI driver if the EC is in S0ix mode and instead keep track of the event and send it on resume. BUG=b:157923800 TEST=tested on drallion system: 1. Put drallion system into suspend 2. Attach power supply 3. Ensure the system can wake with keypress Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I43acb089385d9b41ac955f053e409daad67423f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14ec/google/chromeec: Call \PNOT () on initializing AC power stateFurquan Shaikh
This change calls \PNOT () method when AC power state is initialized to allow platform code to take appropriate action. BUG=b:157752693 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 12:10:17 +0000