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Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
The original include/ec_cmd_api.h version in the EC repo is:
d0771e49e7 MKBP: Increase key matrix size
Change-Id: I4f3dfc3f145e50e6114894352cdc118ad5a9565b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82995
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Under Windows ACPI, GpioInt and _PRW must be mututally exclusive within
the scope of a device, otherwise a BSOD occurs with an ACPI_BIOS_ERROR.
To enforce this, only use _PRW when EC_ENABLE_SYNC_IRQ_GPIO is not set.
If both EC_ENABLE_WAKE_PIN and EC_ENABLE_SYNC_IRQ_GPIO are set, then
ensure that the GpioInt is flagged as ExclusiveAndWake (vs just
Exclusive) so that the CREC device is still able to wake the device
as needed.
TEST=Build/boot google/{nocturne,frostflow} to Win11 w/ sync_irq_gpio
and wake_pin both enabled.
Change-Id: Ia59cce2ee12bfc8d3ac0173a7a4ec88d7079a958
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82233
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the EC doesn't know a value, it will report it as 0xffff. In these
cases, calculate a value to used based on others. For example, if the
EC doesn't know the last full charge capacity, report the design
capacity to the OS.
Change-Id: I310555ff913c2e492bbaec4d77281ac32c0de7a3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81408
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I559aca98044b7f0e6b08c475b5383c014bb4cd3f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81407
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename the BRPR (Battery Remaining Percentage) to B1RP to match
the format of the other variables.
Change-Id: I64a744d78180156e16dbd483a35c7f97ac84bcba
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81406
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iccb60d3530227fb71a3ce5a3ab1421627cc86611
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81405
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The BT1T (temperature) and BT1C (control) are not used so remove
them.
Change-Id: Ie6e85042ec59851bcfb4c88a2e04181c3c39f89c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81404
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The battery remaining percentage is a uint16_t, so correct this in
the EC memory. This change is non-function, as the EC is little
endian.
Change-Id: I56a0ae8199a95c9722e9bcb4c0739f4ef1d6ab05
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81403
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add BIX Method to report extended battery information.
Change-Id: Ie5baecb20c7d4600e0cf1d19ff5f67ce2003fa1d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add Kconfig strings for the battery:
* Model
* OEM
* Technology
Change-Id: Ibbce87ad54874f490af45c41f31956a7e9e996f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I27062c38c10df1d03f563b2f5391f79a3b6ee4fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81411
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3eea1a6d5bf652b9d9b430e9cd59ef9a3ea9fe2f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Initial commit is a copy of ec/system76/ec from tag v24.02.1 (commit
0a280ff7) with string changes. Dasharo-specific features will be added
in subsequent commits, similar to how Librem EC support was added in
changes 52390 and 52391.
Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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When support for the dictation key was added in commit f2782b8328d5
(acpigen_ps2_keybd: Add support for dictation key), I had failed to
include this portion of the change in that commit. The top row key of
`TK_DICTATE` needs to be converted to the ps2_action_key. This commit
simply adds that mapping so that it can be translated.
BUG=b:333101631
TEST=Flash DUT that emits a scancode for a dictation key, verify that it
is mapped to KEY_DICTATE in the Linux kernel using `evtest`.
Change-Id: I1be8c0a96931cca36e6bbbfa0be7d36c4cd93768
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82274
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the ChromiumOS EC indicates that the device has an assistant key,
we should also add it to the generated linux,keymap binding. This
commit simply does so by examining the keyboard capabilities reported by
the EC.
BUG=b:333088656
TEST=With a device that has an assistant key, flash AP FW and verify
that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using
`evtest`.
Change-Id: I217220e89bce88e3045a4fc3b124954696276442
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Do not fill the ACPI table entry associated with the cros_ec_typec
driver once we switch to the UCSI kernel driver. Skip the ACPI entry if
EC implements the UCSI_PPM feature, and the CBI flag to enable UCSI is
set.
BUG=b:333078787
TEST=emerge-brox coreboot chromeos-bootimage
Cq-Depend: chromium:5416841
Change-Id: I67dff6445aa7ba3ba48a04d1df3541f880d09d0a
Signed-off-by: Pavan Holla <pholla@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
b3b35d6433 PPM: Rename ucsi_disabled to ucsi_enabled
The original include/ec_cmd_api.h version in the EC repo is:
562316a71e include: Add fingerprint host commands to ec_cmd_api.h
BUG=b:333078787
TEST=cros build-packages --board brox \
chromeos-bootimage depthcharge coreboot
TEST=cros build-packages --board brya \
chromeos-bootimage depthcharge coreboot
BRANCH=none
Change-Id: I94b509cd6ad8f24bfc3b44ef02633d06320f1e22
Signed-off-by: Pavan Holla <pholla@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81965
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
9fdd96bfc6 keyboard: Add support for a "Dictation" key
The original include/ec_cmd_api.h version in the EC repo is:
562316a71e include: Add fingerprint host commands to ec_cmd_api.h
Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81932
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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_STA unconditionally returning 0xF is pretty much the default[1] and
should be removed to reduce some noise.
[1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html#sta-device-status
Change-Id: I0390767aa866e322c762038c12116a15b280af1a
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Method(..., 0, NotSerialized) is the default[1] and can be reduced to
Method(...) which reduces some noise.
TEST=Timeless build produces the same binary
[1] https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/19_ASL_Reference/ACPI_Source_Language_Reference.html#method-declare-control-method
Change-Id: Ic24e004500a7fa2a5a5b38a3f6f0e13e4ce7dfac
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81205
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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This also does some light cleaning up:
- Place spaces in function names to make it easier to read.
- Adds a newline to a console message.
TEST=Tested to work on HP ProBook 450 G3
Change-Id: I73e60c5baa9db6874e480ecef41cf1006150e081
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81204
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of having things depend on EC_GOOGLE_CHROMEEC, just put an if/
endif block around the configs.
The 'source' line stays outside of the if block because the source
always happens, even if it's inside an if/endif block. Each of the
sub-Kconfigs here already has an if/endif block surrounding the
contents.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Several older ChromeOS boards have issues with fan control on cold boot
and/or on S3 resume, so add functionality to allow those boards to
programmatically enable auto fan control.
TEST=build/boot google/link, verify fan ramps up/down accordingly with
CPU load.
Change-Id: I08a8562531f8af0c71230477d0221d536443f096
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the ubtc.asl as it's no longer needed.
Change-Id: I8564bb7d9bd94c8303c543c078bc76192539c5f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80484
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These entries no longer exist as they are stored in CFR.
Change-Id: Ia85855fddc36db76a65490a1d685e1943db28b74
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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As DRIVERS_PS2_KEYBOARD isn't set, this function is not doing anything.
Change-Id: Ie8842a32fca56f330a0f044cf96112dc5cae6546
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The name LEDLOGO comes from schematics. It's the red indicator, embedded
in the dot of the 'i' of the ThinkPad logo on laptop's lid.
In vendor firmware, this led starts fading in-and-out, or, in other
words, pulsing, when laptop is put to S3. It helps to determine whether
the laptop is in S3 just by taking a look at the logo.
As of now, coreboot doesn't do anything with this particular indicator,
it's always in enabled (on) state, which is not very convenient.
This patch fixes it.
Tested on T440p.
Change-Id: I85fb69c8c1bed8635a1b31e9b8385c7036bb46dd
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80437
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic060f3605cd18d4bf774573c21957f626f984e2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80069
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ibfa17ca83ca178c942d9c41533152235384e0cdf
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Original-Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This was determined by sniffing the LPC bus while moving the hardware
wireless switch between the enabled and disabled positions on the
Latitude E6400. The vendor BIOS provides options to change which radios
the switch controls, which was used to determine the mapping between
each radio device and the command argument values.
Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77534
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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This updates all warnings currently being printed under the files_added
and build_complete targets to the show_notices target.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I926ec4c1c00339209ef656995031026935e52558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ACPI spec defines keywords for the GpioInt and Interrupt resources
to specify whether a given pin is wake capable. Some boards are using
the ec sync interrupt pin to wake the system so the CREC _CRS needs to
be updated accordingly.
Provide a new macro that allows a board to specify whether its ec sync
pin is wake capable.
BUG=b:243700486
TEST=Dump ACPI and verify ExclusiveAndWake share type is set when
EC_SYNC_IRQ_WAKE_CAPABLE is defined
Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
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Building the Lenovo T60/T60p, iasl 20230628 shows the remark below:
dsdt.asl 2099: PowerResource (FPwR, 0, 0)
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR)
dsdt.asl 2118: Name (_PR0, Package () { FPwR })
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR)
Address it by making it all upper case.
Change-Id: Ia7924b015e76c43818d2d82da35ce0013d721c26
Fixes: 3ab13a8691cb ("ec/lenovo/h8/acpi/thermal: Add support for passive cooling")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79367
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
ab9b64ac4c Add a host command to print info about AP-firmware state
The original include/ec_cmd_api.h version in the EC repo is:
ab9b64ac4c Add a host command to print info about AP-firmware state
BUG=b:300525571
BRANCH=none
TEST=none
Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In EC versions older than 1.18, if the mirror flag was enabled, the
EC would mirror once the system reached S5.
When a mirror is successful, the system will automatically power
on, as it acts like it's been in G3. This led to machines turning on
when the intention was them to be off.
In 1.18 and later, they're installed when turning on. The result was
slower boot times when mirroring, but no unwanted powering on.
Because of this, coreboot no longer needs to power off when setting
the mirror flag.
Change-Id: I973c1ecd59f32d3353ca392769b44aadf5fcc9c3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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This reverts commit bb5fa6419dfd71950e61e75eecd48ef8203bb1b1.
Reason for revert: accidentally committed out of order; reverting to
unbreak tree
Change-Id: I36aa1fd3a0befe49b7e9e34198676f16fb08cf73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78524
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: Martin L Roth <gaumless@gmail.com>
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Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This adds is_battery_present_and_above_critical_threshold to check the
battery is present and the battery level is above critical level.
BUG=b:296952944
TEST=Build rex and check is_battery_present_and_above_critical_threshold
returns the correct battery status.
Change-Id: Ib38be55bc42559bab4f12d5e8580ddc3e1a6acc1
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Simplify the Q events for the battery and charger to just notify
when a status has changed. The EC will trigger these events when
either has changed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3300be5254549fe5cd3b3490d9191240c6d36b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77405
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Librem 11's volume keys act as a PS/2 keyboard with only those two
keys. Reduce the minimum number of top-row keys to 2. Make the
"rest of keys" (alphanumerics, punctuation, etc.) optional.
Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data
section support for pre-memory stages"), the `ENV_HAS_DATA_SECTION'
flag and its derivatives can now be removed from the code.
Change-Id: Ic0afac76264a9bd4a9c93ca35c90bd84e9b747a2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77291
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia4b142a5eac2aab7e4fa6e32ed68c96934ec6c32
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Previously the clear_ec_ap_idle() is implemented in
cr50_enable_update.c and be called in the file. Move it to
common code so that it can be called in cse_board_reset.c
TEST=emerge-brask coreboot
Change-Id: I2dbe41b01e70f7259f75d967e6df694a3e0fac23
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77631
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Use 'sizeof(ecfw)' instead of 'sizeof ecfw'.
sizeof operator should only be used for types and variables require sizeof().
Change-Id: Ifae1680917bb0ce610e6ba753741aae233a71103
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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KBL_STATE was originally intended to provide more granular control
of the keyboard backlight. However, KBL_BRIGHTNESS has a valid value
of "off" which achieves the same thing.
Therefore, unconditionally set the KBL_STATE to enabled, and rely on
KBL_BRIGHTNESS.
Change-Id: Ic7ee6b96b1dcaa6633b111e92097bce87908885e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77201
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows coolstar's Windows overlay drivers to attach, while not affecting
operation under Linux or ChromeOS
TEST=build/boot Win11, Linux 6.x on google/drallion
Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows the EC to be properly notified of type-c events like charger
wattage too low (eg),
TEST=build/boot Win11, Linux 6.x on google/drallion
Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the USCI device scope to _SB and set HID to USBC000 so Windows
driver attaches. This matches the ACPI used by the non-Chromebook
version of the Dell Latittude 7410 (which uses the same EC).
TEST=build/boot Win11 on google/drallion
Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows coolstar's Windows drivers to attach.
TEST=build/boot Win11 on google/drallion
Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Both Windows and MacOS get cranky if the Mutex synclevel is non-zero,
aborting any Acquire() call with Mutex param that has a non-zero
synclevel.
TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and
functional.
Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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While debugging lack of battery status under Windows, it was discovered
that the read/write flags in the args to the EC RAM 'ECRW' method were
not being correctly identified. Force set them from the R() and W()
methods which call ECRW() so those calls are processed properly.
TEST=build/boot Windows on google/drallion, verify battery status,
charging, etc are all reported properly.
Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf
Signed-off-by: Coolstar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Early Chromebook generations stored the information about
USB port power control for S3/S5 sleepstates in GNVS, although
the configuration is static.
Reduce code duplication and react to ACPI S4 as if it was ACPI
S5 request.
Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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If the variable `mirror_flag_attempts` isn't accessible, or doesn't
have a value, don't attempt to mirror the EC.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia39b2ce4ffcb8db3a335449c8bdb0d5c8a28a52c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The EC should be mirrored (if it's out of date) unconditionally if
the board support Thunderbolt. Use DRIVERS_INTEL_USB4_RETIMER instead
of SOC_INTEL_COMMON_BLOCK_TCSS as it's more suitable.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I27b238d4d404746c9a70bacf8e60d9e0b0e1ccca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76579
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If the version of the EC firmware in coreboot doesn't match
the firmware that the EC is running, print the versions.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I55c09b8d5ffe8ca9135384c823d005b55cfd83d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76380
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch the TGL variant to use the "merlin" EC variant, and delete the
no longer needed "TGL" EC variant.
This is not a functional change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id4d305490b48c1c79ea52b0bbaa79b675412e0b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76332
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Switch the ADL variant to use the "merlin" EC variant, and delete the
no longer needed "ADL" EC variant.
This is not a functional change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I61e56cc95a26be60d7f10c89d26bce2d857ae81a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The UCSI mailbox isn't used, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I03587a2322b1f34fa26a5c2ba7906a4e1ae82ae0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Merlin was the name for the open-source variant of the EC. It
ended up getting entirely rewritten to work with SDCC, and is
currently being used on starbook/adl. The source code isn't
available at the time of this commit due to some old ITE XLT
code being used.
Add the latest version of the code, replacing the old code, so
the boards can be migrated over.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib8384fc9322058297e8219ac8e483ac37a70bd33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Tablet motion control is a function of the EC, and under Windows, the
TBMC device needs to be initialized after CREC, or driver init will
fail. The only way to ensure this happens is for TBMC to be a child
device under CREC.
TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers
loaded and orientation switching functional under both OSes.
Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Set the ACPI status (_STA) for the PD device enabled+visible, to allow
coolstar's Windows drivers for USB4/Thunderbolt to attach.
TEST=build/boot Win11 on google/drobit, install USB4/TB drivers, verify
USB4/TB ports are functional for PD and data at USB4 speeds.
Change-Id: I84a20cfaf7e077469f8361b3da3b031d9fd84134
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Set the ACPI status (_STA) for the EC ACPI to enabled+visible, to allow
coolstar's Windows drivers for the EC and keyboard backlight to attach.
TEST=build/boot Win11 on google/samus, install EC/kblight drivers,
verify keyboard backlight control functional.
Change-Id: I3e9578f1ef18b3bebb93a9ae2ae4e27bc38f648d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76790
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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System76 EC since system76/ec@9ac513128ad9 detects if the keyboard is
white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for
the selection and update the ACPI methods for the new functionality.
Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Split wait-loop for DP and HPD flags as below -
- google_chromeec_wait_for_hpd
- google_chromeec_wait_for_dp_mode_entry
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Wait for DP/HPD flags only in AP initiated mode entry
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5137c346fbf1edabc60a53e0978e32f54885c330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76369
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skip TCSS `wait_for_connection` for AP initiated mode entry.
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia04ff470961831237fe851f7ae3feaa5623d4b4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76368
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Skip TCSS `enter_dp_mode` command when there is no USB device detected
on the port.
BUG=b:247670186
TEST=Verify display over TCSS and its impact on boot time for
google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ie6cd84cab3631596d4d7178dae2040e25c621f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Resetting the device will cause the keyboard backlight and airplane LED
to lose their state.
Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75275
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Provide system76_ec_cmd() to send arbitrary commands to the EC.
Provide librem_ec_has_jack_detect() to probe for the jack detect fix.
Change-Id: Ic7bda0ce230a3ad68dfeb7b01a0e04f70dab9e5d
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74390
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Use ECRAM field MTNS to determine if motion sensor present, and set
TBMC device status accordingly.
TEST=build/boot google/{jinlon,drobit}, verify ACPI status for TMBC
correct for both devices with and without tablet mode.
Change-Id: Ic06ab6d721f0a3435e6dfd7b5e130f378096afec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Update the chromeec driver to use the EC host command API. Large blocks
of repetitive code to set up EC calls are replaced with single function
calls to perform the same operation.
BUG=b:258126464
BRANCH=none
TEST=booted on rex
Change-Id: I0317405b1ed0c58568078133c17c8cfbc7c21d80
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73325
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new util/chromeos/update_ec_headers.sh utility is used to update
ec_commands.h and introduce ec_cmd_api.h from the chrome EC repo.
ec_cmd_api.h is a new file from the chrome EC repo which defines the API
for communicating with the EC. It is a companion to the existing
ec_commands.h by defining functions corresponding to EC host command
opcodes and request/response struct definitions.
See $EC/docs/ec-host-command-api.md for details.
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
3e35858003 ec: Add another #line directive
The original include/ec_cmd_api.h version in the EC repo is:
59de61f2db zephyr: Add support for RNG devices
BUG=b:258126464
BRANCH=none
TEST=none
Change-Id: I30f20e34d31b7e19cf03f65fefd58ae64eef1d41
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73324
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add _HID to parent SIO device so Windows can find the PS2K, and
remove _ADR since HID and ADR are mutually exclusive.
TEST=build/boot Win11 on google/butterfly, verify keyboard functional.
Change-Id: I772ceef1b439cfd4e2740e53362bee9d494fb36d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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While Chromebook hardware originally would not have the
capacity to do suspend-to-disk (ACPI S4), the power management
code in EC should react to S4 request as if it was S5 request.
Change-Id: Ida9118919c8149d94f470847d0c4aad9c0b97d3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change the fallback value of the `fn_ctrl_swap` option to 0, which
is disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I76329ec59ba630c987a122bffb8045150facdf08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change the fallback value of the `fn_ctrl_swap` option to 0, which
is disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The EC will constantly update the battery variables approximately
every 60 seconds; they should be used unmodified, rather than
trying to change them.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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In the non-timeout case in recv_ec_data_timeout, a message like this one
will get printed at BIOS_SPEW log level: "recv_ec_data_timeout: 0x00".
The "timeout" part of the function name corresponds to what the function
does, but the message will only be printed when not running into the
timeout which is a bit misleading and might suggest a problem when there
is none. To avoid this possible confusion, don't use the function name
in the printk, but use "Data from EC:" instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I521f67517f64fc64e24853d96730c3f9459f1ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74381
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e.
Add multiple fan support for dptf policies.
This also fixes the Google Meet resolution drop issue as per
b:246535768 comment#12. When system starts Google Meet video call,
it uses the hardware accelerated encoder as expected. But, as soon as
another system connects to the call, an immediate fallback is observed
from hardware to software encoder. Due to this, Google Meet resolution
dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC
based fanless platforms. This same issue was not seen on fan based
systems. With the fix in dptf driver where fan configures appropriate
setting for only fan participant, not for other device participants,
able to see consistent 720p resolution.
BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alder Lake-P Redrix system for two fans
support and on Alder Lake-N fanless systems. With this code change
Google Meet resolution drop not observed.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With CB:16732, EC can provide default lid switch implementation(LID0
ACPI device). Up until that point, mainboard has been providing default
switch implementation. When EC provides lid switch implementation, the
lid switch state is read from EC either through MMAP or LPC interface.
Hence there is no need to keep mainboard's LIDS ACPI object in sync with
EC's lid switch state. Use only EC's lid switch state on boards using
EC's implementation. This paves the way to remove LIDS ACPI object on
those mainboards.
BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Trigger lid open/close
events and ensure that they are detected properly through
/proc/acpi/button/lid/LID0/state.
localhost ~ # cat /proc/acpi/button/lid/LID0/state
state: open
localhost ~ # cat /proc/acpi/button/lid/LID0/state
state: closed
Ensure that the system behaves as expected based on powerd
configuration. After signin, system suspends/resumes for lid close/open.
On signin screen, system shuts down/boots for lid close/open.
Change-Id: I013574d7c21761f167ad38aeed27a419677b8000
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.backlight_enable = 0x01,
^~~~
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.dock_event_enable = 0x01,
^~~~
Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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When enabled, the EC will mirror the firmware contained inside the
coreboot ROM. This allows it to be updated at the same time as
coreboot.
Enable the mirror flag if the installed EC firmware does not match
the target version or if a CMOS option, "manual_mirror_flag" is
set.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I377abbb37dc4d3e535e518a73e73969b25967daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This reverts commit b42ca4d0b2fafe7214396d30a1a833ac33cf85bc.
Reason for revert: The mirror flag "0x01" is mirror once, which
relies on the EC remembering that it's been mirrored. However, the
EC forgets this if it's been without power for 20 minutes or so.
Even if power is connected then, it'll instantly try to mirror and
it can't charge whilst doing it. It can either result in
incomplete EC firmware, or a loop where it's constantly trying to
mirror.
Change-Id: I79da9143cc63459e7e29431eff2cb14200424b37
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move the implementation of smbios_system_wakeup_type from the mainboards
to the EC for all models that use System76 EC (everything except KBL).
Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE.
Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when
body detection changed between lap/desk mode. However, that event is a
wake event, which resulted in spurious AP wake events being triggered
when the EC detected lap/desk mode changes while the AP was suspended.
To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was
added, which will not be a wake event. This CL adds handling for the new
event to acpi/ec.asl to switch DPTC tables when a change is detected.
BRANCH=none
BUG=b:261141172
TEST=bodydetectmode on|off, verify host event is received
Change-Id: Iabeb7891489a209f45504804355f1fa817082976
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update ec_commands.h from the EC repo at:
"8441cf4 Add host event: EC_HOST_EVENT_BODY_DETECT_CHANGE"
This is an exact copy of the EC repo's ec_commands.h with the
exception of updating the copyright message.
BUG=b:261141172
BRANCH=none
TEST=built coreboot for skyrim
Change-Id: I9892c0c3518f63d357459861e8fa1b7f5f494e68
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73258
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I150a4ed94bcaead6eb45f1c4b4952ae6957e0940
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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