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2014-09-19chrome ec: Add support for limiting charger currentDuncan Laurie
Update the ec_commands header (direct from EC source) and add support for the new charger current limit interface which will be used by DPTF. Change-Id: Ia9a2a84b612a2982dbe996f07a856be6cd53ebdb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/185758 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1fcca2d75856ecefd3aeb1c551182aa76d649466) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6925 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-12ec/lenovo/h8: return correctly typed package if battery is absentVladimir Serbinenko
Fixes "Discharge rate invalid message" and fwts error. Change-Id: I51f9d819f164552567d75f83c95ba7523e97343e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6793 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-30smbios: reorganise OEM strings handling.Vladimir Serbinenko
OEM strings should not be handled by mobo code but by common code with strings collected from all devices. Change-Id: Ibde61a1ca79845670bc0df87dc6c67fa868d48a9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6788 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-08-30ec/lenovo/h8: Implement thinkpad-acpi compatible LED functionVladimir Serbinenko
Change-Id: I9998b0b4a1413ab65f1dbdf59b2f84d331ce9c3d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30ec/lenovo/h8: Rename LED to avoid conflicting with thinkpad-acpiVladimir Serbinenko
Change-Id: I9fd7f894d0e611f61e8702e4eacb12d7b81154d8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6789 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30lenovo/h8: Support tablet eventsVladimir Serbinenko
_QXX numbers are determined experimentally, hotkey scancodes from thinkpad-acpi module. Change-Id: I1f7548ef62529ae25dcdcbed0fc74390b7529a2e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6765 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-23ec/lenovo/h8/acpi/systemstatus.asl: Fix typo in o*n* in commentPaul Menzel
Change-Id: I655536f64faaa7e1600d4fec62ba80730e2cc45a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6674 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-13lenovo/h8: Support uwb radio.Vladimir Serbinenko
It's the third minipcie slot in x200. Change-Id: Ibfa8d787698cd23b4abcffe5cff2d62039cf0f86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6641 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-13chromeos: On ARM platforms VBNV lives in the ECStefan Reinauer
This patch renames the x86 way of doing things to explicitly mention CMOS (which is not available on our ARM platforms) and adds an implementation to get VBNV through the Chrome EC. We might want to refine this further in the future to allow VBNV in the EC even on x86 platforms. Will be fixed when that appears. Also, not all ARM platforms running ChromeOS might use the Google EC in the future, in which case this code will need additional work. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901 Reviewed-on: https://chromium-review.googlesource.com/167540 Reviewed-by: David Hendrix <dhendrix@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6616 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-11lenovo/h8: Remove useless smi.h include.Vladimir Serbinenko
It's not really used. Change-Id: I760d5a4cbe46d17ef37ea34e29eecdb0721cb945 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6588 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-08chromeec: Implement full battery workaround at 6%Duncan Laurie
Currently the workaround for indicating a "full" battery kicks in at 3%, but this turns out to be too high for some devices. So move the workaround start point to 6% from full, or 94%. Change-Id: Ib4305df3a68e89f3a10a096d0e89d8105ea9037b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 982dc496a0553c90dee56fda6411b7c21a5d7da9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6521 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-04chrome ec: Add Methods for new EC eventsDuncan Laurie
The EC recently added events for Thermal and Battery shutdown to provide some sort of notification to the OS that it is about to pull power. Original-Change-Id: Ibbdb5f11b8fa9fc80612a3cc10667c612420b1bb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@google.com> (cherry picked from commit 03a53ed5e58caa018d49df193510d95bdf5bed7b) Change-Id: I0cdf89a60b541840029db58d49921340e7ab60eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16d00848f48da83f6d6c813137a35af45bb05c4b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-29ec/lenovo/h8: Apply ME workaround on X230 on S3 resume.Vladimir Serbinenko
This makes S3 work. Change-Id: Ife14372f5f9bb151d7e6e98c6069eb99d5369baf Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6392 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-23src/.../Kconfig: various small fixes to textsDaniele Forsi
Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25src/ec: Sanitize headers and comment #endif pairingsEdward O'Callaghan
Comment #endif /* FOO */ pairings. Alphabetise headers and remove any #if CONFIG_ guards around them. Background rational: Remove guarding the inclusion of headers based on CONFIG_ options. This *potentially* could hide issues such as functions being swapped from under our feet, since different runtime behaviour could be declared with the same function same name and type-signature. Hence, depending on the header we happen to get may change runtime behaviour. Change-Id: Ic61bdfb64d99f0e2998c6451ae6686915b7bb3d4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6059 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-13chromeec: add function to reboot on unexpected imageAaron Durbin
It's helpful to have a generic function that will tell the EC to reboot if the EC isn't running a specified image. Add that and implement google_chromeec_early_init() to utilize the new function still maintaing its semantics of if recvoery mode is enabled the EC should be running its RO image. There is a slight change in that no communication is done with the EC if not in recovery mode. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Built and boot with recovery request. Noted EC reboot. Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182060 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5039 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Fix temperature calcualtion in PATx methodsDuncan Laurie
The PATx methods will be passed a temperature in deci-kelvin, so it needs to be converted back to kelvin before being sent to the EC. The PAT disable method is changed to take the temperature ID as an argument so individual sensors can be disabled. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and esif_uf userspace application. Start and stop DPTF and see that temperature thresholds are set to sane values. Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: call DPTF thermal threshold event handlerAaron Durbin
When an EC thermal event occurs call the DPTF thermal threshold event handler to handle notifications. Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Update header and add functions to support DPTFDuncan Laurie
The EC now supports two auxiliary programmable trip points for thermal monitoring. These are expected to be used by DPTF and need to be exported. In order to support these the header was updated from the latest chrome ec source. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13src/*: Remove the last remnants of struct keyboardEdward O'Callaghan
Change-Id: I7d0e8d2119a470428cfc01c0738b8988ab75ba2d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5624 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13src/drivers/pc80: Remove empty struct keyboardEdward O'Callaghan
This is a empty struct that has propagated through the superio's & ec's but really does nothing. Time to get rid of it before it adds yet more cruft. However, since this touches many superio's at once we do this in stages by first changing the function type to be a pure procedure. Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5617 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-09baytrail: Basic DPTF frameworkDuncan Laurie
This is not complete yet but it compiles and doesn't cause any issues by itself. It is tied into the EC pretty closely so that is part of the same commit. Once we have more of the EC support done it will need some more work to make use of those new interfaces properly. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: I4b27e38baae18627a275488d77944208950b98bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179459 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-01Declare recovery and developer modes outside ChromeOSKyösti Mälkki
Move the implementation for recovery and developer modes from vendorcode/google/chromes to lib/. Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-19ec/compal/ene932: Update to use coreboot EC-mainboard APIAlexandru Gagniuc
This patch implements a simple interface between the EC and mainboard ASL code. This interface does not rely on the preprocessor, and prevents name conflicts by scoping the interface methods. As this interface is documented on the coreboot wiki, an in-tree documentation is not provided. Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5515 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-12ec/compal/ene932/acpi: Let mainboard define the ACPI lid objectAlexandru Gagniuc
The GP15 ACPI object was used to get the state of the lid. However GP15 is specific to certain Intel chipsets, and will not always be in the ACPI namespace. Instead of hardcoding this object, let the mainboard define it. Also, document the ACPI interface for the EC. Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5444 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-09ec/compal/ene932/ec.h: Include stdint.h for definition of 'u8'Alexandru Gagniuc
Change-Id: I7ffa8e8f807e7d8a778eb80c12a0dc984bdb3f8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5470 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-03-01lenovo/x60: Unify volume button handling with common code.Vladimir Serbinenko
Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5099 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-30chromeec: allow override of i8042 interruptAaron Durbin
Some boards need to override which IRQ the i8042 keyboard controller has its interrupt on instead of the default IRQ#1. The SIO_EC_PS2K_IRQ macro provides the mainboard an ability to override the interrupt location. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi using this option. New IRQ is correctly picked up by kernel allowing keyboard support. Change-Id: Ic2b222018dfc3aa30e24a31009e832ae0fb7e9cf Reviewed-on: https://chromium-review.googlesource.com/177222 Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4978 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30chrome ec: Fix ASL to use IO() instead of FixedIO()Duncan Laurie
FixedIO seems like a nice short version of IO but in reality it is limited to 10-bit ISA addresses and so should not really be used in most situations. Change all the references to use IO() directly instead. BUG=chromium:311294 BRANCH=none TEST=emerge-samus chromeos-coreboot-samus and check for iasl warnings using updated iasl compiler revision 20130117. Boot the imge and ensure that EC regions are still exported in /proc/ioports. Change-Id: I54de65892bed9e43dbba916990cf2b70c370843c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174810 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4910 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-12acpi/ec: Add missing delaysVladimir Serbinenko
Without these delays on fast systems like X230 the port is read before it's updated. Change-Id: I3e01fc348cc5170cec108a05095ba301055ed6b0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4617 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Add backlight control.Vladimir Serbinenko
Change-Id: I773793bf53d91ae787bd0d0ae7bd882243196d56 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4678 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Make trackpoint enable a CMOS option.Vladimir Serbinenko
To be consistent with touchpad counterpart. Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Remove trackpoint_enable from device tree.Vladimir Serbinenko
Change-Id: I6652e0ad4e0179950f775bbd0200484907bfc976 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: make wlan config a CMOS optionVladimir Serbinenko
To stay in line with wwan and bluetooth. Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Allow control of low-battery beep.Vladimir Serbinenko
Change-Id: I2f422e83f2afcf0cc3f3ecbace01a8f4f39e87d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Allow user to disable powermanagement beeps.Vladimir Serbinenko
They're pretty annoying. Change-Id: I44d26dc168927a9cedfd6ecc4c9a51a3a7b362c7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Implement sticky Fn option.Vladimir Serbinenko
Useful for accessibility. Sticky modifier (sticky Fn) is a behaviour of modifier key when you don't have to hold it pressed to achieve the result. E.g. with normal Fn brightness up is: <Press Fn> <Press Home> <Despress Home> <Depress Fn> With sticky Fn you can do: <Press Fn> <Depress Fn> <Press Home> <Despress Home> Change-Id: I4da5adcea02428d936023891de08684cae77c44e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4661 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Add an option to swap ctrl and fn.Vladimir Serbinenko
Tested on my X201 and X230. Change-Id: I3c7ec65681157d15c6e87eea64779a08e03ae5a8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree.Vladimir Serbinenko
wwan_enable was never used. wlan_enable isn't something for device tree but for CMOS config if at all. Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4651 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10Replace all occurences of sprintf with snprintfVladimir Serbinenko
THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-21chromeec: Add event methods for EC requested throttleDuncan Laurie
Two new events possible from the EC for starting and stopping throttle. These are handled in a per-board method that is defined under the thermal zone. This is not quite where I wanted it but the scoping rules in ACPI don't let me have a defined external object in the same scope. Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63988 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4415 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-19ec/lenovo/h8: Enable 3G modemVladimir Serbinenko
Just like bluetooth and wlan it need to be enabled in EC. Set the appropriate bit in EC if CMOS config says so. Change-Id: Ia48ca3201f013d3b4c4153f32ff536e06b6a2f6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4516 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-15ec/lenovo/h8: Fix peripheral init without CMOS configVladimir Serbinenko
Currently H8 skips important init if unable to access CMOS config. Change default to enable all features to have a sane system without using CMOS config. Change-Id: I4448ccd21beae8ad23eb22391770c6fe3b83e3b4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4515 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-12chromeec: Allow get_board_version to be called from romstage.Shawn Nematbakhsh
We will soon need to call google_chromeec_get_board_version to determine correct DDR SPD. We must do so before DDR is initialized, so allow this function to be called from romstage. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I882d84e38d11bf66067193a6f408f941f2cf8a81 Reviewed-on: https://gerrit.chromium.org/gerrit/61191 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4351 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Introduce a config whether dock is inited in romstage or notVladimir Serbinenko
Instead of depending on exact mobo configure general characteristic whether dock is configured in romstage or ramstage. X60 and T60 have superio in dock so it needs to be inited to get serial, so it should be inited in romstage. On X201 there is nothing useful that early in boot but it's needed to init more to get dock working, in particular EC init needs to be done first. Change-Id: If5072e3dec883a94cd2d5643a92f7f6c3c9feee9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4294 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02EC H8: remove dependence on IS_X201Vladimir Serbinenko
Instead define brightness up/down function and gfx device and use preprocessor magic to glue it together. Change-Id: I03074ae07b33c1546d229efc3e80606ddbee6300 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4282 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-12-02global: Fix usage of get_option() to make use of CB_CMOS_ codesAlexandru Gagniuc
Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02ec/lenovo/h8: Add h8_build_id_and_function_spec_version()Peter Stuge
The function reads the Build ID and the supported function specification version from the running EC firmware, and stores a text representation in the provided output buffer. Change-Id: I3b647d7f315c9b4922fa9a9c5167a80f6d82e753 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3617 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-01H8: Move EC GPE declaration to mainboardVladimir Serbinenko
Change-Id: Iefc481f09268dd15bbc3cbfa8bdd110d44383f6a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4281 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25Add declaration of dock registers 1, 2 and 3.Vladimir Serbinenko
Needed to make dock work on X201. Change-Id: Id0b32266cacf04bb48530bedf50818c268f947ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4081 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-11-24Lenovo hotkeys supportVladimir Serbinenko
Implement proprietary lenovo ACPI hotkeys Change-Id: I36a6d3a280b0ac76d9ea063cdc10197a57e306f9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4055 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-23Change EC GPE on X201Vladimir Serbinenko
X201 has GPE at 0x11 (17) instead of 28. Tested on X201. Change-Id: Ib6306e6f085c4f6811df0789aa402a0d6901ed13 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4053 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-23Call X201 dock hooks in EC codeVladimir Serbinenko
Unlike on X60/T60 dock has to be inited at the same time as EC. Change-Id: If6eb3140c871859ce99027a50908f72bcc560243 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4082 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-29ec/kontron/it8516e: Add sanity checks for values from nvramNico Huber
Change-Id: Ie52d80fc8657064efdcec51c31dc9309fcc28121 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3787 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29ec/kontron/it8516e: Comment low-level EC functionsNico Huber
Change-Id: I5f75998356554e08f8c9920e7612494e4710ab15 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3786 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29ec/kontron/it8516e: Remove some unsafe bit shiftingNico Huber
The EC expects the temperature in 64ths degree C. Alter it8516e_set_fan_temperature() to just export this interface and make the calculation more obvious. Change-Id: Ibe241b7909f4c02b30b1e1200a1850d47695a765 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3785 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-29ec/kontron/it8516e: Add PWM limits optionNico Huber
Add an option to set minimal and maximal PWM percentages when the fan is in temperature controlled mode. Also fix a non-ascii flaw. Change-Id: I85ae244bee2145bf17d6c29e93dd4871540985c8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3774 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29ec/kontron/it8516e: Correct fan setting for PWM modeNico Huber
The EC firmware expects a 255th while we provide a percentage. Change-Id: Ib06a061b431ac728329043179800729e39e6166b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3773 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29ec/kontron/it8516e: Add option for external temperature sensorNico Huber
The IT8516E firmware of Kontron supports some selected external sensors attached to the EC via SMBUS or GPIO16. Change-Id: I4c451c360a393e916430e3bea04a95847455cef7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3772 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-10chromeec: Add a function to send passthrough i2c messages.Gabe Black
Change-Id: I576d0dbf65693f40d7d1c20d3d5e7a75b8e14dc9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/3752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/google: Support ChromeOS EC on SPI bus.Hung-Te Lin
For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface (see spi-generic.h) to exchange data. Note: Only EC protocol v3 is supported for SPI bus. Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/google: Support Chrome EC protocol version 3.Hung-Te Lin
Add the new Chrome EC protocol version 3 to Coreboot. Note, protocol version 3 is not applied on any bus implementations yet. LPC (x86) and I2C (arm/snow) are still using v2 protocol. The first one to use v3 protocol will be SPI bus (arm/pit). LPC / I2C will be updated to v3 only when they are ready to change. Change-Id: I3006435295fb509c6351afbb97de0fcedcb1d8c4 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3750 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/google: Generalize communication protocol support in EC drivers.Hung-Te Lin
Since EC protocol v3, the packet format will be the same for all buses (inclding I2C, SPI, and LPC). That will simplify the implementation in each individual bus driver source file. To prepare for that, we will move the protocol part into crosec_proto.c: crosec_command_proto, with bus driver in callback "crosec_io". Change-Id: I9ccd19a57a182899dd1ef1cd90598679c1546295 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3749 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec/chromeec: Merge upstream V3 structure and constant definition.Hung-Te Lin
Chrome EC protocol V3 has several new command structure and constants defined. Simply cherry-picking changes from upstream. Change-Id: I7cb61d3b632ff32743e4fa312e0cc691c1c4c663 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3748 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec: Reserve correct ioport regions for Chrome OS EC to useBill Richardson
The LPC-based ChromeOS EC uses several ioport regions to communicate with the AP. In order for the new unified userspace access method to work, we need them to be reserved by the BIOS. Before /proc/ioports shows: 0800-0803 0804-08ff We'd like just a single 256-byte region at 0x800, but ASL can't handle that. So this will work: 0800-087f 0880-08ff Change-Id: I3f8060bff32d3a49f1488b26830ae26b83dab79d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/3746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10slippy/falco/peppy: Enable SERIRQ continuous modeDuncan Laurie
The Chrome EC still does not tolerate SERIRQ in quiet mode and so the keyboard does not work properly. Change-Id: I9ab052187c9926ce0e2c86b86dfe987dd6564c1b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec: Add romstage function for checking and rebooting ECDuncan Laurie
Now that we are executing VbInit() in coreboot we can end up in a situation where the recovery reason is consumed during VbInit (end of romstage) and then the EC is rebooted to RO during ramstage EC init, thereby losing the recovery reason. Two possiblities are to remove the EC check+reboot from ramstage and let it happen in depthcharge. This however means that the system has to boot all the way into depthcharge and then reboot the EC and the system again. Instead if we do a check in romstage before VbInit() is called then we can reboot the EC into RO early and avoid booting all the way to depthcharge first. This change adds a ramstage version the EC init function and calls it from the shared romstage code immediately after the PCH decode windows are setup. Change-Id: I30d2a0c7131b8e4ec30c63eea36944ec111a8fba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3744 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10chrome ec: Update EC header from EC repositoryDuncan Laurie
- Updated ec_commands.h is copied in directly from EC repo - Removed "old" interface and update resources for "new" interface - Updated temp sensor constants and added "not calibrated" - Update mainboards to remove check for EC_SWITCH_KEYBOARD_RECOVERY Change-Id: Ic93c1914f86b6f5bc224178270624ed92b5c1e15 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec: Remove hardcoded GPI offset in EC SCIDuncan Laurie
With LynxPoint-LP the SCI GPE is no longer a GPIO that is offset by 16. Remove the Add and fix up the link definition so it is still accurate. Change-Id: I091141183a09345b5ffe28365583e48019f9f5e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec: Fix spellingMartin Roth
Change-Id: I5e4d35572c43f07bec5ec0bcd75c717723228e2f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3757 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ChromeEC: Fix the default, depends for EC_GOOGLE_CHROMEEC_I2C.Gabe Black
The default for this variable should be n, it should only depend on EC_GOOGLE_CHROMEEC, and it should be (and is) explicitly enabled when needed. This prevents it from being turned on when the EC bus is SPI. Change-Id: Idc6651a764be4f055341a36b9b4a58990f050b0c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3737 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-08Revert "Radio and dock support in EC on X60 and X201"Peter Stuge
This reverts commit 7d1ebbff5ad224591a2d1972737611f96a13145c Change-Id: I4a9d0cd31a3df3d1e092193953f334697ca65167 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/3616 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-17pnp: Unify some alignment to ease autogenerating patchesNico Huber
Most PnP drivers align the initialization of their `device_operations` with spaces. Unify this, so next autogenerated patches always match the alignment. Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Avoid tripping overheat alarm on X201 before ME bootsVladimir Serbinenko
Until ME boots (which takes seconds on X201) the reported temperature is 128 °C which triggers Linux overheat alarm which shuts down. Pretend temperature is 40°C until ME boots. Change-Id: Ia49fa03c6eb27f539a23711f2c8ebfde72b1dc18 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3404 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Make acpi/ec.c usable in romstageVladimir Serbinenko
On X201 to enable EHCI debug you need to go through EC if USB power is disabled so we need to inclue ec.c. Change-Id: I8f8b7de639ecaebceaa53cd338136befaeec8214 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3405 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12Radio and dock support in EC on X60 and X201Vladimir Serbinenko
Enable UMTS on Lenovo X60 and X201. Enable radios if no options are available. Enable dock on Lenovo X201. Based on my X201 branch. Change-Id: I6e8d3bbd6a6b1a8e59473dd5cc8125a1583d75df Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/3377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-06ec/acpi: Add ACPI methods for generic EC accessNico Huber
Port most of the functions found in ec/acpi/ec.c to ACPI Source Language (ASL). These functions are used to control embedded controllers with the standard ACPI interface (mostly through i/o ports 0x62 / 0x66). The following methods are implemented and tested against the power managements channels of a ITE IT8516E embedded controller: * WAIT_EC_SC Wait for a bit in the EC_SC register * SEND_EC_COMMAND Send one command byte to the EC_SC register * SEND_EC_DATA Send one data byte to the EC_DATA register * RECV_EC_DATA Read one byte of data from the EC_DATA register * EC_READ Read one byte from ec memory (through cmd 0x80) * EC_WRITE Write one byte to ec memory (through cmd 0x81) To use the provided methods, one should include `ec/acpi/ec.asl` in the EC device code. Prior doing so, two macros should be defined to identify the used i/o ports: * EC_SC_IO I/o address of the EC_SC register * EC_DATA_IO I/o address of the EC_DATA register Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3285 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-06-06ec/kontron/it8516e: Add it8516e EC driverNico Huber
This driver communicates with the IT8516e on the Kontron KTQM77. Since we don't know if the firmware and protocol are standard for the chip or customized to the board, call it kontron/it8516e. Change-Id: I7382172c6d865d60106c929124444821a07a5184 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-18ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOTStefan Reinauer
This used to contain the path for the EC include files, but those files are included in coreboot now. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369 Reviewed-on: https://gerrit.chromium.org/gerrit/47606 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3057 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16ec/google: Move plug-n-play initialization to LPC protocol.Hung-Te Lin
"Plug-n-play" is not supported on all platforms using Google's Chrome EC. For example, EC on I2C bus will need explicit configuration and initialization. So move the plug-n-play initialization to the LPC implementation. Verified by building Google/Link (with EC/LPC) successfully. Change-Id: I49e5943503fd5301aa2b2f8c1265f3813719d7e3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3089 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-16ec/google: Support Google's Chrome EC on I2C interface.Hung-Te Lin
Google's Chrome EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3074 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12ec/google: Isolate EC bus protocol implementation.Hung-Te Lin
The Chrome EC can be connected by different types of bus like LPC / I2C / SPI, and the current implementation is only for LPC. To support other types, we must first isolate the LPC protocol stuff and add configuration variable (EC_GOOGLE_CHROMEEC_LPC) to specify bus type. Verified by building google/link (with chromeec) configuration successfully. Change-Id: Ib2920d8d935bcc77a5394e818f69e9265e26e8a0 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3068 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14Support ITE IT8518 embedded controller running Quanta's firmwareStefan Reinauer
Change-Id: Ib406b9d5005243d79eea5d2c0c6c86b5aa949891 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2721 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-22Add support for Google ChromeECStefan Reinauer
Google ChromeEC is an EC with completely open source firmware. See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary for the EC firmware source code (aka more information about the ChromeEC) This patch adds support for the ChromeEC on coreboot's side. Great thanks to the ChromeEC team for this amazing work. It's another important milestone towards a free and open firmware stack on modern hardware. Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2481 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-11Add support for "Butterfly" ChromebookStefan Reinauer
We're happy to announce coreboot support for the "Butterfly" Chromebook, a.k.a HP Pavilion Chromebook. More information at: http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html This commit also includes support for the ENE KB3940Q embedded controller running on Quanta's firmware. Change-Id: I194f847a94005218ec04eeba091c3257ac459510 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2359 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2012-12-12Add support for ENE932 EC w/ Compal firmwareStefan Reinauer
Change-Id: I19b03139e7edfee6ff3e0bcef735bb36bfadc354 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2024 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-04Make the device tree available in the rom stageStefan Reinauer
We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1398 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02Add EC component for SMSC MEC1308/1310Stefan Reinauer
Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/828 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-31X60/T60: Add option to enable/disable bluetoothSven Schnelle
Change-Id: I9761a8a9a7cc708fe95169cb8b79b413b97ee523 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/598 Tested-by: build bot (Jenkins)
2011-12-14Lenovo X60/T60: add first_battery settingSven Schnelle
The EC allows to select the order in which batteries are (dis)charged. Make this setting available to the user. Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/475 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-25Lenovo H8: Fix h8_set_audio_mute()Sven Schnelle
Logic is inverted (if argument is true, one would expect that mute is enabled) and the wrong bit was used (1 instead 0) Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/334 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-20T60: Add support for Ultrabay Legacy I/O devices (40Y8122)Sven Schnelle
Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/282 Tested-by: build bot (Jenkins)
2011-08-19Lenovo H8: Always clear audio muteSven Schnelle
The mute bit is set by ACPI before poweroff/going to suspend. So clear it after resume, to have working volume control even if the ACPI doesn't clear it on resume. OSPM should control Audio mute with ec bit 0x30:6, so it is safe to clear this bit even if the user has audio muted. Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/162 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
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