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Remove the ubtc.asl as it's no longer needed.
Change-Id: I8564bb7d9bd94c8303c543c078bc76192539c5f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80484
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These entries no longer exist as they are stored in CFR.
Change-Id: Ia85855fddc36db76a65490a1d685e1943db28b74
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The UCSI mailbox isn't used, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I03587a2322b1f34fa26a5c2ba7906a4e1ae82ae0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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The EC will constantly update the battery variables approximately
every 60 seconds; they should be used unmodified, rather than
trying to change them.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EC values will be changed when entering S3, S4 or S5, so move
the function that stores the current settings outside of logic
that restricts it to S4 or S5. This means the state isn't lost
when entering S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia007a8ad9c08a309489e9f64f1ed311858bfcd10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use ECWR function, instead of writing raw values to emem, to avoid a
lack of syncronisation as it uses a mutex.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I90cfd3e1752fe25493bd72ea6bcab1fd9318d2e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I40dc78c743f4201a11ea0c26a8af716cab42b805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I93444cdb96eaf729630b48551d0853511b584634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iabeec47bf492b698f95d86aa2d08ba9caedd75f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.
Switch argument will store the correct value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic2a83df9a270de6d7bab295e732a6c13accbe17c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.
Switch argument will store the correct value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I62e0fc3b6fcae72f2d8eacf37a390b4e4b1f0783
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62605
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current code will read the raw value from the EC, which doesn't
match the respective setting in CMOS.
Switch argument will store the correct value.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62604
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id64d321846dc042d4092d39ce9598d028ab15ed0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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When entering suspend, ACPI support is disabled by setting OSFG to 0x00.
This has been moved to be the final action, so it is after saving the
current EC settings.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5705efab42d2fe0fd5abc6c17eeea46ead27db17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Use ECRD function, instead of getting raw values from emem, to avoid a
lack of syncronisation as it uses a mutex.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I31113ef9af3a1e171e3e1f226e7adcfa0fbce61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design
Capacity), only report the design capacity. This handles cases where
the battery calibration is incorrect, and the battery runs out before
the OS thinks it's empty.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e965513d5888398834cab8c8445e97372f2b115
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Currently, the settings from CMOS were written to the
EC, which was pointless.
Now, when suspending, the EC values are stored in CMOS
when suspending and subsequently restored when waking.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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End all CMOS variable with a C and EC variables with an E.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie0fab6b9dcd805f7b8c9bf8f14b0a799d8f396c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Convert EC_GPI_SCI to Kconfig option with default value of
0x50 that is used by most boards.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Replace `Index (FOO, 0)` with `FOO[0]`.
Change-Id: I88cb974ed808b602a9398c9c3e363cb145420528
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: I4f8b71c90f0c56fdb29c4d2e9a2a737f704f3265
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Built with BUILD_TIMELESS=1 and coreboot.rom remains identical.
Change-Id: Ib59cba7bf553e8323c20fd9aa3474f3ecccf465a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add EC support that supports different Q Events and EC memory.
Created from the ITE IT5570E and IT8987E datasheets, all using
data port 0x4e.
Tested with Ubuntu 20.04.3 and Windows 10 on:
* StarBook Mk V (TGL + IT5570E):
* ITE Firmware 1.00
* Merlin Firmware 1.00
* LabTop Mk IV (CML + IT8987E):
* ITE Firmware 1.04
* LabTop Mk III (KBL + IT8987E):
* ITE Firmware 3.12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58343
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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