| Age | Commit message (Collapse) | Author |
|---|
|
Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The name LEDLOGO comes from schematics. It's the red indicator, embedded
in the dot of the 'i' of the ThinkPad logo on laptop's lid.
In vendor firmware, this led starts fading in-and-out, or, in other
words, pulsing, when laptop is put to S3. It helps to determine whether
the laptop is in S3 just by taking a look at the logo.
As of now, coreboot doesn't do anything with this particular indicator,
it's always in enabled (on) state, which is not very convenient.
This patch fixes it.
Tested on T440p.
Change-Id: I85fb69c8c1bed8635a1b31e9b8385c7036bb46dd
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80437
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic060f3605cd18d4bf774573c21957f626f984e2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80069
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I926ec4c1c00339209ef656995031026935e52558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Building the Lenovo T60/T60p, iasl 20230628 shows the remark below:
dsdt.asl 2099: PowerResource (FPwR, 0, 0)
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR)
dsdt.asl 2118: Name (_PR0, Package () { FPwR })
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR)
Address it by making it all upper case.
Change-Id: Ia7924b015e76c43818d2d82da35ce0013d721c26
Fixes: 3ab13a8691cb ("ec/lenovo/h8/acpi/thermal: Add support for passive cooling")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79367
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use 'sizeof(ecfw)' instead of 'sizeof ecfw'.
sizeof operator should only be used for types and variables require sizeof().
Change-Id: Ifae1680917bb0ce610e6ba753741aae233a71103
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
This to fix following error using Clang-16.0.0:
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.backlight_enable = 0x01,
^~~~
/cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion]
.dock_event_enable = 0x01,
^~~~
Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where
possible.
Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace `ShiftLeft (a, b)` with `a << b`.
Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace `ShiftLeft (a, b, c)` with `c = a << b`.
Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was
simplified to just `a >> b`.
Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Replace `Or (a, b)` with `a | b`.
Change-Id: I73842cd4843ebb0b48440059ae9dcf6c82235a76
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70845
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Replace `Store (a, b)` with `b = a`.
Change-Id: I1c68816f47aa3ed0ab3bf55d4cfde71d5838d051
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Replace `LLessEqual (a, b)` with `a <= b`.
Change-Id: I76855f9d4564fc08cd70456e2a0b1514cd73e35f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70620
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie5355e05982b372ef69515cfa081e2afbc7b09fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0
syntax") mixed up boolean and bit-wise operators while replacing Not()
with ASL 2.0 syntax. Thus, fix that.
Built dsdt.aml of lenovo/x230 and differs, but it remains the same when
this commit is applied after commit 37a89d519d4e.
Change-Id: Ifa848aafb5480acaac4fabffcf90a3dbf5248e43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66380
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Having to use a runtime configurable option backend like CMOS just to
specify the value of the "fn_ctrl_swap" option is annoying. Introduce
a new Kconfig option to allow specifying the fallback value, which is
only used when the option backend cannot provide a value.
Change-Id: I00bb3cd60c443fc0c8adb82e8e0c436dfc5de24b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67836
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This makes coccinelle script happy, everyone else sets flags last.
Change-Id: I80f421aeacb6e72fea2265c69cafb2a0d89e5616
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I8a0f18d37c065827a0f5b54f24ea1fcde497c504
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Change-Id: Id600bcb3fad35455adffe11a8105ad2590e83feb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `Multiply (a, b, c)` with `c = a * b`.
Change-Id: Idfc08803946cc2d4537db4be8d1bc07e48aa6fed
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LLessEqual(a, b)` with `a <= b`.
Change-Id: I256e56841e1c7037fe8ba5e9a963ad2301092325
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LNotEqual(a, b)` with `a != b`.
Change-Id: Ic114e097a08488106554ce2dec61fa219d7cf1d0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LGreater(a, b)` with `a > b`.
Change-Id: I1dbe6c325ed33a4dd15e4d6315b2308d8351974e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LEqual(a, b)` with `a == b`.
Change-Id: I49a7ed2d57124746815478f3ead8a8f7c54d048a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: Ia0550a115d75183cd72e478ae739731001febe22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Change-Id: I9f7c4bdd9299e686c375aced221a72994ef2d6ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Replace `LNot (a)` with `!a`.
Change-Id: I8de151e7df39a0282d032b8ca96c2d1b01014c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Replace `Subtract (a, b)` with `a - b`.
Change-Id: Id8fec71cc174008f48fc0a80c36942e6941982ac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: Ibbc0831e688b62d7ed0dec5e4b7224688ed0ae6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Replace `Subtract (a, b, c)` with `c = a - b`.
Change-Id: Ic38c60503fedaffc66153e103d40fda86781f9c8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Replace `LAnd (a, b)` with `a && b`.
Change-Id: Ic578506dd2a1ab4341361f1a3b435372f2dac260
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
|
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.
The volume field is only 8 bits long. Do not set the volume if it is out
of range. Also, use an out-of-range value as fallback to skip setting
the volume when it cannot be read using the option API, to preserve the
current behavior.
Change-Id: I7af68bb5c1ecd4489ab4b826b9a5e7999c77b1ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: Ie5cb54b171244be71848a59a788ed8d42b3e3161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The conversion to ASL 2.0 syntax in commit 81d55cf introduced a
regression triggering a BUG in Linux when reading the battery current.
Correct the wrongly-converted calculation.
Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0")
Tested-by: Andrew A. I. <aidron@yandex.ru>
Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52144
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: I1955390fcceeb42ecb644ac74541b7e9dd25320f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: I5691a582d9a195317994413fff4fd3273413b5fe
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Currently coreboot is using the ec hardware id IBM0068 for all
thinkpads, but for newer thinkpads the id maybe LEN0068 or LEN0268.
On Windows, the Lenovo Vantage app can't get battery details when using
IBM0068. This patch config this id by motherboard. The hardware IDs for
the following models can be found by searching for disassembled
dsdt.asl on vendor BIOS:
(But this info is not easy to find online. So I only changed some of
the thinkpads.)
T420:
https://github.com/tluck/Lenovo-T420-Clover/blob/master/EFI/CLOVER/ACPI/1600x900-EDID/DSDT.edid-2e2-hs.dsl
LEN0068
T430:
https://github.com/ThiagoSchetini/macosx-thinkpad-t430/blob/master/vanilla%20ACPI%20dsl's/DSDT.dsl
LEN0068
T520: Confirmed by Patrick Rudolph
LEN0068
W520: Confirmed by Patrick Rudolph
LEN0068
T530: Confirmed by Prasun Gera
LEN0068
W530: https://bugzilla.kernel.org/show_bug.cgi?id=66731
LEN0068
X230/X230T:
https://github.com/tuandzung/ThinkPad-X230-macOS-10.12.x/blob/master/DSDT/DSDT.dsl
LEN0068
T440p: https://github.com/doudou/t440p/blob/master/acpi/2.30/dsdt.dsl
LEN0068
Signed-off-by: Da Lao <dalao@tutanota.com>
Change-Id: I797080ec8ba7ce39d47fe587319f8f32d6938875
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Mainboard specific dock-init mechanism introduced
https://review.coreboot.org/c/coreboot/+/36093 works on most boards,
but https://ticket.coreboot.org/issues/256 shows that some boards
(e.g. x201 and t410) need communication with h8 EC to enable or
disable dock, (in dock_connect() and dock_disconnect() respectively)
so they must be done after the h8 EC is brought up, which is not
garanteed in the above mainboard specific dock-init mechanism.
This time, a hook function h8_mb_init() will be called at the end of
h8_enable(). (in place of the ancient h8_mainboard_init_dock() removed
in CB:36093) Its default implementation is a weak empty function, but
could be overrided with a strong one for boards needing to perform
actions which should be done after h8 EC is brought up.
This should fix the regression detected in
https://ticket.coreboot.org/issues/256
Change-Id: I3674fbfeab2ea2cd2a4453a8e77521157d553388
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It was always defined to the same value, and only used twice.
Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
h8_has_bdc() and h8_has_wwan() do not need to modify the device
structure. Hence, this change makes the struct device * parameter to
these functions as const.
This is being done in preparation to make struct device * parameter to
fill_ssdt as const.
Change-Id: Id3d65d2de7b5161b0e7cff26055c00d5dae967dc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40706
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch moves the code to control the ThinkLight to the common ACPI
folder for h8. This reduces code duplication and allows other ThinkPads
to include the same code for ThinkLight support.
Change-Id: I57de7516051bdcbb23fc21b4de352f265075893b
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and
the lock hotkey (KEY_COFFEE) on scancode 0x02.
On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2
and Fn-F3 are different from the default one so a new layout has to be
defined.
Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
All other messages in `ec/lenovo/h8` are prepended with *H8*, so also prepend
the EC version log message with *H8*.
EC Firmware ID 79HT50WW-3.4, Version 7.01A
No CMOS option 'usb_always_on'.
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN detection not implemented. Assuming WWAN installed
No CMOS option 'fn_ctrl_swap'.
Change-Id: Ib4f341946a336b57bd96c053a05364276caad1ac
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iabe55bfbc8e047c0791c21d162767081a181b6c5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37411
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Discussed in CB:36093, in the past many lenovo boards need to declare
an empty h8_mainboard_init_dock() to satisfy h8.c.
Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a
mainboard needs dock init (done with h8_mainboard_init_dock() in the
past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is
introduced) it can just do it in its own chip_ops.enable_dev function.
Tested on X200. Testing on other affected targets may be necessary.
Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested on Lenovo ThinkPad T440p.
Change-Id: I83dc2c19341475abeeacd374a1b6cf152ec9b497
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: Ib74c5c8cb9197fa06b2972cb96337fedd7f85b5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ifdb2dee08da45d698174583ee5ed44bf5a0243ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Fix a typo.
Change-Id: I2ab624eccd9bad36908df7fd739828e9ed8a4f62
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
|
|
IASL reports warning 'Control Method should be made Serialized'.
Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Use Fn-Key as recovery mode switch.
Tested using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.
Change-Id: I2c682431b3f09839db265259205104bd9ef4abfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
* Add function to wait for sense registers to become valid.
* Add function to retrieve Fn-Key state.
Tested on Lenovo T500:
* It takes about 700msec for the registers to become valid.
Tested on Lenovo T520:
* It takes less than 150msec for the registers to become valid.
Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
There are two known reverse-engineered ways to manage battery
thresholds.
This patch implements them and adds a way to enable them for
different mainboards.
Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11.
Works fine with new Linux userspace API for controlling battery
thresholds, available since 4.17.
(/sys/class/power_supply/BAT0/charge_(start|stop)_threshold).
The new API is supported by TLP (you might need to set NATACPI_ENABLE=1
in /etc/tlp.conf).
tpacpi-bat works fine too.
Signed-off-by: Alexey Kharlamov <der@2-47.ru>
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On my Thinkpad T420 the default 3000ms SeaBIOS timeout is too short,
it takes nearly 5000ms for my keyboard to become ready.
Timing out before it's ready leads to pretty bad behavior: I cannot use
my keyboard at all to control SeaBIOS, nor the subsequent GRUB instance.
Linux is fine though, possibly because it does its own keyboard init.
Signed-off-by: Michael Bacarella <michael.bacarella@gmail.com>
Change-Id: Id1681bf3921c8b5dc124d4c4e9072f146f84f3a2
Reviewed-on: https://review.coreboot.org/c/31279
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Re-write the UAO handling code as it had stopped working (#171)
(the flag was not getting read from the RTC properly in SMM)
Remove the SMM code as it's not needed (but EC flag won't be set
upon entering S3 now)
Set the EC flags on boot the same way other flags are set
Document bitwise operators for clarity
Propagate changes to other Thinkpads
(updated X201 to have 2 bits for the flag as it only had 1)
Per Nicola Corna's previous commits, 0x0d is set for "AC only"
"AC only" does exhibit different behaviour - the USB port is
turned on a few seconds after entering S3, rather than < 1 sec,
regardless of AC status
Tested on X220
Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: Iecc54e94484f5f11e0ba8ef6d1d844276e484b4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29886
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The pmh7 has at least a 9bit address space.
The h8s allows to access the 9th address space by using io port
0x15ed as second address register.
The pmh7 is connected via SPI to the h8s. The h8s is acting as
proxy to access the address space.
Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
|
|
Add CMOS option that allows to use both integrated and discrete GPU.
Tested on ThinkPad W530.
Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Make the code simpler and improve readability.
Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Store the power on defaults in the _REG method after the ERAM region
is ready for use. It might not be ready when accessed from _INI.
Tested on Lenovo T430.
Change-Id: I70f22f8ac61dd850180fa159313bb0f8e4ab31d9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Implement ACPI S3 resume control to restore the state before entering
sleep.
* Store the requested state wake state for bluetooth and WWAN.
* Add new methods to init the state and apply the requested state on wake.
* Call the new method on all devices.
Change-Id: I13c08b8c6b1bf0f3deb25a464b26880d8469c005
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add ACPI methods GUWB and SUWB for thinkpad_acpi.
Required for power control of the UWB module.
Change-Id: I8f9a56e45c0d765b0e06b8d3600bd3575dd09491
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add methods MLCG and MLCS for thinkpad_acpi kernel module.
Required for backlight or thinklight control from userspace.
Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Implement GWAN and SWAN for thinkpad_acpi kernel module.
Both methods allow power control of the WWAN module.
Change-Id: I5550c78e0d36884eca7a8d8ece19b64aaee44045
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
* Add SSDT generator to add dynamic ACPI code.
* Implement GBDC and SBDC for thinkpad_acpi kernel module.
Required for BDC power control from userspace.
Tested on Lenovo T430:
The bluetooth module is detected and can be powercycled using network manager.
Change-Id: Ida825196650966194a883945896a038b0790fe45
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Move the APCI HKEY device to a new file and include it.
The follow-up commits will extend it and this way it remains readable.
Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Change-Id: Ib47cc1ee617aae74a8cfbcb25c1d0c083196f417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26460
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use of device_t has been abandoned in ramstage.
Change-Id: I3db9487c46b29510e59ec5c019d022f5cbaff354
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
PWRS is is the power source gnvs.
Notifying CPU is needed to change P- and C-states on these events.
Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The EC does enable bluetooth on wifi cards and BDC at the same time.
Check the new Kconfig to support bluetooth on wifi in case no BDC
is installed and the BDC detection fails.
Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Fix a regression introduced by #21227 0709dc04
(ec/lenovo/h8/acpi/thermal: Add ACPI fan control).
The commit caused Windows to crash as EC reads aren't allowed in the fan
device or it's powerresource's methods. Implement the same approach as all
other platforms using a GNVS variable named FLVL instead of reading from EC.
In addition to EC reads writing to FIELD elements, in another ACPI scope,
seems to be broken. Introduce a new method to set the fan disengage mode.
Tested on Windows 7 and Lenovo T500.
Change-Id: Ia99f8814ac14194578dcd1aa50a63e3f35c042dd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Add register HPPI and GSTS.
Add method WLSW that is used by thinkpad_acpi kernel module.
Seperate method by an empty newline.
Change-Id: I5a125047fad0e08cd9256bc53c3f5a7db7e56e7d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Sometimes (observed on Thinkpad T400s during cold boot) a few (only one
observed) garbage bytes may detained in the output queue of EC after power
up, and they should be cleared otherwise later communications will be
disrupted.
Change-Id: Id1733f7350232d0b10ac0d1bc912b62e7fa4da75
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22181
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Disengage the fan 10 degree below passive threshold as the automatic EC fan
control does not disengage the FAN even when CPU starts melting ...
* Add EC registers FAND and FANA.
* Add ACPI methods _AC0 and _AL0.
* Add fan device and PowerResource for fan control.
Tested on Lenovo T430:
* The fan disengages at 80°C and keeps running at full speed until temperature
drops below 80°C.
* Fan can be disengaged using sysfs:
/sys/devics/virtual/thermal/cooling_device0/cur_state
Tested on Lenovo T500:
* The fan disengages at 80°C and keeps running at full speed until temperature
drops below 80°C.
* Fan cannot be disengaged using sysfs, but the current state can be read:
/sys/devics/virtual/thermal/cooling_device0/cur_state
Change-Id: I075ff5c69676927db1c5e731294e18796884f97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21227
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The ACPI spec requires _TSP, _TC1, _TC2 and _PSL for passive cooling.
_TSP already has been added in a previous commit.
Copy the coefficients used on google devices to activate the feature.
Tested on Lenovo T430:
The CPU is throttled once the passive threshold has been reached.
Tested on Lenovo T500:
The CPU is throttled once the passive threshold has been reached.
Change-Id: I922923a9029de77158988ac254bab4aad9536935
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
```
dsdt.aml 1461: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
```
Change-Id: Iaf9455b16b061b32248139a85890f49de7467261
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Dump PMH7 revision and ID for diagnostic purposes.
Tested on Lenovo T430: PMH7: ID 05 Revision 12
Change-Id: I60d15a8f740aeb974a79b27507e974a730cec174
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
* Add support for detecting WWAN.
* Allows to turn off power to WWAN if no card is installed.
Add the following devicetree values:
* has_wwan_detection
Set to one to indicate that the following register are sane.
* wwan_gpio_num
SB GPIO num to read.
* wwan_gpio_lvl
SB GPIO level for card to be present (usually zero).
Don't enable WWAN power if no card is detected.
As there are no devicetree values yet, the new code doesn't have any effect.
Change-Id: Ie53275b384c85df8adf71fe79b3d54211c868756
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
* Add support for detecting BDC.
* Allows to turn off power to BDC if no card is installed.
* Should fix https://ticket.coreboot.org/issues/99 .
Add the following devicetree values:
* has_bdc_detection
Set to one to indicate that the following register are sane.
* bdc_gpio_num
SB GPIO num to read.
* bdc_gpio_lvl
SB GPIO level for card to be present (usually zero).
Don't enable BDC power if no card is detected.
As there are no devicetree values yet, the new code doesn't
have any effect.
Change-Id: I506de2eca4b820e6d82de6b2c48a5440462e1db5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
