summaryrefslogtreecommitdiff
path: root/src/ec/lenovo/pmh7
AgeCommit message (Collapse)Author
2022-06-22ec/lenovo/pmh7: Add IORESOURCE_ASSIGNED flagKyösti Mälkki
This makes coccinelle script happy, everyone else sets flags last. Change-Id: I80f421aeacb6e72fea2265c69cafb2a0d89e5616 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-04src/ec: Get rid of unnecessary blank line {before,after} braceElyes HAOUAS
Change-Id: I9f7c4bdd9299e686c375aced221a72994ef2d6ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-21ec/lenovo: Use get_int_option()Angel Pons
Change-Id: Ie5cb54b171244be71848a59a788ed8d42b3e3161 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05src/ec: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15nb/intel/i945: Initialize console in bootblockArthur Heymans
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-08-20lenovo/pmh7: Remove use of __PRE_RAM__ and __SMM__Kyösti Mälkki
Change-Id: Ib74c5c8cb9197fa06b2972cb96337fedd7f85b5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-22src/ec: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: Ifdb2dee08da45d698174583ee5ed44bf5a0243ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-29src/{ec,vendorcode}: Add missing 'include <types.h>Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I1eb4163fb36a47b584f1fc9dd3c012e2930e9866 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-09-14ec/lenovo/pmh7: support 9bit address spaceAlexander Couzens
The pmh7 has at least a 9bit address space. The h8s allows to access the 9th address space by using io port 0x15ed as second address register. The pmh7 is connected via SPI to the h8s. The h8s is acting as proxy to access the address space. Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
2018-09-05mb/lenovo: Support dual graphics for xx20/xx30 ThinkPadsEvgeny Zinoviev
Add CMOS option that allows to use both integrated and discrete GPU. Tested on ThinkPad W530. Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28393 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20ec/lenovo/pmh7: use read/write function in clear_bit/set_bitAlexander Couzens
Make the code simpler and improve readability. Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-25ec/lenovo/pmh7: Dump revision and IDPatrick Rudolph
Dump PMH7 revision and ID for diagnostic purposes. Tested on Lenovo T430: PMH7: ID 05 Revision 12 Change-Id: I60d15a8f740aeb974a79b27507e974a730cec174 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-29kbuild: automatically include ECsStefan Reinauer
This change switches all ECs and the generic EC ACPI code to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in ec/Makefile.inc or in ec/<vendor>/Makefile.inc. This means, vendor and ec directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9798 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-27{arch,cpu,drivers,ec}: Don't hide pointers behind typedefsEdward O'Callaghan
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/7146 Tested-by: build bot (Jenkins)
2014-06-25src/ec: Sanitize headers and comment #endif pairingsEdward O'Callaghan
Comment #endif /* FOO */ pairings. Alphabetise headers and remove any #if CONFIG_ guards around them. Background rational: Remove guarding the inclusion of headers based on CONFIG_ options. This *potentially* could hide issues such as functions being swapped from under our feet, since different runtime behaviour could be declared with the same function same name and type-signature. Hence, depending on the header we happen to get may change runtime behaviour. Change-Id: Ic61bdfb64d99f0e2998c6451ae6686915b7bb3d4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6059 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Make trackpoint enable a CMOS option.Vladimir Serbinenko
To be consistent with touchpad counterpart. Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-15ec/lenovo/h8: Fix peripheral init without CMOS configVladimir Serbinenko
Currently H8 skips important init if unable to access CMOS config. Change default to enable all features to have a sane system without using CMOS config. Change-Id: I4448ccd21beae8ad23eb22391770c6fe3b83e3b4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4515 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-02global: Fix usage of get_option() to make use of CB_CMOS_ codesAlexandru Gagniuc
Do not directly check the return value of get_option, but instead compare the returned value against a CB_CMOS_ error code, or against CB_SUCCESS. Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4266 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-04Make the device tree available in the rom stageStefan Reinauer
We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1398 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-10-20T60: Add support for Ultrabay Legacy I/O devices (40Y8122)Sven Schnelle
Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/282 Tested-by: build bot (Jenkins)
2011-06-22PMH7: add missing License HeaderSven Schnelle
Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/55 Tested-by: build bot (Jenkins)
2011-06-07T60/PMH7: move 'touchpad' option to pmh7Sven Schnelle
This option is PMH7 specific, and should be moved there, so all Notebook utilizing a PMH7 have this option. For Thinkpads without Touchpad (like the X60), simply don't add 'touchpad' to cmos.layout. Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/6 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-04-27Lenovo PMH7: add pmh7_ultrabay_power_enable()Sven Schnelle
Can be used to enable/disable Ultrabay power on Thinkpads who control that with the PMH7. (i.e. T60) Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Lenovo PMH7: add pmh7_touchpad_enable()Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-17PMH7: Add dock event controlSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11PMH7: Add chip configSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-02pmh7.[ch]: Add missing license headers.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-01Add support for the Lenovo PMH7 embedded controllerSven Schnelle
Lenovo PMH7 (Power Management Hardware Hub) is found in most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 19:49:15 +0000