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2024-06-17ec/google/chromeec/acpi/cros_ec: Ensure GpioInt and _PRW are mutually exclusiveCoolStar
Under Windows ACPI, GpioInt and _PRW must be mututally exclusive within the scope of a device, otherwise a BSOD occurs with an ACPI_BIOS_ERROR. To enforce this, only use _PRW when EC_ENABLE_SYNC_IRQ_GPIO is not set. If both EC_ENABLE_WAKE_PIN and EC_ENABLE_SYNC_IRQ_GPIO are set, then ensure that the GpioInt is flagged as ExclusiveAndWake (vs just Exclusive) so that the CREC device is still able to wake the device as needed. TEST=Build/boot google/{nocturne,frostflow} to Win11 w/ sync_irq_gpio and wake_pin both enabled. Change-Id: Ia59cce2ee12bfc8d3ac0173a7a4ec88d7079a958 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82233 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <stddef.h>Elyes Haouas
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-16chromeec/ec_acpi: Convert TK_DICTATE to ps2_action_keyAseda Aboagye
When support for the dictation key was added in commit f2782b8328d5 (acpigen_ps2_keybd: Add support for dictation key), I had failed to include this portion of the change in that commit. The top row key of `TK_DICTATE` needs to be converted to the ps2_action_key. This commit simply adds that mapping so that it can be translated. BUG=b:333101631 TEST=Flash DUT that emits a scancode for a dictation key, verify that it is mapped to KEY_DICTATE in the Linux kernel using `evtest`. Change-Id: I1be8c0a96931cca36e6bbbfa0be7d36c4cd93768 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82274 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-22acpigen_ps2_keybd: Add assistant key to linux,keymapAseda Aboagye
If the ChromiumOS EC indicates that the device has an assistant key, we should also add it to the generated linux,keymap binding. This commit simply does so by examining the keyboard capabilities reported by the EC. BUG=b:333088656 TEST=With a device that has an assistant key, flash AP FW and verify that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using `evtest`. Change-Id: I217220e89bce88e3045a4fc3b124954696276442 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-04-22ec/google/chromeec: Do not fill TypeC ACPI device when UCSI is enabledPavan Holla
Do not fill the ACPI table entry associated with the cros_ec_typec driver once we switch to the UCSI kernel driver. Skip the ACPI entry if EC implements the UCSI_PPM feature, and the CBI flag to enable UCSI is set. BUG=b:333078787 TEST=emerge-brox coreboot chromeos-bootimage Cq-Depend: chromium:5416841 Change-Id: I67dff6445aa7ba3ba48a04d1df3541f880d09d0a Signed-off-by: Pavan Holla <pholla@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-04-19ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hPavan Holla
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: b3b35d6433 PPM: Rename ucsi_disabled to ucsi_enabled The original include/ec_cmd_api.h version in the EC repo is: 562316a71e include: Add fingerprint host commands to ec_cmd_api.h BUG=b:333078787 TEST=cros build-packages --board brox \ chromeos-bootimage depthcharge coreboot TEST=cros build-packages --board brya \ chromeos-bootimage depthcharge coreboot BRANCH=none Change-Id: I94b509cd6ad8f24bfc3b44ef02633d06320f1e22 Signed-off-by: Pavan Holla <pholla@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81965 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-04-17ec/google/chromeec: Update EC headersAseda Aboagye
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 9fdd96bfc6 keyboard: Add support for a "Dictation" key The original include/ec_cmd_api.h version in the EC repo is: 562316a71e include: Add fingerprint host commands to ec_cmd_api.h Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81932 Reviewed-by: Forest Mittelberg <bmbm@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05ec/google/chromeec: Enclose Kconfig in 'if/endif' blockMartin Roth
Instead of having things depend on EC_GOOGLE_CHROMEEC, just put an if/ endif block around the configs. The 'source' line stays outside of the if block because the source always happens, even if it's inside an if/endif block. Each of the sub-Kconfigs here already has an if/endif block surrounding the contents. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab Reviewed-on: https://review.coreboot.org/c/coreboot/+/81025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-03-01ec/chromeec: Enable auto fan control on startupMatt DeVillier
Several older ChromeOS boards have issues with fan control on cold boot and/or on S3 resume, so add functionality to allow those boards to programmatically enable auto fan control. TEST=build/boot google/link, verify fan ramps up/down accordingly with CPU load. Change-Id: I08a8562531f8af0c71230477d0221d536443f096 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-02-18ec, lib, security, sb: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-24ec: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic060f3605cd18d4bf774573c21957f626f984e2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80069 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-12-11ec/google/chromeec: Provide ec_sync wake optionMark Hasemeyer
The ACPI spec defines keywords for the GpioInt and Interrupt resources to specify whether a given pin is wake capable. Some boards are using the ec sync interrupt pin to wake the system so the CREC _CRS needs to be updated accordingly. Provide a new macro that allows a board to specify whether its ec sync pin is wake capable. BUG=b:243700486 TEST=Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2023-11-16ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hSimon Glass
Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state The original include/ec_cmd_api.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state BUG=b:300525571 BRANCH=none TEST=none Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-16ec/google/chromeec: Add is_battery_present_and_above_critical_thresholdJamie Ryu
This adds is_battery_present_and_above_critical_threshold to check the battery is present and the battery level is above critical level. BUG=b:296952944 TEST=Build rex and check is_battery_present_and_above_critical_threshold returns the correct battery status. Change-Id: Ib38be55bc42559bab4f12d5e8580ddc3e1a6acc1 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-10-02acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punctJonathon Hall
Librem 11's volume keys act as a PS/2 keyboard with only those two keys. Reduce the minimum number of top-row keys to 2. Make the "rest of keys" (alphanumerics, punctuation, etc.) optional. Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-09-18clean-up: Remove the no more necessary `ENV_HAS_DATA_SECTION` flagJeremy Compostella
With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data section support for pre-memory stages"), the `ENV_HAS_DATA_SECTION' flag and its derivatives can now be removed from the code. Change-Id: Ic0afac76264a9bd4a9c93ca35c90bd84e9b747a2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77291 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14vc/google/chromeos: Move clear_ec_ap_idle() to common codeDerek Huang
Previously the clear_ec_ap_idle() is implemented in cr50_enable_update.c and be called in the file. Move it to common code so that it can be called in cse_board_reset.c TEST=emerge-brask coreboot Change-Id: I2dbe41b01e70f7259f75d967e6df694a3e0fac23 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-08-21ec/google/wilco/superio: Adjust PS2K HID/CID for Windows driversMatt DeVillier
Allows coolstar's Windows overlay drivers to attach, while not affecting operation under Linux or ChromeOS TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco/acpi: Read message when notifying UCSICoolStar
Allows the EC to be properly notified of type-c events like charger wattage too low (eg), TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco: Correct scope of UCSI ACPI deviceCoolStar
Set the USCI device scope to _SB and set HID to USBC000 so Windows driver attaches. This matches the ACPI used by the non-Chromebook version of the Dell Latittude 7410 (which uses the same EC). TEST=build/boot Win11 on google/drallion Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco/acpi: Unhide GOOG000C ACPI deviceMatt DeVillier
Allows coolstar's Windows drivers to attach. TEST=build/boot Win11 on google/drallion Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-21ec/google/wilco/acpi/dptf: Fix mutex synclevelMatt DeVillier
Both Windows and MacOS get cranky if the Mutex synclevel is non-zero, aborting any Acquire() call with Mutex param that has a non-zero synclevel. TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and functional. Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20ec/google/wilco: Fix ACPI EC RAM read/write opsMatt DeVillier
While debugging lack of battery status under Windows, it was discovered that the read/write flags in the args to the EC RAM 'ECRW' method were not being correctly identified. Force set them from the R() and W() methods which call ECRW() so those calls are processed properly. TEST=build/boot Windows on google/drallion, verify battery status, charging, etc are all reported properly. Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf Signed-off-by: Coolstar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-16ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki
Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-04ec/google/chromeec: move TBMC ACPI device under CRECMatt DeVillier
Tablet motion control is a function of the EC, and under Windows, the TBMC device needs to be initialized after CREC, or driver init will fail. The only way to ensure this happens is for TBMC to be a child device under CREC. TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers loaded and orientation switching functional under both OSes. Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-31ec/google/chromeec: Unhide ChromeEC PD ACPI deviceMatt DeVillier
Set the ACPI status (_STA) for the PD device enabled+visible, to allow coolstar's Windows drivers for USB4/Thunderbolt to attach. TEST=build/boot Win11 on google/drobit, install USB4/TB drivers, verify USB4/TB ports are functional for PD and data at USB4 speeds. Change-Id: I84a20cfaf7e077469f8361b3da3b031d9fd84134 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-07-31ec/google/chromeec: Unhide GOOG0004 ACPI deviceMatt DeVillier
Set the ACPI status (_STA) for the EC ACPI to enabled+visible, to allow coolstar's Windows drivers for the EC and keyboard backlight to attach. TEST=build/boot Win11 on google/samus, install EC/kblight drivers, verify keyboard backlight control functional. Change-Id: I3e9578f1ef18b3bebb93a9ae2ae4e27bc38f648d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76790 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15ec/google/chromeec: Split wait-loop for DP and HPD flagsKapil Porwal
Split wait-loop for DP and HPD flags as below - - google_chromeec_wait_for_hpd - google_chromeec_wait_for_dp_mode_entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15ec/google/chromeec: Call `wait_for_dp_hpd` only in AP mode entryKapil Porwal
Wait for DP/HPD flags only in AP initiated mode entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5137c346fbf1edabc60a53e0978e32f54885c330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76369 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15ec/google/chromeec: Skip TCSS `wait_for_connection` for AP mode entryKapil Porwal
Skip TCSS `wait_for_connection` for AP initiated mode entry. BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia04ff470961831237fe851f7ae3feaa5623d4b4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76368 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15ec/google/chromeec: Skip unnecessary call to TCSS `enter_dp_mode` cmdKapil Porwal
Skip TCSS `enter_dp_mode` command when there is no USB device detected on the port. BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ie6cd84cab3631596d4d7178dae2040e25c621f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-17ec/google/chromeec/ACPI: Set TBMC status based on motion sensor presenceMatt DeVillier
Use ECRAM field MTNS to determine if motion sensor present, and set TBMC device status accordingly. TEST=build/boot google/{jinlon,drobit}, verify ACPI status for TMBC correct for both devices with and without tablet mode. Change-Id: Ic06ab6d721f0a3435e6dfd7b5e130f378096afec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-16ec/google/chromeec: Use host command APICaveh Jalali
Update the chromeec driver to use the EC host command API. Large blocks of repetitive code to set up EC calls are replaced with single function calls to perform the same operation. BUG=b:258126464 BRANCH=none TEST=booted on rex Change-Id: I0317405b1ed0c58568078133c17c8cfbc7c21d80 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73325 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-16ec/google/chromeec: Add ec_cmd_api.h, update ec_commands.hCaveh Jalali
The new util/chromeos/update_ec_headers.sh utility is used to update ec_commands.h and introduce ec_cmd_api.h from the chrome EC repo. ec_cmd_api.h is a new file from the chrome EC repo which defines the API for communicating with the EC. It is a companion to the existing ec_commands.h by defining functions corresponding to EC host command opcodes and request/response struct definitions. See $EC/docs/ec-host-command-api.md for details. Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 3e35858003 ec: Add another #line directive The original include/ec_cmd_api.h version in the EC repo is: 59de61f2db zephyr: Add support for RNG devices BUG=b:258126464 BRANCH=none TEST=none Change-Id: I30f20e34d31b7e19cf03f65fefd58ae64eef1d41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-07ec/google/chromeec: Handle ACPI S4 in chromeec_smi_sleep()Kyösti Mälkki
While Chromebook hardware originally would not have the capacity to do suspend-to-disk (ACPI S4), the power management code in EC should react to S4 request as if it was S5 request. Change-Id: Ida9118919c8149d94f470847d0c4aad9c0b97d3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-12Reland "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e. Add multiple fan support for dptf policies. This also fixes the Google Meet resolution drop issue as per b:246535768 comment#12. When system starts Google Meet video call, it uses the hardware accelerated encoder as expected. But, as soon as another system connects to the call, an immediate fallback is observed from hardware to software encoder. Due to this, Google Meet resolution dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC based fanless platforms. This same issue was not seen on fan based systems. With the fix in dptf driver where fan configures appropriate setting for only fan participant, not for other device participants, able to see consistent 720p resolution. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alder Lake-P Redrix system for two fans support and on Alder Lake-N fanless systems. With this code change Google Meet resolution drop not observed. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12ec/google/chromeec: Use either EC or MB lid switch stateKarthikeyan Ramasubramanian
With CB:16732, EC can provide default lid switch implementation(LID0 ACPI device). Up until that point, mainboard has been providing default switch implementation. When EC provides lid switch implementation, the lid switch state is read from EC either through MMAP or LPC interface. Hence there is no need to keep mainboard's LIDS ACPI object in sync with EC's lid switch state. Use only EC's lid switch state on boards using EC's implementation. This paves the way to remove LIDS ACPI object on those mainboards. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Trigger lid open/close events and ensure that they are detected properly through /proc/acpi/button/lid/LID0/state. localhost ~ # cat /proc/acpi/button/lid/LID0/state state: open localhost ~ # cat /proc/acpi/button/lid/LID0/state state: closed Ensure that the system behaves as expected based on powerd configuration. After signin, system suspends/resumes for lid close/open. On signin screen, system shuts down/boots for lid close/open. Change-Id: I013574d7c21761f167ad38aeed27a419677b8000 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-02acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-02-27ec/google/chromeec: Update ec_commands.hTim Van Patten
Update ec_commands.h from the EC repo at: "8441cf4 Add host event: EC_HOST_EVENT_BODY_DETECT_CHANGE" This is an exact copy of the EC repo's ec_commands.h with the exception of updating the copyright message. BUG=b:261141172 BRANCH=none TEST=built coreboot for skyrim Change-Id: I9892c0c3518f63d357459861e8fa1b7f5f494e68 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-02-08ec/google/chromeec: Update ec_commands.hCaveh Jalali
Update ec_commands.h from the EC repo at: "8b6f7de2a7 fan: update fan stalled value reporting" This is an exact copy of the EC repo's ec_commands.h with the exception of updating the copyright message. BUG=b:258110734 BRANCH=none TEST=built coreboot for brya Change-Id: I4ce15e1af40cc54a6cf2ebd6f5d5adf8953dee60 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08ec/google/chromeec: clang-format ec_commands.hCaveh Jalali
This is a format-only change: Reformat ec_commands.h using clang-format according to the EC repo's current formatting style. The command is: clang-format --style=file:$EC/.clang-format -i ec_commands.h where $EC points to the chromeos EC repo. The EC repo has recently adpoted the practice of formatting all files through clang-format using its own style. So, run ec_commands.h through the EC's clang-format so future updates don't get overwhelmed by inconsequential style changes. BUG=b:258110734 BRANCH=none TEST=built coreboot for brya Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-01ec/google/wilco/acpi: Add DPTF RCDP() methodMatt DeVillier
The Windows DPTF drivers expect this method, and if not present appear to hang. Adding this method fixes DPTF under Windows on drallion. Modeled after existing method used by chrome-ec. TEST=build/boot Win11 on google/drallion, verify DPTF functional. Change-Id: I6570345379da413273251ecf5209c4997aac9b11 Original-patch-by: Coolstar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-01-28ec/google/chrome-ec: Demote Vivaldi printk from error to infoMatt DeVillier
Not all Chrome-EC devices have a keyboard or use Vivaldi for key remapping, so demote the printk output when the EC doesn't support it from ERROR to INFO. Adjust the printk text for clarity. Change-Id: I14059f4e3e56ff891f302601d5acc1bb842cffc1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72474 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22ec/google/chromeec/acpi/ec: add scope comment to nested #endifFelix Held
To make the code slightly easier to read, add a comment about the scope to the #endif of the outer #ifdef block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic2bc83c77750cd8a509f4755fdfa4daaf082d754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2023-01-11ec/google/chromeec: Add retimer flag for mux devicePrashant Malani
Not all ports have retimers. Add a property to denote that a particular port has a retimer (instead of assuming that all ports have retimers). BUG=b:263964979 TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when device tree is updated accordingly. Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71663 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-10chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang
When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I449ec5b0bbf3f24d51688efef151d3018d2848b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71524 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{superio,ec}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-26tree/acpi: Replace Not(a) with ASL 2.0 syntaxFelix Singer
Replace `Not (a)` with `~a`. Change-Id: I53993fb7b46b3614d18ee001323f17efacbf04c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b)` with `a & b`. Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where possible. Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace Or(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where possible. Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b)` with `a << b`. Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftRight(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was simplified to just `a >> b`. Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14ec/google/chromeec/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I2cdb1c9ae3a33bfc72767ff60d8948054d4e151a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01vboot: Allow for comparison of hash without zero-paddingJakub Czapiga
Adjust asserts to allow to store and compare (at S3 resume) hashes without padding to maximum hash length / slot size. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01ec/google/chromec: Add DPTC support for host event 1/2/9EricKY Cheng
DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for host event lid-open/lid-close/Thermal Threshold. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-30ec/google/chromeec: Add packed attribute to structs in unionArthur Heymans
Clang warns about structs inside a union also needing the packed attribute. This files is copied from the chromeec project, so it adds comment next to the coreboot specific changes as a reference. TEST: google/vilboz remains the same with BUILD_TIMELESS=1 and gcc. Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-22ec: Add SPDX license headers to MakefilesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ie5355e05982b372ef69515cfa081e2afbc7b09fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17{ec/superio}/acpi: Remove _PRS if no _SRS is implementedArthur Heymans
_PRS only makes sense if _SRS is implemented. Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-12ec/google/chromeec: Deprecate dev_index from google_chromeec_rebootCaveh Jalali
This removes the dev_index argument from the google_chromeec_reboot API. It's always set to 0, so don't bother passing it. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iadc3d7c6c1e048e4b1ab8f8cec3cb8eb8db38e6a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69373 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12ec/google/chromeec: Simplify error handling for GET_VERSIONCaveh Jalali
We don't need to check the lower level error code to determine if an EC call succeeded. Simply check the return value of the call. BUG=b:258126464 BRANCH=none TEST=none Change-Id: Iaf0795b0c1a2df0d3f44e6098ad02b82e33c5710 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69372 Reviewed-by: Boris Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-12ec/google/chromeec: Simplify get_uptime_info error handlingCaveh Jalali
google_chromeec_get_uptime_info() doesn't need to return an error code from the lower level calls for the caller to interpret. It is more appropriate to return a success/failure boolean. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I3e27b8b4eed9d23e6330eda863e43ca78bb174a3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69371 Reviewed-by: Boris Mittelberg <bmbm@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-10ec/google/chromeec: Fix USB_PD_PORTS response data typeCaveh Jalali
The EC_CMD_USB_PD_PORTS host command returns a struct ec_response_usb_pd_ports, not a struct ec_response_charge_port_count. Luckily, both structs have the same memory layout, so this is simply a name change. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10ec/google/chromeec: Simplify KEYBOARD_BACKLIGHT error handlingCaveh Jalali
Simplify the implementation of setting the keyboard backlight PWM value. Host command stubs typcially don't need to examine the host command's return value as stored in cmd_code because that level of detail is not very interesting. Higher value error codes are returned in actual result structures. This host command can return EC_RES_ERROR for out of range PWM values which is already a generic error and unlikely to happen since we already limit the range to 0..100 here. Finally, none of the callers in coreboot check the return value. BUG=b:258126464 BRANCH=none TEST=none Change-Id: If17bc4e31baba02ba2f7ae8e7a5cbec7f97688c5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69369 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10ec/google/chromeec: Fix keyboard_backlight callCaveh Jalali
The EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT command does not return data, so don't specify a result buffer. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I5b9a0d228e187a9337498246a3b9ed8db07b95c7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2022-11-10google/chromeec: Add ACPI method for EC PanicRob Barnes
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events. EC panic is not covered by the standard (0-F) ACPI notify values. Arbitrarily choosing B0 notify, which is in the 84-BF device specific ACPI notify range. This will be a no-op until the kernel driver is also updated to handle this event. BUG=b:258195448 BRANCH=None TEST=Observe event with modified cros_ec_lpc driver Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69391 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09ec/google/chromec: Expand EC share memory for DTTSEricKY Cheng
DTTS is Dynamic Thermal Table Switching Proposal. DTTS needs one bit to save the body detection result from EC. Define mode change STTB bit for Desktop (1) and laptop (0). This bit is Switch thermal table by body detection status. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68077 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-03ec/google/wilco: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I93f02674fde0415e4d831ec13541a806bbc3bd91 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-10-25ec/google/wilco/superio: Fix PS2K under WindowsMatt DeVillier
PS2K device needs to be under PCI0, not LPCB, for Windows to recognize it. Same change was made to ChromeEC previously. Test: Boot Win11 on Drallion, verify built-in keyboard functional. Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-20Revert "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 672bd9bee5c0045694ef20fe3e2f7a003bef0edd. Reason for revert: Gmeet resolution dropped. When system starts Gmeet video call, it uses the hardware accelerated encoder as per the expectation. But, as soon as another system connects to the call, the immediate fallback observed from hardware to software encoder. Due to this, Gmeet resolution dropped from 720p to 180p. Currently, this issue observed on AlderLake-N SoC based fanless platforms. This issue is not seen on fan based systems. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alderlake-N systems. With this revert Gmeet resolution drop not observed. Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2022-10-20ec/google/wilco/acpi: Hide CrOS-specific devices from OSMatt DeVillier
Set _STA to 0xB for GOOG000C/GOOG000E devices to prevent showing as missing drivers under Windows. Change-Id: I0887fd6e18528d2c8523e7bc66db9efaa31adf5d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68462 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14ec/google/chromeec: Demote LPC EC error printk from ERR to SPEWMatt DeVillier
Several EC host commands check for support of a given feature or msg version, and a non-zero response does not necessarily indicate an actual error. Since the caller is (should be) handling the non-zero response to the host command, demote the EC printk from ERR to SPEW to clean up the console log and prevent non-errors from causing false failures in firmware tests. BUG=b:238961053 Change-Id: Ib7afc0b7e5b571acb56252f7adb518a6b2716b62 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-05ec/google/chromeec: Modify ufp from type-c roleDtrain Hsu
In order to fix the USB port of type-C dongle has no function after reboot/shutdown, modify ufp which is in google_chromeec_usb_pd_get_info from the bit1 of type-c role (PD_CTRL_RESP_ROLE_DATA). BUG=b:239138412 TEST=Built coreboot image and verified that using this patch can detect usb drive after reboot. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I73a4a6ec37129388783599125f067068d155d93f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67168 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04drivers/intel/dptf: Add multiple fan support under dptfSumeet Pawnikar
Add multiple fan support for dptf policies BUG=b:235254828 BRANCH=None TEST=Built and tested on Redrix system for two fans Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-31acpi: Replace EC_ENABLE_AMD_DPTC_SUPPORT with Kconfig valueTim Van Patten
Compile-time support of DPTC is controlled by EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. Each variant's run-time support of DPTC continues to be controlled by the variant's overridetree.cb "dptc_enable" value. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-26ec/google/chromeec: Call PNOT() when Battery Status ChangesTim Van Patten
PNOT() should be called when the battery status changes, to give the SOC an opportunity to handle it. This is in preparation for the low/no battery boot changes. This CL also updates the PNOT() comments to better match the name of the function and why it's called. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Change-Id: I8b74313d242fd4959315a67579eb6c5f49a31a76 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66993 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-24ec/google/chromeec/acpi: Add support for DPTF oem variable event notifyTony Huang
The agah EC code will monitor adapter current to choose corresponding DPTF oem variable table. When it changes, this event will send to the ACPI FW through host event and then pass onto the DPTF kernel driver. This patch adds support for that feature. BUG=b:238921409 TEST=add Printf() calls to the ACPI, and check these Printf() will show up in the kernel log when EC send oem variable table change notify. Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18ec/google: Notify DPTF driver power participant on PD eventVarshit B Pandya
The DPTF power participant device needs to be notified when power source changes so it can re-evaluate power source and power source change count, this can be later used by DPTF along with methods provided by EC. Corresponding changes in EC are https://crrev.com/c/3545778 and https://crrev.com/c/3547317 BUG=b:205928013 TEST=Build, boot brya0 and dump DSDT to check change Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-08-17ec/google/chromec: Add BFIV, BFCTTim Van Patten
The flag EC_BATT_FLAG_CUT_OFF was added with the CL: 3704470: battery: Set battery cutoff flag https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704470 This flag is set in the ACPI memory mapped area when the command `ectool batterycutoff` is issued so ACPI code can respond appriopriately. This CL adds the flags to coreboot ACPI. BRANCH=none BUG=b:217911928 TEST=Boot nipperkin with low & no battery TEST=Boot skyrim with low & no battery Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I4e63ff4fc2d6b0ecf767a6bffd81f823c74c15bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66803 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-14commonlib: Substitude macro "__unused" in compiler.hBill XIE
Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-13ec/google/chromec: Update ACPI handlers for GPUTim Wawrzynczak
There is a new field in EC EMEM for arbitrary GPU data to be passed from EC to ACPI FW; this patch adds support for it. Also the current host event for _Q0C (EC_HOST_EVENT_USB_CHARGER) is unused, and is being repurposed in the next CL, so this patch drops the handler. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iff6f935a5bdc8c47277eaa6bcbedd5fc5ed311a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-04treewide: Unify Google brandingJon Murphy
Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-30ec/google/chromeec: Update ec_commands.hYu-Ping Wu
This change copies ec_commands.h directly from the ChromiumOS EC repo, with the exception of changing the copyright header to SDPX format. Update to commit SHA1 2cbf6fbf (ec_commands: Drop VBNV read/write support). BUG=b:178689388 TEST=none BRANCH=none Change-Id: I74fa8b1171ca109dee163a7657659cdac1687450 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65469 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-24ec/google/chromeec: Remove google_chromeec_vbnv_context()Yu-Ping Wu
With CB:65012, google_chromeec_vbnv_context() is no longer used. Remove it from the codebase. BUG=b:178689388 TEST=./util/abuild/abuild -t GOOGLE_STOUT -a -x Change-Id: I717f600f0f73c3ca932b6a442a9d5b90c35c8f3b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
These changes made my crude pattern matching work with coccinelle simpler. Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-15ec/google/chromeec: Add property to denote mux mode switchPrashant Malani
On some systems, the Chrome EC controls both the USB Type-C mux as well as the retimer. Introduce a boolean property "mode-switch" to denote switches which act as a mode-switch. BUG=b:235834631 TEST=None BRANCH=None Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: If209a8529ff7ec424f23fd96875ac95a1fe6267d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-10ec/google/chromeec: Add support to report fan speed via ACPISumeet Pawnikar
Add fan speed rpm control for DPTF based Active2 policy as per document #626708, by utilizing existing FAN0 variable from src/ec/google/chromeec/acpi/emem.asl#18. There is no corresponding EC change required for this policy support because EC fan code already exporting this rpm value using EC_MEMMAP_FAN for FAN0. BUG=b:224457192 BRANCH=None TEST=Built and booted on ADL-P based Brya system and verify the fan speed in rpm under sysfs path cat /sys/bus/acpi/devices/INTC1048\:00/fan_speed_rpm. Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-09ec/google/chromeec/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LNotEqual(a, b)` with `a != b`. Change-Id: I2e0c5961fcc90c97666f49837a71f6c0bdc429b3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-06-03ec/google/chromeec/acpi: Replace LGreater(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LGreater(a, b)` with `a > b`. Change-Id: Ie6238ead464d79b3576846f3b5b92b658972eec8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-03ec/google/chromeec/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b, c)` with `c = a * b`. Change-Id: Iea86e77df6c76756ed336f57a906ac0757aef1cf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-03ec/google/chromeec/acpi: Replace Divide(a,b,,c) with ASL 2.0 syntaxFelix Singer
Replace `Divide (a, b, , c)` with `c = a / b`. Change-Id: I26117087c09109cfc480cbe01d3761a02a12c61b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-03ec/google/chromeec/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: I4d79080ecfe457766983b20a0217ccadcd188fcf Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-03ec/google/chromeec/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LLess(a, b)` with `a < b`. Change-Id: I65225a890f9085574a2295e6ccd2cdc3e84f71e0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>