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2018-02-17chromeec: Sync ec_commands.h for CBI tagsDaisuke Nojiri
This patch syncs ec_commands.h with the one in chromeec. BUG=b:70294260 BRANCH=none TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz. Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17chromeec: Add google_chromeec_wait_for_displayDaisuke Nojiri
The google_chromeec_wait_for_display API checks whether a display is ready or not. It waits in a loop until EC says it entered DisplayPort alternative mode or times out in 2 seconds. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ieee5db77bd6e147936ea8fc735dcbeffec98c0f8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-17chromeec: Add google_chromeec_pd_get_amodeDaisuke Nojiri
The google_chromeec_pd_get_amode API checks whether TCPM is in a specified alternate mode or not. BUG=b:72387533 BRANCH=none TEST=See 23746 "mb/google/fizz: Wait until display is ready" Change-Id: Ib9b4ad06b61326fa167c77758603e038d817f928 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-12ec/chromeec: Fix battery ACPI mutex levelMatt DeVillier
Commit 07fe618 [chromeec: Add support for reading second battery info] added a mutex as part of the ACPI code to determine battery statuses. Windows is extremely picky about ACPI code, and attempting to acquire a level 1 mutex without first having acquired a level 0 mutex causes Windows to hang on boot. Since there's no reason to use a level 1 mutex here, change it to level 0. Test: Boot Windows on device with ChromeEC without hanging Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-09chromeec: Fix ACPI compile warningLijian Zhao
For system without secondary battery, current DSDT will report warning during build time. Add a conditional check to make sure only battery index 0 can return success. TEST=Build pass. Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23661 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07chromeec: Add support for reading second battery infoNicolas Boichat
We share the same shared memory fields for both batteries. When the host wants to switch battery to read out, it will: - Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index - Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value - Then fetch the data BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/23598 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-02-05ec/google: Get OEM ID and SKU ID from ECDaisuke Nojiri
This patch adds EC_CMD_GET_CROS_BOARD_INFO and two APIs to fetch OEM ID and SKU ID from cros EC. CBI abbreviates Cros Board Info. BUG=b:70294260 BRANCH=none TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz. Change-Id: Iff69a2dc0e562d87dd287f79c407f23aeb09fb9e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-02ec/google/chromeec: Remove wake flag from keyboard IRQDuncan Laurie
The keyboard IRQ was changed to ExclusiveAndWake in order to support waking from suspend-to-idle (S0ix) with commit f611fcfacac5be14a51e04ae4d0b1e25cd5439c0 http://review.coreboot.org/11712 However this is triggering a kernel panic on Windows 10 because it apparently does not like legacy device interrupts to to be set as wake capable. This change is no longer necessary because the linux kernel was changed to always treat the keyboard as wake capable: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/input/serio/i8042.c?id=f13b2065de8147a1652b830ea5db961cf80c09df Change-Id: I26e27de68095f8d176108f39312338522d7cfba0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23563 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-30chromeec: Decouple EC tablet event and TBMC deviceFurquan Shaikh
This change decouples EC tablet event and TBMC device by guarding TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It allows mainboards to use tablet events without having to define a TBMC device. BUG=b:72554519 Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-26ec/google/chromeec: Add _PRW property to CREC deviceFurquan Shaikh
This change adds _PRW property to CREC device that allows Linux kernel to identify CREC as a wakeup source. BUG=b:69118395 TEST=Verified following steps: 1. Under sys devices for CREC: "echo enabled > wakeup" 2. Lid close/Lid open -- Verified that wakeup_count increases 3. Mode change -- Verified that wakeup_count increases Change-Id: Ib0a687e171c7e5c81325b39f47c9a2462553fe3e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-17google/chromeec: Enable unified host event programming interfaceJenny TC
Unified Host Event Programming Interface (UHEPI) enables a unified host command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events. Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F) is supported for backward compatibility. But newer version of BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT) The UHEPI also enables the active and lazy wake masks. Active wake mask is the mask that is programmed in the LPC driver (i.e. the mask that is actively used by LPC driver for waking the host during suspended state). It is same as the current wake mask that is set by the smihandler on host just before entering sleep state S3/S5. On the other hand, lazy wake masks are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set the active wake mask depending upon the type of sleep that the host has entered. This allows the host BIOS to perform one-time programming of the wake masks for each supported sleep type and then EC can take care of appropriately setting the active mask when host enters a particular sleep state. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix 1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix 2). suspend_stress_test with S3 and S0ix 3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm wake sources (Lid, power buttton and Mode change) 4). Verified "mosys eventlog list" in S5 resume to confirm wake sources (Power Button) 5). Verified above scenarios with combination of Old BIOS + New EC and New BIOS + Old EC Change-Id: I4917a222c79b6aaecb71d7704ffde57bf3bc99d9 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-08chromeec: Add command to override charger limitDaisuke Nojiri
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which overrides the max input current and voltage when a barrel jack adapter supplies power. BUG=b:64442692 BRANCH=none TEST=Boot Fizz. Use chgsup console command to verify the max current and voltage are set as expected. Change-Id: I8c6fc54e519ce13e3db82ee2cecaa96c6eb42d8a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08cr50: Make EC clear AP_OFF before hibnernateDaisuke Nojiri
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes EC clear AP_OFF flag then hibernate. This is needed to make Chromebox boot when cr50 toggles the EC's reset line after TURN_UPDATE_ON command. BUG=b:69721737 BRANCH=none CQ-DEPEND=CL:802632 TEST=Verify Fizz reboot after cr50 update. Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-30chromeec: Notify CREC device of wakeup eventsFurquan Shaikh
Whenever there is a new EC event that could be wake-capable, notify CREC device of this using notification value 0x2 i.e. device wake. This allows Linux kernel to track active_count value correctly for CREC device. BUG=b:69118395 BRANCH=None TEST=Verified on Soraka: 1. Put device into suspend 2. Wake up using mode change/lid open 3. Check that the active_count for GOOG0004 has increased (cat wakeup_sources | grep GOOG0004) Change-Id: I723f7f4e4c99e7a5b57c6296da66cf30cd413c27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-22chromeec: Change the API for hostevent/wake masks to handle 64-bitFurquan Shaikh
ChromeEC is getting ready to bump up the hostevents and wake masks to 64-bits. The current commands to program hostevents/wake masks will still operate on 32-bits only. A new EC host command will be added to handle 64-bit hostevents/wake masks. In order to prevent individual callers in coreboot from worrying about 32-bit/64-bit, the same API provided by google/chromeec will be updated to accept 64-bit parameters and return 64-bit values. Internally, host command handlers will take care of masking these parameters/return values to appropriate 32-bit/64-bit values. BUG=b:69329196 Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20chromeec: Add function to retrieve usb c charger infoShelley Chen
Add google_chromeec_get_usb_pd_power_info(), which will call the EC_CMD_USB_PD_POWER_INFO host command to retrieve the current and voltage info of the usb c charger. Returns power info in watts. BUG=b:37473486 BRANCH=None TEST=output debug info to make sure that correct power is returned. Change-Id: Ie14a0a6163e1c2699cb20b4422c8062164d92076 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/21771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19google/chromeec: Do not set wake mask before logging EC eventsFurquan Shaikh
Earlier the EC expected the host to set appropriate masks before reading host events. However, with recent change in EC, this is no longer required. This change removes the setting of wake_mask before and after reading the host events. However, in order to support older versions of EC, a new feature flag is added on the EC side that informs the host whether or not it is using the new way of reporting host events without having to set wake mask. CQ-DEPEND=CL:719578 TEST=Verified that EC wake events are correctly logged with both old and new versions of EC. Change-Id: Ib17e1296fb7d3bbc84fc7581fd0a9bd179ac87b9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22006 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19ec/google/chromeec: Export google_chromeec_log_events in ec.hFurquan Shaikh
This change makes google_chromeec_log_events available to callers outside ec.c. BUG=b:67874513 Change-Id: I36cc1e66e035eda707297d8153cd3fabeadfee45 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18google/chromeec: Drain all MKBP events while clearing host eventsFurquan Shaikh
EC maintains a FIFO of all MKBP events and sets host event whenever a new entry is added to the FIFO. Clearing only the host event for MKBP creates an inconsistent state where there are pending MKBP events in the FIFO but host event for MKBP is cleared. In order to maintain a consistent view, host should clear all MKBP events in the FIFO if host event is being cleared. This change drains out all the MKBP events in the FIFO when clear_pending_events is called. TEST=Verified by adding debug logs in EC to verify that all the MKBP events that occur before clear_pending_events is called get cleared from the FIFO. Change-Id: I131722dc01608dff30230fe341e6b23ae4cc409e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-18google/chromeec: Add new helper function to read MKBP eventsFurquan Shaikh
This change adds a new helper function google_chromeec_get_mkbp_event that allows coreboot to query EC for the next available MKBP event. Change-Id: Ia6d64586ca62378d08025c96c2689c00c816041f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-08ec/google/chromeec: Add library function google_chromeec_events_initFurquan Shaikh
mainboard_ec_init implemented by all x86-based mainboards using chromeec performed similar tasks for initializing and recording ec events. Instead of duplicating this code across multiple boards, provide a library function google_chromeec_events_init that can be called by mainboard with appropriate inputs to perform the required actions. This change also adds a new structure google_chromeec_event_info to allow mainboards to provide information required by the library function to handle different event masks. Also, google_chromeec_log_device_events and google_chromeec_log_events no longer need to be exported. Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-04chromeec: Remove checks for EC in RODaisuke Nojiri
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26Use stopwatch_wait_until_expired where applicableJonathan Neuschäfer
Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-26chromeec: Provide helper routine to read boardid from Chrome ECFurquan Shaikh
Instead of duplicating the code across multiple mainboards, provide a helper function to read boardid from Chrome EC. Change-Id: I2008de7032bc880e90b2c3c385b2a67bfb8724cc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-13ec/google: Add command to set APU SKU ID to ECKevin Chiu
EC needs to have command to set SKU ID from APU to support specific feature (ex: keyboard backlight) for variant board. BUG=b:65359225 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I8cd3b8f646d4134d6bfff2869f6df2d9c615c157 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30ec/google: Use feature flag layout that matches the EC host commandPatrick Georgi
The EC side of the feature bits in ACPI EC space isn't stable yet, and we're now going for matching them up with the EC host command of the same purpose. Change-Id: I9c1f0e5390e840ea0c32315a3da8eea6f3e12f54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22ec/google: Detect keyboard backlight at runtimePatrick Georgi
This enables adding the backlight driver to boards that may or may not come with a keyboard backlight function. It's the responsibility of the EC to report if that feature exists, but that's not a big extra burden given that it already keeps track of everything else related to the backlight. BUG=b:64705535 BRANCH=none CQ-DEPEND=CL:620595 TEST=configured KBLE manually and noticed the presence/absence of /sys/devices/platform/GOOG0002:00/ on a Chrome OS Linux kernel, corresponding to the value reported by the EC. Change-Id: Idc36bfaa6e69581ba19b52d37af6956f63cfdb8f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15ec/google: Add command to fetch SKU ID from ECPatrick Georgi
BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I82e324407b4b96495a3eb3d4caf110f9eae05116 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-11ec/google: update ec_commands.hPatrick Georgi
Copy from chrome-ec codebase, except for keeping the long-form license header. BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I513123547f3854945e827d2f7f6c0df6591886eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20945 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-01ec/google/chromeec: Add support for EC device eventsDuncan Laurie
Add support for the new EC device event interface which is used to report events from devices that are connected behind the EC. This can be used to differentiate wake sources from the EC in the case that the EC has the wake pins from various devices. This can be used in case the AP is unable to directly wake from the device itself, for example when using the Deep S3 state on Intel platforms only a few pins can directly wake the AP. BUG=b:30624430 TEST=build google/* boards that use chrome EC. Feature is used and tested further in a subsequent commit. Change-Id: I5126c6d6ffb6b0ef6e8db8dcd5aec62db925a371 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-01ec/google/chromeec: Sync header with Chromium EC codebaseDuncan Laurie
Update this header from the upstream source so new host commands can be used in coreboot. https://chromium.googlesource.com/chromiumos/platform/ec commit bbb759ceaa843f548f90c35d1668e17c8879bad3 BUG=b:30624430 TEST=build google/* and intel* boards Change-Id: I56c9f891262d8984b6a9a69d96752c2dd6bb2371 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-28src/ec: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-13device/pnp: remove struct io_infoSamuel Holland
The 'set' field was not used anywhere. Replace the struct with a simple integer representing the mask. initializer updates performed with: sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \ src/ec/*/*/ec.c sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \ src/ec/*/*/ec_lpc.c \ src/superio/*/*/superio.c \ src/superio/smsc/fdc37n972/fdc37n972.c \ src/superio/smsc/sio10n268/sio10n268.c \ src/superio/via/vt1211/vt1211.c src/ec/kontron/it8516e/ec.c was manually updated. The previous value for IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and had a zero bit in the middle of the mask. Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Myles Watson <mylesgw@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-02ec/google/chromeec: Fix typo in ECUI deviceDuncan Laurie
The IO region defined for EC_HOST_CMD_REGION1 was incorrectly using EC_HOST_CMD_REGION0 for the range maximum so the region was showing a minimum of 0x880 and a maximum of 0x800. Both min and max should report the same value as this region is fixed and cannot be relocated by the OS. Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05ec/google/chromeec: provide reboot functionAaron Durbin
Provide a common function to issue reboot commands to the EC. Expose that function for external use and use it internal to the module. BUG=b:35580805 Change-Id: I1458bd7119b0df626a043ff3806c15ffb5446c9a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19573 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-27ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeecFurquan Shaikh
Instead of defining a separate LID device for mainboards using chromeec, define EC_ENABLE_LID_SWITCH for these boards. Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18964 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-22google/chromeec: Ensure \_SB.LID0 is present before using itFurquan Shaikh
Since we want to support devices that do not have a lid but still use EC, we need to conditionally check if referencing \_SB.LID0 is valid. BUG=b:35775024 Change-Id: I92433460ec870fb07f48e67a6dfc61e3c036a129 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18941 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-09google/chromeec: Add support for cros_ec_keyb deviceFurquan Shaikh
This is required to pass button information from EC to kernel without using 8042 keyboard driver. 1. Define EC buttons device using GOOG0007 ACPI ID. 2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE. BUG=b:35774934 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-07ec/google/chromeec: let platform prepare for reboot when resetting ECAaron Durbin
This fixes an issue on systems where the S3 state in the pm1 control registers are not cleared when vboot determines recovery mode is required on an S3 resume. The EC code will reboot the system knowing that the EC was in RW. However, on subsequent entry into romstage the S3 path will be taken and fails to recover cbmem -- forcing another reboot. To work around that, signal to the platform a reboot is happening and let the platform perform the necessary fix ups to the register state. BUG=chrome-os-partner:62627 Change-Id: Ic144b11b4968c92a1273b8d9eb9dc10f0056bf3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18295 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-07ec/google/chromeec: Add support for tablet mode switch driverGwendal Grignou
Add a new driver GOOG0006 to report tablet switch to user space. On glados based convertible, check that with a new kernel driver (cros_ec_tbmc) that evtest collects tablet switch changes. Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/430951 Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/18173 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15ec/google/chromeec: query cbmem for retrain statusAaron Durbin
The EC switches, including the hardware retrain flag, are cleared when handing off the vboot state in romstage. However, one may still want to query the state of the hardware retrain flag. Thus, add a method to get the flag from cbmem. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17869 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15ec/chromeec: Correct ACPI battery data fed into ToString()Matt DeVillier
ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString(). Change-Id: I4fdbf97e9b75030374dffc99a954dd9faa6a5209 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17782 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-06google/chromeec: Add command to control USB PD roleJulius Werner
Normally firmware should have no business messing with the USB PD role (source/sink/whatever) in the EC. But, as so often happens, ugly issues crop up that require weird work-arounds, and before you know it you need to do this for some reason that only makes sense in context. I do now, so add this function to send the necessary host command in the simplest possible fashion. BRANCH=gru BUG=chrome-os-partner:59346 TEST=Used it in a follow-up patch. Change-Id: I07d40feafd6a8387a633d6384efb205baf578d76 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8b71767caccff9b77d458182ce8066f7abf6321c Original-Change-Id: Ie8d0be98f6b703f4db062fe2f728cd2588347202 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/413030 Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/17627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-14google/chromeec: Add elog events for recovery mode switchesFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified eventlog on reef 0 | 2016-11-12 19:49:25 | Log area cleared | 4088 1 | 2016-11-12 19:49:25 | Kernel Event | Clean Shutdown 2 | 2016-11-12 19:49:25 | ACPI Enter | S5 3 | 2016-11-12 19:49:39 | System boot | 365 4 | 2016-11-12 19:49:39 | EC Event | Power Button 5 | 2016-11-12 19:49:45 | Chrome OS Recovery Mode | Recovery Button Pressed 6 | 2016-11-12 19:49:45 | Chrome OS Developer Mode 7 | 2016-11-12 19:49:45 | EC Event | Keyboard Recovery 8 | 2016-11-12 19:49:45 | Memory Cache Update | Recovery | Success 9 | 2016-11-12 19:50:46 | System boot | 366 10 | 2016-11-12 19:50:46 | EC Event | Power Button 11 | 2016-11-12 19:50:52 | Chrome OS Recovery Mode | Recovery Button Pressed 12 | 2016-11-12 19:50:52 | Chrome OS Developer Mode 13 | 2016-11-12 19:50:52 | EC Event | Keyboard Recovery Forced Hardware Reinit 14 | 2016-11-12 19:50:52 | Memory Cache Update | Recovery | Success 15 | 2016-11-12 19:51:24 | Power Button 16 | 2016-11-12 19:51:24 | ACPI Enter | S5 17 | 2016-11-12 19:51:27 | System boot | 367 18 | 2016-11-12 19:51:27 | EC Event | Power Button 19 | 2016-11-12 19:51:32 | Wake Source | Power Button | 0 20 | 2016-11-12 19:51:32 | ACPI Wake | S5 21 | 2016-11-12 19:51:32 | Chrome OS Developer Mode 22 | 2016-11-12 19:51:32 | Memory Cache Update | Normal | Success Change-Id: I45dda210cf9d4e5a75404792fcee15b2010787a7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17394 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10google/chromeec: Sync ec_commands.h host events with ec codebaseFurquan Shaikh
BUG=chrome-os-partner:59352 BRANCH=None TEST=Compiles successfully for reef Change-Id: Ibfa5681e16a97e342633104d2aae1fb0402939b8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17240 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-10-07ec/google/chromeec: Add minimum delay between SPI CS assertionsJulius Werner
Some Chrome OS ECs require a small amount of time after a SPI transaction to reset their controllers before they can service the next CS assertion. The kernel and depthcharge have always enforced a 200us minimum delay for this... coreboot should've done the same. BRANCH=gru BUG=chrome-os-partner:58046 TEST=Booted Kevin in recovery mode, confirmed that recovery events got logged with correct timestamps in eventlog. Change-Id: I32ec343f3293ac93729d3e6e2f43d7605a396cdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9e4696533d4318ae7c8715b71ab963d8897c16c Original-Change-Id: I6a7baf7859d5d50e299495d118e7890dcaa2c1b0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/392206 Original-Tested-by: Shawn N <shawnn@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://review.coreboot.org/16885 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-02Kconfig: Update default hex values to start with 0xMartin Roth
Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16834 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-26ec/google/chromeec: provide optional ASL lid switch implementationAaron Durbin
Instead of relying on the mainboards to provide their own LID0 ACPI device, provide the infrastructure so that the mainboards can signal to the EC ASL code to provide the default lid switch implementation. BUG=chrome-os-partner:56677 Change-Id: Ie43b1c4f8522db1245f1f479bfdb685d3066121d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16732 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-09-07src/ec: Improve code formattingElyes HAOUAS
Change-Id: I93b71ca577c973046d1651d92665168b329eda1b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16503 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Omar Pakker
2016-08-20google/chromeec: Ensure data is ready before reading itFurquan Shaikh
Before reading the data provided by EC to the host, ensure that data ready flag is set. Otherwise, it could result in reading stale/incorrect data from the data buffer. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is read correctly by host on reef. Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16258 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-12chromeec/acpi: add Tablet event and EC ACPI MEMjiazi Yang
Switch DPTF table when TABLET/NOTEBOOK mode changes 1. EC send EC_HOST_EVENT_MODE_CHANGE(29/0x1D) when mode changes 2. Host read current "physical mode" from EC ERAM BUG=chrome-os-partner:53526 BRANCH=master TEST=build glados Change-Id: I836d2b9d1a24c455c4b8d4b85f7edc19259d2f71 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9506c4c07e0f713c9a22a0231bc4255f6876783f Original-Change-Id: I5a3363ff9c958decb5aed1c85fc2a1ef6670931d Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com> Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/365991 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16151 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-08google/chromeec: Enable/Disable ccache with config variableMartin Roth
If the CONFIG_CCACHE variable is NOT set, define the CCACHE variable as blank on the Chrome EC make command line. This will overrride and disable the CCACHE variable in the Chrome EC makefile. Change-Id: Idb1da06941084cea104d77748820971edf151f7b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16035 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04chromeec: Chrome EC firmware source selection for EC and PD firmwaresPaul Kocialkowski
In some cases, we don't want the Chrome EC firmwares (both EC and PD) built directly by the coreboot build system or included in images at all. This is already supported with EC_EXTERNAL_FIRMWARE but it does implement a binary (build and include) or (neither build nor include) policy. Some cases require the ability to separately control whether the EC and PD firmwares should be built and included by the coreboot build system, only included from externally-built images or not included at all. This introduces config changes implementing that behaviour, renaming options to make it clear that they are specific to the Chrome EC. Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-31build system: really disable building CrEC when not neededPatrick Georgi
Enable users to set the EC_EXTERNAL_FIRMWARE config flag, and actively ignore anything related to EC firmware board names if enabled. BUG=none BRANCH=none CQ-DEPEND=CL:344540 TEST=emerge-samus coreboot works Change-Id: I02aa1e4bc0c98300105b83a12979e9368a40cbcf Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4f0b6fd10aa89fbb38bdebf14b8a82d52e9ee233 Original-Change-Id: I39c3038d059ec3d7710b864061fcf83b8d6d4d13 Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345584 Original-Reviewed-by: Aaron Durbin <adurbin@google.com> Original-Commit-Queue: Martin Roth <martinroth@chromium.org> Original-Trybot-Ready: Martin Roth <martinroth@chromium.org> Original-Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15938 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-27chromeec: Use CHROMEEC_SOURCE with fallback instead of hardcoding pathPaul Kocialkowski
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS EC source path, with a fallback to 3rdparty/chromeec. This allows specifying an external path for the CrOS EC source path. Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15765 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-07-15ec/google/chromeec: provide common SMI handler helpersAaron Durbin
The mainboards which use the Chrome EC duplicate the same logic in the mainboard smi handler. Provide common helper functions for those boards to utilize. BUG=chrome-os-partner:54977 Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15685 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-10google/chromeec: Update EC command headerGwendal Grignou
In particular, update host_event the original value for MKBP was not set in ToT. CQ-DEPEND=CL:353634 BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I0184e4f0e45c3321742d3138ae0178c159cbdd0a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: cc6750b705300f5b94bf23fe5485d6e7a5f9e327 Original-Change-Id: I60df65bfd4053207fa90b1c2a8609eec09f3c475 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354040 Reviewed-on: https://review.coreboot.org/15567 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24ec/google: Add support for the EC 'get time' functionSimon Glass
Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to implement rtc_get() so that this can be plumbed in. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits, boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I3b38f23b259837cdd4bd99167961b7bd245683b3 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4a4a26da37323c9ac33030c8f1510efae5ac2505 Original-Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351780 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-03chromeec: Move EC image hash to separate file in CBFSJulius Werner
The Chrome OS bootloader is changing its EC software sync mechanism to look for the hash of an EC image in a separate CBFS file, rather than using the CBFS hash attribute of the image itself (see http://crosreview.com/348061). This patch makes coreboot generate appropriate hash files for the new format when it builds and bundles a Chrome EC image. This also allows us to compress the EC image itself. Change-Id: I9aee6b8d24cdf41cb540db86a7569038fc7d9937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15039 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-18ec/google/chromeec/acpi: Add MKBP supportGwendal Grignou
Allow EC to send an interrupt using ACPI SMI when a MKBP event is available. This will be used by the sensor stack. Update all ACPI branch except those without sensors with: for i in $(find . -name ec.h -exec grep -l MAINBOARD_EC_SCI_EVENTS {} \+ | cut -d '/' -f 2 | grep -v -e cyan -e lars); do echo $i cd $i git diff ../lars/ec.h | patch -p 5 cd - done BUG=b:27849483 BRANCH=none TEST=Compile on Samus. Tested in Cyan branch. Change-Id: I4766d1d56c3b075bb2990b6d6f59b28c91415776 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: d3b9f76a26397ff619f630c5e3d043a7be1a5890 Original-Change-Id: I56c46ee17baee109b9b778982ab35542084cbd69 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342364 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14854 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-05-13ec/google/chromeec: don't guard function declarationsAaron Durbin
In order to allow using the same C source to be compiled for multiple stages (with #if/#endif guards) one needs the necessary function delcarations. Therefore, remove the guards. Change-Id: Iea94d456451c5d3db8b8b339e81163b3b3fed3ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14796 Reviewed-by: Duncan Laurie <dlaurie@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-11ec/google/chromeec: provide way to query ioport rangeAaron Durbin
In order to provide other stages access to the ioport range required by the ChromeEC provide google_chromeec_ioport_range() function to fill in the details. Currently, the ioport range is only consumed by the LPC implemenation. Also allow ec_lpc.c to be built for the bootblock stage. Change-Id: I6c181b42e80e71fe07e8fa90df783107287f16ad Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14769 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-09ec/google/chromeec/acpi: Add GOOG0004 to load cros_ec_lpc dynamically.Gwendal Grignou
Add a GOOG0004 object that will be used to load cros_ec_lpc. BUG=chromium:516122 BRANCH=none TEST=Compile. Work in cyan branch. Change-Id: Id8d9487ea6f376728eaa57728baceda7e5f6b2b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6380104986d2740a14fc74161fec9f2994d2affc Original-Change-Id: I682d68e0858327ec7c0fbd0924dd9f99527d4df0 Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/342363 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-06ec/google/chromeec/ec_lpc: Declare used IO ports as a resourceAlexandru Gagniuc
Chrome EC uses IO ports 0x800 -> 0x9ff to communicate over LPC; however, those ports were not declared as a resource. This had two major downsides: * It allowed the allocator to assign said ports to other devices * It required manually open up an IO window in the LPC bridge. The LPC bridge on many chromeec boards had to be painstakingly adjusted to meet these constraints. The advantage of declaring the resources upfront is that the lpc bridge can now scan its child resources and automatically open up IO windows, as requested by its LPC children devices. Change-Id: I35c4e48dddb7300674d7a9858b590c1f20e3b0e3 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14585 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-06ec/google/chromeec/ec_commands.h: Include stdint.hAlexandru Gagniuc
This file use stdint types, but does not include the appropriate header. This creates a parasitic dependency on including stdint.h before ec_commands.h. Fix that by including the necesarry header. Change-Id: I52477028c4ba8f6ffad0356c09e5fad4972649ed Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14589 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-05Hide EC_GOOGLE_CHROMEEC_SPI_BUS.Vladimir Serbinenko
It's mobo architecture, not a user-adjustable setting. Change-Id: I8bb81638f391cf0ba880801e4707d8f0957897c8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13906 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-09build system: Build Chrome EC firmware on requestPatrick Georgi
With the Chrome EC's "board" name set in Kconfig, the build system will build and add the EC firmware, too. Available for the EC and the USB PD controller. Change-Id: I017d3a44d6ab8a540fcd198b4b09c35e4b98a8cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13547 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04google/chromeec: implement vboot_(save|retrieve)_hash APIAaron Durbin
For x86 systems which resume through the reset vector one needs to ensure the the RW slot taken at resume time matches the one at boot time. To that end, allow Chrome OS EC to supply the plumbing to vboot for storing and retrieving the RW slots' hash digest using the vstore backend. BUG=chrome-os-partner:46049 BRANCH=glados TEST=Suspended and resumed on chell. Also, tested with an EC build which returns a bad hash to ensure that is properly caught. Change-Id: Ib056f7e6b3386447ed1ff95c740ef5b4544f9049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c78546b1d6298a4c397a587c564df6d9d097e75 Original-Change-Id: I86c96a4092deab2dfa51b3043b9dba16b6a4c201 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/323502 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13577 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/chromeec: Add temporary storage interfaceDuncan Laurie
Add support functions for the Chrome EC temporary storage interface. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados with modified coreboot Change-Id: Id2bc46df9cb2d82b15e3309e78d07407a622b6f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7e6f693666b162e11eb0611715f10a8f465ad88 Original-Change-Id: Ieefabfc5bcb9d8a5064f0da967c46d0f377ca320 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315217 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13572 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04google/chromeec: Update EC command headerDuncan Laurie
Update to the latest EC command header. BUG=chrome-os-partner:46049 BRANCH=none TEST=emerge-glados coreboot Change-Id: I132f91b31931ed40c20c0f5dbbf4449663768418 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e6d9d51cfe99fe7c3806d1f74ea67b2d2ed5e7e Original-Change-Id: I3c2e268689d64683f4a138e20f518e6eda49a138 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315216 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13571 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-01drivers/pc80: Add PS/2 mouse presence detectTimothy Pearson
On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-28ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant.Freddy Paul
TEST=Plug/Unplug AC Adapter multiple times and make sure device is charging properly. Original-Reviewed-on: https://chromium-review.googlesource.com/303990 Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Original-Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Signed-off-by: Freddy Paul <freddy.paul@intel.com> Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/12748 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14ec/: add missing license headersMartin Roth
thermal.asl was written as part of the coreboot project, so gets the standard coreboot license header. ec_commands.h came from the chrome ec tree, so gets the BSD license from that tree as mentioned in the header that has been replaced. Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-27ec/chrome: Disable LPC Continuous Serial IRQ Selectpchandri
This patch removes the auto select of SERIRQ_CONTINUOUS_MODE as part of the EC_GOOGLE_CHROMEEC_LPC. BUG=chrome-os-partner:44993 BRANCH=none TEST=Builds and Boots on fab3 kunimitsu. Change-Id: I4aed2c53bfdcbb8f7cd28f9a23fad86c9cd5086e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 90a1e0785857a4da556e7664a8b83e9c8a0a78a7 Original-Change-Id: Ia411966bab557c269afa1d7e88ab2550eb35447e Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/305580 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/12155 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-15ec/google: Move label to BOL to satisfy lint-testsPatrick Georgi
Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11886 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-28chromeec: Fix ACPI compile warningsDuncan Laurie
Recent version of iasl are flagging more things as warnings. Remove unused Local0 uses and make _CRS method serialized to fix these warnings. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I1d4535205426dd9a6346f53ff159221cf5cd899a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8b43f8f24bb7cb33ad0411c24616da66663c2e3e Original-Change-Id: I71eafd91d30d5f50e6211368f0bbc517c8085892 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302163 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28ec: superio: Report keyboard IRQ as wake capableDuncan Laurie
In order to wake from S0ix the kernel needs to know that the keyboard interrupt is wake capable. Using IRQNoFlags does not allow the wake capability to be reported. For normal S3 this does not matter as the EC is the one handling the keyboard wake event. For S0ix the EC does not need to be involved in this particular wake event. BUG=chrome-os-partner:43079 BRANCH=none TEST=echo freeze > /sys/power/state and wake from keyboard Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373 Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/301441 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11712 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-09chromeec: Add kconfig entry for EC PD supportDuncan Laurie
Add a kconfig entry to indicate that a board has a PD chip and try to put it in RO mode before the EC during early init. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I170271de9b929fcb73d6b0e09171385a6d23f153 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 17e2d13261f4e35a8148039e324e22ec1da64b3c Original-Change-Id: I44eed5401beb1dc286e316cf0cc958da791580a5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297747 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11571 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-07Drop "See file CREDITS..." commentStefan Reinauer
coreboot has no CREDITS file. Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-01chromeec: Move keyboard backlight code into Chrome EC directoryDuncan Laurie
Since more boards are starting to use the EC provided keyboard backlight interface move the code to a common place and allow it to get included in mainboards. Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/11478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-27chromeec: Add helper function to read EC switch stateDuncan Laurie
Add a helper function to read the EC switch state on LPC based ECs instead of having each board need to understand and use the specific EC LPC IO method that is required. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293514 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11280 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-21mec: Correct the access mode for short payloadsJagadish Krishnamoorthy
If the Host Command payload is less than 4 bytes and is word aligned then the payload was not transferred at all. EC reads the old packet and CRC mismatch occurs. In this issue, the HC command packet consisting of EC_CMD_REBOOT_EC as command and EC_REBOOT_COLD as payload encountered the same problem as above. Hence select byte access mode for shorter payloads. BRANCH=None BUG=chrome-os-partner:42396 TEST=System should boot after chromeos-firmwareupdate Change-Id: I22bdb739108d31b592c20247be69c198d617d359 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8a43d2636b1bbfbac0384e1ea5e8853a7bd87a7f Original-Change-Id: I5572093436f4f4a0fc337efa943753ab4642d8e4 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286537 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/11012 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30EC: Add new EC host event for FASTBOOT_MODE requestFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Change-Id: Id24b87e03097eb93c0b4316c853575629e5502aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf80de709d2bf310a3a37b9897063d2d833933b9 Original-Change-Id: Ia5d42efd81b59c1b99d3be5be6d0c770ad602429 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/280879 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-29kbuild: automatically include ECsStefan Reinauer
This change switches all ECs and the generic EC ACPI code to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in ec/Makefile.inc or in ec/<vendor>/Makefile.inc. This means, vendor and ec directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I29d757d1f8c10a1d0167a76fd0d0f97bac576f6d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9798 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-28chromeos: remove VBOOT2_VERIFY_FIRMWARE optionAaron Durbin
There's no need to have the VBOOT2_VERIFY_FIRMWARE distinction because it's the only game in town. Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9958 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-27chromeec: ec_mec: Fix misaligned data accessShawn Nematbakhsh
Long auto-increment access cannot be used when our initial address is misaligned or when our terminal address is misaligned on write operations. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on cyan. BRANCH=None Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354 Original-Reviewed-on: https://chromium-review.googlesource.com/266653 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9987 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Add variant MEC IOShawn Nematbakhsh
MEC cannot access memmap-range data directly though LPC and instead must access through its EMI unit. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on glower. BRANCH=None Change-Id: If98d425014a894ddeafad4268f92af5860878522 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ed3c50ab97ca1e172d5cdc00f4cd8e069e565c Original-Change-Id: I32b897836d28ef4f3b3aa5f81b9023f2ceb629c8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263611 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22chromeec: lpc: Read / write IO ports through common functionsShawn Nematbakhsh
Rather than calling inb + outb directly, access the ports through common functions. This is in preparation for alternative access modes required by certain new embedded controllers. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Verify system boots cleanly in normal mode. BRANCH=None Change-Id: I98783ff67a37d970019683bb589825bc5d68c033 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25afa3f95183d8cf2e9a35272c77e92fbc6ee030 Original-Change-Id: Ic9d8f7f5c5d392212e39db28ebceea461d46f796 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263571 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9909 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 09:19:45 +0000