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2020-06-14ec/google/chromeec: Call \PNOT () on initializing AC power stateFurquan Shaikh
This change calls \PNOT () method when AC power state is initialized to allow platform code to take appropriate action. BUG=b:157752693 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08ec/google/chromeec: Append connector device to *-switch propertiesTim Wawrzynczak
The orientation, etc. -switch properties are supposed to use the connector device (underneath the MUX device) that belongs to the port number in question. This patch finds the CONx device and uses that to pass to the acpigen API. BUG=b:154620502 TEST=on Volteer, dump SSDT and verify the *-switch properties point to \_SB.PCI0.PNC.MUX.CON0 and CON1 Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-06ec/google/wilco: Always use current value of battery status bitMathew King
According to the Wilco EC spec the BTSC bit of PWSR is always cleared when PWSR is read so that battery status change events are only triggered one time. Testing of the Wilco EC has verified this behavior. This changes the way in which the battery status change bit is used from checking the bit state against the previous value to always issuing a battery event when the BTSC bit is set. The other bits in PWSR indicate state directly and do not behave like the BTSC bit. BUG=b:157113138 TEST=Deploy on Drallion and verify that battery events are generated BRANCH=drallion, sarien Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove unused 'include <bootmode.h>'Elyes HAOUAS
Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28ec/google/chromeec: Switch to use new acpigen_usb moduleTim Wawrzynczak
Implementation of the ACPI objects for the Type-C Connector Class was added in the previous patch. This patch removes the functionality from the ChromeEC's SSDT generator, and uses acpigen_usb instead. TEST=Verified contents of SSDT are the same. Change-Id: Icdbcee1f989ee3146f7495e08fc13f9386791858 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28ec/google/chromeec: Add new *-switch properties to USBC.CONx devicesTim Wawrzynczak
The Linux ChromeOS EC driver now looks for 3 new properties under each USBC.CONx device contained within the ChromeOS EC device. These properties are just a reference to the device that controls the switches for USB 2/3 muxing, SBU lines, and CC lines. It uses the new function, soc_get_pmc_mux_device() to retrieve the device. Change-Id: I03cd83f9b2901b5583053fac8ab6eab64717a07d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40618 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27ec/google/chromeec/acpi/superio: Add PS/2 Mouse ACPI entryRaul E Rangel
The PNP ID Means: PNP0F13 PS/2 Port for PS/2-style Mice BUG=b:145575366 BRANCH=none TEST=Verified mouse was initialized Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2a4f071ad54730ea75f75ebf1633a4a08f7f2dd0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080664 Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Commit-Queue: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41639 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTIONKyösti Mälkki
After removal of CAR_MIGRATION there are no more reasons to carry around ENV_STAGE_HAS_BSS_SECTION=n case. Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit zero-initializers. Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-21ec/google/chromeec/acpi: Add CROS EC CODEC deviceYu-Hsuan Hsu
This is currently used by trembyle. Add it in a common location so other boards can use it. BUG=b:147200751 BRANCH=none TEST=Able to get ec codec on trembyle Change-Id: Ie21cd813b0e3129f1c61d2de199532b25d3c70fa Signed-off-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2000271 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41575 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21ec/google/chromeec/i2c_tunnel: Fix missing constRaul E Rangel
This was missed in the refactor. BUG=b:157140753 TEST=Built trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I150e0b8a806042ef8001805eaefbce71dc1be0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41574 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Convert more license headers to SPDX stylePatrick Georgi
Change-Id: Ia3de79c7d71049da00ed108829eac6cb49ff3ed6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41205 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: move copyrights and authors to AUTHORSPatrick Georgi
Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01ec/google/chromeec: Fix incorrect diag messageVictor Ding
The expected error code observed in clear_pending_events() should be EC_RES_UNAVAILABLE(9), not EC_RES_INVALID_COMMAND(1). BUG=b:153896701 Change-Id: I609490ceef675267760d34b5e9775211da93347c Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22ec/google/chromeec: Add driver for i2c_tunnel device under Chrome ECFurquan Shaikh
This change enables support for generating ACPI nodes for I2C tunnel for any GOOG0012 device that is sitting behind the Chrome EC. It accepts a config "remote_bus" which allows mainboard to configure the id of the remote bus that is being tunneled. BUG=b:154290952 BRANCH=None TEST=Verified that SSDT node for I2C tunnel behind Chrome EC is generated correctly. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/40515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-22ec/google/chromeec: Add .scan_bus() callback for Chrome EC deviceFurquan Shaikh
This change adds scan_static_bus() as .scan_bus() callback for Chrome EC device which allows scanning of devices sitting behind the EC using the topology provided by mainboard's devicetree.cb. BUG=b:154290952 TEST=Verified with follow-up changes that devices behind EC are scanned correctly. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id3630db56774fba1e3fc53bf349588c4c585773b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40514 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22ec/google/chromeec: Fix acpi_name() for Chrome EC deviceFurquan Shaikh
In ACPI tables, Chrome EC device (CREC - HID GOOG0004) is a child of EC device (EC0 - HID PNP0C09). However, in coreboot device tree, there is no separate chip/device for EC0. Thus, acpi_name() needs to return EC0.CREC as the ACPI name for the Chrome EC device. By returning the ACPI name as EC0.CREC, all devices that live under Chrome EC device can simply call acpi_device_path()/acpi_device_scope() to emit the right path/scope. In the future, if we ever add a special chip driver for handling EC0 (HID PNP0C09), then the ACPI name for Chrome EC can be fixed to return CREC. BUG=b:154290952 TEST=Verified that acpi_device_path()/acpi_device_scope() return the correct name for Chrome EC device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Iec4b0226d1e98ddeb0f8ed8b89477fc4f453d221 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20ec/google/chromeec: Fill up SSDT for EC provided PS2 keyboardRajat Jain
Query the EC to get the top row layout, and if it provides one, generate the SSDT for the PS2 keyboard. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I75d2eee32c82b9bee73436b08b5f615d1b388148 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40032 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20google/chromeec: Add wrapper for EC_CMD_GET_KEYBD_CONFIGRajat Jain
Add a wrapper command for the subject command Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I29a4021c2ea0d1cbb4a72f56bf2232d8f9c80ac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-20google/chromeec: Revise parameters of EC USB PD API callGaggery Tsai
This patch adds voltage and curent parameters in google_chromeec_get_usb_pd_power_info and remove power parameter. Caller could use the voltage and current information to calculate charger power rating. The reason for this change is, some applications need the voltage information to calculate correct system power eg PsysPmax. BUG=b:151972149 TEST=emerge-puff coreboot; emerge-fizz coreboot Change-Id: I11efe6f45f2f929fcb2763d192268e677d7426cb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-04-17ec/google/chromeec: Update the USBC ACPI device hierarchyKarthikeyan Ramasubramanian
Type C connector class driver in kernel (v5.4) expects the Type C ACPI device under ChromeEC ACPI device scope. Currently the Type C ACPI device is populated under ChromeEC device's parent. This leads to incorrect casting of Type C's parent device and hence a crash. Move the Type C device under ChromeEC ACPI device. BUG=b:153518804 TEST=Build and boot the mainboard. Ensure that the USBC ACPI device is populated under ChromeEC ACPI device. Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (USBC) { Name (_HID, "GOOG0014") // _HID: Hardware ID ... } } Change-Id: I628489bc420d7a3db4ad3cb93d085d568c6de507 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-17ec/google/chromeec: Add host command EC_CMD_GET_KEYBD_CONFIGRajat Jain
Add command to query the EC for the keyboard layout. Also add supporting data structures for the exchange. Signed-off-by: Rajat Jain <rajatja@google.com> Change-Id: I26aff6dd0e701e0cecb3b66bc54c5a23688f0109 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-16ec/google/chromeec: add BOARD_VERSION CBI supportAaron Durbin
Obtaining the CBI_TAG_BOARD_VERSION value wasn't in the code base. Add the binding for it so it can be used. BUG=b:153640981 Change-Id: Ie2f289631f908014432596448e56b5048a196a10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13google/chromeec: Add USB MUX InterruptBrandon Breitenstein
Kernel relies on the USB MUX interrupt to configure USB devices that are connected on the Type-C ports for TGL. Adding in the Q1C Interrupt so the Kernel can properly receive and configure USB devices BUG=b:152902608 TEST=buld_packages for volteer and verified that Proto 1 and Proto 2 are now seeing extcon events Change-Id: Ie3a2f829a295f090a03e72e12f19ecc5bb724952 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Prashant Malani <pmalani@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13ec/google/chromeec: add smbios_mainboard_manufacturer()Aaron Durbin
When EC_GOOGLE_CHROMEEC_SKUID is selected provide an implementation of smbios_mainboard_manufacturer() so the code doesn't need to be duplicated in the mainboards. BUG=b:153767369 Change-Id: Ib65fe373a79d606cffcba71882b0db61be5a18c3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-11ec/google/chromeec: expose failure and unprovisioned SKU id valuesAaron Durbin
Provide CROS_SKU_UNKNOWN and CROS_SKU_UNPROVISIONED defintion so callers can utilize the default and failing value without open coding it. BUG=b:153642124 Change-Id: I447004e9016b6ab3306ea532721494ebbcda741d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40299 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-09ec/google/chromeec: Replace uses of ec_current_image with ec_imageFurquan Shaikh
This change replaces all uses of ec_current_image with ec_image since Chromium OS EC has deprecated (sha 78d1ed61d) the use of enum ec_current_image and instead changed it to enum ec_image. BUG=b:149987779 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7e45ea6c736b44040561f0f8a80f817ade8db864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-09ec/google/chromeec: Update ec_commands.hFurquan Shaikh
This change copies ec_commands.h directly from Chromium OS EC repo at sha b3c3f6a8f. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I940f5c7fe8ad4d989a1dfcd6da3ccf9fc151ec56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-05src/ec: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20ec/google/chromeec: don't put empty block in SSDTMatt DeVillier
Check that there are actually USB-PD ports for which to add data to SSDT, before actually generating SSDT data. This prevents an empty scope from being generated on devices without any USB-PD ports, which was breaking parsing/decompilation on some older platforms (eg, Braswell). Test: build/boot google/edgar, verify SSDT table able to be parsed via iasl after dumping. Change-Id: Ia213e5815e9160e9b36b2501eeccb6385abef47e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39665 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15ec/google/wilco: Store LID status into LIDS and change device nameEric Lai
Store LID status into LIDS and change device name to LID0. Then Intel driver can reference it. BUG=b:151134069 TEST=check LID status by evtest Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/39497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-03-14ec/google/chromeec/acpi: Move ECPD under CRECPrashant Malani
Move the ECPD (GOOG0003) device under CREC (GOOG0004) so that the ECPD AP device drivers can access the parent EC device to communicate with the EC. Also, update the Notify() call to reflect the new location of the ECPD device. Signed-off-by: Prashant Malani <pmalani@chromium.org> Change-Id: I830b030c7a063506f50f9cd51df3a5018e248fc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-06ec/google/chromeec: Fix dev ops for chromeecFurquan Shaikh
CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-04src/ec,mainboard: Move weak smbios_system_sku() override inwardsEdward O'Callaghan
Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c implementation and simply wrap a call to: google_chromeec_smbios_system_sku(). BUG=b:150735116 BRANCH=none TEST=none Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-04mainboard/google/octopus: Migrate onto SKU ID helpersEdward O'Callaghan
Leverage the common sku id space helper encoders and set the sku id max to 0xff for legacy to ensure we behave the same. BUG=b:149348474 BRANCH=none TEST=tested on hatch Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-02-28ec/google/chromeec: Introduce SKU_ID helpersEdward O'Callaghan
The following introduces helpers that, by default, accommodate a larger SKU id space. The following is the rational for that: Allow INT32_MAX SKU id encodings beyond UINT8_MAX. This allows for the SKU id to accommodate up to 4 bytes however we reserve the highest bit for SKU_UNKNOWN to be encoded. However, the legacy UINT8_MAX encoding is supported by leveraging the Kconfig by overriding it with the legacy max of 0xff. Follow ups migrate boards to this common framework. V.2: Fixup array size && drop sku_id SKU_UNKNOWN check and pass whatever is set to userspace as firmware doesn't care about the value. V.3: Use SPDX-License header. BUG=b:149348474 BRANCH=none TEST=tested on hatch. Change-Id: I805b25465a3b4ee3dc0cbda5feb9e9ea2493ff9e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-18ec/google/chromeec: Add SSDT generator for ChromeOS ECTim Wawrzynczak
Upcoming patches for the Linux kernel (5.6 ?) would like to consume information about the USB PD ports that are attached to the device. This information is obtained from the CrOS EC and exposed in the SSDT ACPI table. Also, the device enable for this PCI device is moved from ec_lpc.c to a new file, ec_chip.c, where EC-related ACPI methods can live. It still allows other code to call functions on device enable (so that PnP enable for the LPC device still gets called). BUG=b:146506369 BRANCH=none TEST=Verify the SSDT contains the expected information Change-Id: I729caecd64d9320fb02c0404c8315122f010970b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-17vboot: push clear recovery mode switch until BS_WRITE_TABLESJoel Kitching
Serves two purposes: (1) On some platforms, FSP initialization may cause a reboot. Push clearing the recovery mode switch until after FSP code runs, so that a manual recovery request (three-finger salute) will function correctly under this condition. (2) The recovery mode switch value is needed at BS_WRITE_TABLES for adding an event to elog. (Previously this was done by stashing the value in CBMEM_ID_EC_HOSTEVENT.) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-01ec/google/wilco: Set cpu id and cores to ECEric Lai
Set CPU ID and cores to EC then EC will adapt power table according to the CPU ID and number of cores. BUG=b:148126144 BRANCH=None TEST=check EC can get correct CPU id and cores. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01ec/google/chromeec: Add new wrappers for host commandsTim Wawrzynczak
Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-01ec/google/chromeec: Add new host command, EC_CMD_GET_PD_PORT_CAPSTim Wawrzynczak
The new host command provides these static capabilities of each USB-PD port: 1) Port number 2) Power role: source, sink, dual 3) Try-power role: none, sink, source 4) Data role: dfp, ufp, dual 5) Port location: these come from power_manager BUG=b:146506369 BRANCH=none TEST=compiles Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-27ec/google/wilco: add ec command set cpu idEric Lai
Add new mailbox command support. Set CPU ID and cores to EC. EC will according to different CPU to set different power table. BUG=b:148126144 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I135d2421d2106934be996a1780786f6bb0bf6b34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-01-22ec/google/chromeec: add support for fw_config cbi fieldJett Rink
The firmware configuration (fw_config) field is store in the CBI EEPROM and it should be used to make firmware customization instead of sku/variant id. BUG=b:145519081 TEST=builds Change-Id: I790998a29e724ecdff8876cca072267537b7cea6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-22ec/google/chromeec: update ec_commands.hJett Rink
Copy ec_commands.h directly from Chromium OS EC repo at sha e57217a250. This is needed for the FW_CONFIG CBI field definition. Change-Id: Id010721033ebe32ac9c9482d666cf790442a26ee Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-01-18ec/google/wilco: Set minimum UCSI_ACPI region lengthBernardo Perez Priego
IMD provides support for small and large allocations. Region IMD Small memory is 1 KB with 32 Bytes alignment, this region holds smaller entries without having to reserve a whole 4 KB page. Remaining space is assigned to IMD Large to hold various regions with 4 KB alignment. The UCSI kernel (kernel version 4.19) driver maps the UCSI_ACPI memory as not cached. Cache mapping is set on page boundaries and all IMD Small is within the same page. If another driver maps the memory as write-back before the UCSI driver is loaded then the UCSI driver will fail to map the memory as not cached. Placing UCSI_ACPI in IMD Large region will prevent this mapping issue since it will now be located within its own page. This patch will force UCSI_ACPI region to be located in IMD Large region. BUG=b:144826008 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Id00e76dca240279773a95c8054831e05df390664 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38414 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/{skylake,common}/acpi/dptf/thermal.asl: Prevent iasl remarksWim Vervoorn
Prevent iasl remarks about unused parameters. BUG=N/A TEST=build Change-Id: I54fa4712e618038fdd5a96c2012c2ec64ca34706 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-29ec/google/chromeec: ignore LIMIT_POWER based on command code in responseRizwan Qureshi
Assume that LIMIT_POWER is not requested if the ec does not support it. Do this by checking the command code in the response message instead of return value. BUG=b:146165519 BRANCH=None TEST=Boot puff with EC which does not support LIMIT_POWER param. Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-12-27ec/google: Fix wedging AP on early ec sw syncTim Wawrzynczak
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power limits to reasonable defaults and can wedge the AP by browning out at the end of vboot. BRANCH=none BUG=b:146165519 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src/{drivers,device,ec}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32822 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-17src: Conditionally include TEVTFrans Hendriks
ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized), which indicates the TEVT method is empty. The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT. The TEVT method will be removed from the ASL code when the EC does not support TEVT. BUG=N/A TEST=Tested on facebook monolith. Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16ec/google/chromeec/acpi: move PS2K under PCI0Matt DeVillier
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node] moved the PS2K ACPI device from under the SIO device to under the LPCB, and while this fixed the keyboard under Windows for Skylake devices, it was insufficient for Baytrail and Braswell devices (and likely Apollo Lake/Gemini Lake too). Moving the PS2K device under PCI0 allows the PS2K to be functional under Windows for all Chrome-EC platforms. Test: build/boot various Chrome-EC devices from IVB, HSW, BDW, BYT, SKL, BSW, and KBL platforms, verify keyboard functional under both Linux (4.x and 5.x) and Windows 10. Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02ec/google/wilco: Add EC ACPI methods for privacy screenMathew King
Add ACPI methods to the Wilco EC for controlling a privacy screen on the device. BUG=b:142237145, b:142656363 TEST=none Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36044 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29ec/google/chromeec: Drop CAR_GLOBAL_MIGRATION supportArthur Heymans
Change-Id: I09bca1897920871a6b29c25dc2bad94a8061da29 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37038 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-18include: Make stdbool.h a separate fileJulius Werner
This patch moves the traditional POSIX stdbool.h definitions out from stdint.h into their own file. This helps for using these definitions in commonlib code which may be compiled in different environments. For coreboot everything should chain-include this stuff via types.h anyway so nothing should change. Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-09ELOG: Introduce elog_gsmi variantsKyösti Mälkki
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04include: Remove EC_EVENT_* from elog.hYu-Ping Wu
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_* macros defined in ec_commands.h, which is synchronized from Chromium OS ec repository. BRANCH=none BUG=none TEST=emerge-kukui coreboot Change-Id: I12c7101866d8365b87a6483a160187cc9526010a Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-31ec/google/chromeec: Add EC driver support for software syncTim Wawrzynczak
Quite a few new functions added here in order to support the use-case of performing EC software sync within coreboot. Most of these functions are related to retrieving the EC's hash, and writing a new image into the EC's flash. BUG=b:112198832 BRANCH=none TEST=With whole patch series, successfully performed EC software sync Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-29ec/google/chromeec: Clean up ec.[ch]Tim Wawrzynczak
Change all uN integral types to uintN_t. Make the names of host command params/responses consistent. Use static struct initialization to ensure all fields are initialized. BUG=none BRANCH=none TEST=compiles Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-25ec/{compal,google,quanta}: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24(acpi) superio.asl: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-24ec/google/chromeec/acpi: Drop wrong _ADR objectElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-09ec/google/chromeec: fix format security warningGreg V
Change-Id: I7a7bcb56523d595e8d4f32849aac53d66d416a12 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35866 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabledMartin Roth
Don't set a default bus type for the Chrome EC on x86. The platform must select the bus, typically LPC or ESPI. BUG=b:140055300 TEST=Build tested only Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-163rdparty/chromeec: Update to latest masterElyes HAOUAS
It's been some time and there are 1420 new commits. Including one that allows reproducible builds \o/ and one that breaks building with empty $(CC) :-/ Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-02vboot: remove fastboot supportJoel Kitching
Fastboot support in vboot_reference is unused, unmaintained, and produces compile errors when enabled. Since there is no current or planned use cases for fastboot, remove it. BUG=b:124141368, chromium:995172 TEST=make clean && make test-abuild BRANCH=none Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35002 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30ec/google/chromeec: Add config option for eSPIMartin Roth
The Intel platforms using eSPI EC communication have just been enabling the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically the same, but at least marks it as eSPI in Kconfig for clarity. BUG=b:140055300 TEST=Build tested only. Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35128 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-23google/chromeos: Support AP watchdog flag from Chrome ECYou-Cheng Syu
After ChromiumOS CL:1293132 and CL:1295890, Chrome EC can store the flag telling if the last reboot was triggered by AP watchdog for some boards (e.g., Kukui). This CL adds a new function google_chromeec_get_ap_watchdog_flag(), which reads the AP watchdog flag from Chrome EC, and updates the tables of reset causes and reset flags. A new Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is added for elog_handle_watchdog_tombstone() to determine if watchdog reset was triggered by the AP watchdog flag from EC instead of the tombstone in AP. BUG=b:109900671,b:118654976 BRANCH=none TEST=test with https://review.coreboot.org/c/coreboot/+/31843 Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-23ec/google/chromeec: Update ec_commands.hYou-Cheng Syu
Copy ec_commands.h directly from ChromiumOS EC repository (CL:1520574). Since ec_commands.h already defines usb_charge_mode and only USB_CHARGE_MODE_DISABLED is used in coreboot, enum usb_charge_mode is removed from ec.h. To avoid redefinition of the BIT macro, #ifndef check is added to include/types.h. BUG=b:109900671,b:118654976 BRANCH=none TEST=emerge-kukui -j coreboot Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31885 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21chromeec: Depend on events_copy_b to identify the wake sourceRavi Chandra Sadineni
google_chromec_get_event() depends on the main copy of EC which is used by ACPI subsytem in the kernel for querying events. google_chromeec_get_event() also clears the event from EC. Thus if the kernel has to identify the wake source, it has no way to do that. Thus instead depend on events_copy_b to log the wake source. Please look at go/hostevent-refactor for more info. BUG=b:133262012 BRANCH=None TEST=Hack hatch bios and make sure hostevent log is correct. Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-20src/ec: Drop __PRE_RAM__ and __SMM__ guardsKyösti Mälkki
For files built in ramstage and smm -classes, testing for !__PRE_RAM__ is redundant. All chip_operations are exluded with use of DEVTREE_EARLY in static devicetree, so garbage collection will take care of the !__SMM__ cases. Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-20devicetree: Remove duplicate chip_ops declarationsKyösti Mälkki
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-19ec/google/chromeec: Use MAYBE_STATICKyösti Mälkki
Change-Id: I4c6238b0e5f41fcc667baf6b486c7fff4c90a7cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34944 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25ec/google/wilco: Hide wilco symbols when unusedElyes HAOUAS
This cleans up .config file from unused wilco symbols. Change-Id: I813d3fe57b97e2c1ba67e1e3674de256c2529029 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34539 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18ec/google/chromeec: Pass reference of object to BBST() methodDuncan Laurie
The BBST() method writes an updated status flag mask that is intended to be stored back in the battery object. This value needs to be passed as a reference to an object to prevent it from being evaluated at the time the method is loaded or it will not actually update the BSTP value in the battery device. This was tested by instrumenting the _BST method in the primary battery and ensuring the value can be updated by the BBST method. Change-Id: Ia8e207a2990059a60d96d8e0f3ed3c16a55c50f4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-22src/ec: Use 'include <stdlib.h>' when appropriateElyes HAOUAS
Change-Id: Ifdb2dee08da45d698174583ee5ed44bf5a0243ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-21ec/google/chromeec/ec_lpc: Remove unneeded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: I98d0ab0d139186b312e8c1086c475ba6ef0b7d3b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-13ec/google/wilco: Read back from EC RAM after S0ix entryDuncan Laurie
We are seeing an EC interrupt after setting the EC RAM offset that indicates that the EC should transition to S0ix mode and this is preventing the kernel from going into S0ix on the first try. As a workaround if we read back from the EC RAM while still in the _DSM handler it seems to prevent this problem. BUG=b:130644677 BRANCH=sarien TEST=ensure s0ix entry works on the first try with sarien Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455 Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-07ec/google/wilco: Add UCSI supportDuncan Laurie
This change adds support for the UCSI specification in order to provide information about the Type-C port and an interface to perform power and data role swap. This change is split across the DSDT and SSDT, with the shared memory and operation region declared in the SSDT after being allocated in CBMEM. The OS will fill in the registers in the system memory region and then call the _DSM method wtih a read or write argument. The DSM method will copy the required registers to/from the system memory and the EC and perform the write or read action. Responses from the EC will generate a new SCI with event code 0x79 which will notify this UCSI ACPI device and the OS driver will take action to read status from the EC. BUG=b:131083691 Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-24ec/google/wilco: Fix radio control commandDuncan Laurie
This command is working as written, but it is not actually correct as to what the format of the command should be. Fix this and add define the other radios. There is no change in the command send to the EC. Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-05-22ec/google/wilco: set diagnostic LEDs on boot failureKeith Short
On Wilco devices, if any of the coreboot stages fails with a fatal error, set the diagnostic LEDs with the Wilco EC. The last saved post code is used to determine the error code sent to the EC. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). TEST=Forced a fatal error in both bootblock and verstage to confirm diagnostic LEDs during these stages. This works on cold-boots only. Bug b:132622888 tracks the mailbox failures on warm boots. Change-Id: If865ab8203f89e499130f4677fec166b40d80174 Signed-off-by: Keith Short <keithshort@chromium.org> Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-20ec/google/wilco: Add support for KB_ERR_CODE to Wilco ECKeith Short
Adds support for the KB_ERR_CODE command on the Wilco EC. This command is used to drive diagnostic LEDs on the platform after a failed boot. This change also adds the Wilco EC mailbox command support to bootblock and verstage so that those stages can use the KB_ERR_CODE command. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32776 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18ec/google/wilco: Support board_id with EC provided IDDuncan Laurie
The EC can return a board ID value similar to the Chrome EC. In order to use this for the board version returned by SMBIOS this commit implements the board_id() function for mainboards that use this EC. BUG=b:123261132 TEST=Check /sys/class/dmi/id/board_version to see that it is reflecting the value that the EC provides. Change-Id: I3fbe0dc886701f37d2424fe7a2867fd860fa1ec0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32276 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-18ec/google/wilco: Send "logo displayed" progress codeDuncan Laurie
This progress code enables keyboard backlight control that otherwise would only work 30 seconds after boot. This code is already defined but it was not being sent by coreboot. It is run in the "post device" step between the other defined progress codes. BUG=b:130754032 Change-Id: Ica6c622e568cb236c17bf3edb6639d0177510846 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-28ec/google/wilco: Add ACPI _BIX method for batteryDuncan Laurie
I added a method to fill out the _BIX package structure but never hooked it up to the expected _BIX method that the OS uses. This change adds _BIX method and uses the existing method to fill it out. It also adds ^ before the _UID in _BIF to match _BIX as the _UID is one level above the method. Change-Id: I0de91369b6780fd9432990732c1078a73f6a3419 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-28ec/google/wilco: Add a romstage init function to send progress codeDuncan Laurie
When using FSP with debug enabled it takes too long to get to ramstage and send the first progress code to the EC. The same thing has been reported to happen when 2x16GB memory is installed. BUG=b:127875364 TEST=boot with FSP debug and ensure EC does not try to turn off the system while it is still booting. Change-Id: I5676354f5e53540273a9029411507f91864735a1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-21Revert "UPSTREAM: ec/google/wilco: Enable software sync for VBOOT"Duncan Laurie
This reverts commit 51169b7dda4a1978d622e329a1c40e384471c165. I was not ready to enable this option yet, until it is enabled in depthcharge it needs to stay off in coreboot or depthcharge will attempt to do software sync without a proper driver. Change-Id: I4840812d0541f822502cfc5c66bed27edf4d2ecc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32007 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-21ec/google/wilco: Add function to indicate if EC uses signed FWDuncan Laurie
This will be used to distinguish the mainboard SKU so that the correct EC firmware can be bundled with the board. This is read from EC RAM so it can be used by an ACPI method in the future. BUG=b:119490232 Change-Id: I71b8017fc4b88e793dfe709e1cb1ab0f0bcdc4fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-18ec/google/wilco: Enable software sync for VBOOTDuncan Laurie
Enable software sync by default if VBOOT is enabled. The slow update option is also needed, but this is moving to depthcharge so it is not defined here. Change-Id: I046661fae7315f84e96293532b4e1568558df962 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 21:08:25 +0000