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Change-Id: I5c77b6d1e1dc1134f62dcb3e93df01dc9c2f386c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71520
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie5355e05982b372ef69515cfa081e2afbc7b09fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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_PRS only makes sense if _SRS is implemented.
Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Also sort includes.
Change-Id: I93f02674fde0415e4d831ec13541a806bbc3bd91
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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PS2K device needs to be under PCI0, not LPCB, for Windows to
recognize it. Same change was made to ChromeEC previously.
Test: Boot Win11 on Drallion, verify built-in keyboard functional.
Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Set _STA to 0xB for GOOG000C/GOOG000E devices to prevent showing
as missing drivers under Windows.
Change-Id: I0887fd6e18528d2c8523e7bc66db9efaa31adf5d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68462
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These changes made my crude pattern matching work with
coccinelle simpler.
Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SYSTEM_TYPE_CONVERTIBLE is not valid SMBIOS enclosure type,
but selecting it implies SMBIOS_ENCLOSURE_CONVERTIBLE.
Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ia278b538a8904651d16c37d095972fa78e264288
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/7S5OJMLQUEIU6YK36JTTRINF5OOCI66V/
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Building google/sarien with a 64-bit compiler (x86_64-linux-gnu) fails
with the error below.
src/ec/google/wilco/mailbox.c: In function 'wilco_ec_transfer':
src/ec/google/wilco/mailbox.c:184:43: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
184 | printk(BIOS_ERR, "%s: data too short (%lu bytes, expected %zu)",
| ~~^
| |
| long unsigned int
| %u
185 | __func__, rs.data_size - skip_size, msg->response_size);
| ~~~~~~~~~~~~~~~~~~~~~~~~
| |
| size_t {aka unsigned int}
`data_size` has type `uint16_t`, and `skip_size` has type `size_t`,
whose size differs in 32-bit (unsigned int) and 64-bit (unsigned long).
So use the length modifier `z` for a `size_t` argument.
Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110
Change-Id: Ida27323daeed9b8ff487302d0f3d6fcce0bbb705
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie
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Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Individual drivers check whether the concerned device is enabled before
filling in the SSDT. Move the check before calling acpi_fill_ssdt() and
remove the check in the individual drivers.
BUG=None
TEST=util/abuild/abuild
Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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If a UCSI event comes in when the EC is in S0ix mode then the kernel
driver attempts a transaction but fails and this can leave the system
in an unexpected state where the only wake source is the power button.
This change will not notify the UCSI driver if the EC is in S0ix mode
and instead keep track of the event and send it on resume.
BUG=b:157923800
TEST=tested on drallion system:
1. Put drallion system into suspend
2. Attach power supply
3. Ensure the system can wake with keypress
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I43acb089385d9b41ac955f053e409daad67423f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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According to the Wilco EC spec the BTSC bit of PWSR is always cleared
when PWSR is read so that battery status change events are only
triggered one time. Testing of the Wilco EC has verified this behavior.
This changes the way in which the battery status change bit is used from
checking the bit state against the previous value to always issuing a
battery event when the BTSC bit is set. The other bits in PWSR indicate
state directly and do not behave like the BTSC bit.
BUG=b:157113138
TEST=Deploy on Drallion and verify that battery events are generated
BRANCH=drallion, sarien
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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<types.h> is supposed to provide <commonlib/bsd/cb_err.h>,
<stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes
each time when <types.h> is included.
Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`.read_resources` and `.set_resources` are the only two device
operations that are considered mandatory. Other function pointers
can be left NULL. Having dedicated no-op implementations for the
two mandatory fields should stop the leaking of no-op pointers to
other fields.
Change-Id: I6469a7568dc24317c95e238749d878e798b0a362
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.
Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Store LID status into LIDS and change device name to LID0.
Then Intel driver can reference it.
BUG=b:151134069
TEST=check LID status by evtest
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Set CPU ID and cores to EC then EC will adapt power table
according to the CPU ID and number of cores.
BUG=b:148126144
BRANCH=None
TEST=check EC can get correct CPU id and cores.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new mailbox command support. Set CPU ID and cores to EC.
EC will according to different CPU to set different power table.
BUG=b:148126144
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I135d2421d2106934be996a1780786f6bb0bf6b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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IMD provides support for small and large allocations. Region IMD Small memory is 1 KB
with 32 Bytes alignment, this region holds smaller entries without having to reserve a
whole 4 KB page. Remaining space is assigned to IMD Large to hold various regions with
4 KB alignment.
The UCSI kernel (kernel version 4.19) driver maps the UCSI_ACPI memory as not cached.
Cache mapping is set on page boundaries and all IMD Small is within the same page.
If another driver maps the memory as write-back before the UCSI driver is loaded then
the UCSI driver will fail to map the memory as not cached.
Placing UCSI_ACPI in IMD Large region will prevent this mapping issue since it will
now be located within its own page. This patch will force UCSI_ACPI region to be
located in IMD Large region.
BUG=b:144826008
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Id00e76dca240279773a95c8054831e05df390664
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I05422ee4b0aa5c02525ef0b4eccb4dc3ecf871e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32822
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not
enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized),
which indicates the TEVT method is empty.
The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses
this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT.
The TEVT method will be removed from the ASL code when the EC does not support TEVT.
BUG=N/A
TEST=Tested on facebook monolith.
Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Add ACPI methods to the Wilco EC for controlling a privacy screen
on the device.
BUG=b:142237145, b:142656363
TEST=none
Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36044
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.
Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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These are only referenced inside auto-generated static.c
files, and util/sconfig also generates the declarations
automatically from source file pathnames.
Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This cleans up .config file from unused wilco symbols.
Change-Id: I813d3fe57b97e2c1ba67e1e3674de256c2529029
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34539
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifdb2dee08da45d698174583ee5ed44bf5a0243ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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We are seeing an EC interrupt after setting the EC RAM offset that
indicates that the EC should transition to S0ix mode and this is
preventing the kernel from going into S0ix on the first try.
As a workaround if we read back from the EC RAM while still in the
_DSM handler it seems to prevent this problem.
BUG=b:130644677
BRANCH=sarien
TEST=ensure s0ix entry works on the first try with sarien
Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for the UCSI specification in order to
provide information about the Type-C port and an interface to
perform power and data role swap.
This change is split across the DSDT and SSDT, with the shared
memory and operation region declared in the SSDT after being
allocated in CBMEM.
The OS will fill in the registers in the system memory region and
then call the _DSM method wtih a read or write argument. The DSM
method will copy the required registers to/from the system memory
and the EC and perform the write or read action.
Responses from the EC will generate a new SCI with event code 0x79
which will notify this UCSI ACPI device and the OS driver will take
action to read status from the EC.
BUG=b:131083691
Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This command is working as written, but it is not actually correct
as to what the format of the command should be. Fix this and add
define the other radios. There is no change in the command send to
the EC.
Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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On Wilco devices, if any of the coreboot stages fails with a fatal
error, set the diagnostic LEDs with the Wilco EC. The last saved
post code is used to determine the error code sent to the EC.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).
TEST=Forced a fatal error in both bootblock and verstage to confirm
diagnostic LEDs during these stages. This works on cold-boots only. Bug
b:132622888 tracks the mailbox failures on warm boots.
Change-Id: If865ab8203f89e499130f4677fec166b40d80174
Signed-off-by: Keith Short <keithshort@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Adds support for the KB_ERR_CODE command on the Wilco EC. This command
is used to drive diagnostic LEDs on the platform after a failed boot.
This change also adds the Wilco EC mailbox command support to bootblock
and verstage so that those stages can use the KB_ERR_CODE command.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I96d17baf57694e4e01c676d80c606f67054cd0c3
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EC can return a board ID value similar to the Chrome EC.
In order to use this for the board version returned by SMBIOS
this commit implements the board_id() function for mainboards
that use this EC.
BUG=b:123261132
TEST=Check /sys/class/dmi/id/board_version to see that it
is reflecting the value that the EC provides.
Change-Id: I3fbe0dc886701f37d2424fe7a2867fd860fa1ec0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32276
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This progress code enables keyboard backlight control that
otherwise would only work 30 seconds after boot. This code
is already defined but it was not being sent by coreboot.
It is run in the "post device" step between the other defined
progress codes.
BUG=b:130754032
Change-Id: Ica6c622e568cb236c17bf3edb6639d0177510846
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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I added a method to fill out the _BIX package structure but never
hooked it up to the expected _BIX method that the OS uses.
This change adds _BIX method and uses the existing method to fill
it out. It also adds ^ before the _UID in _BIF to match _BIX as
the _UID is one level above the method.
Change-Id: I0de91369b6780fd9432990732c1078a73f6a3419
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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When using FSP with debug enabled it takes too long to get to ramstage
and send the first progress code to the EC. The same thing has been
reported to happen when 2x16GB memory is installed.
BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.
Change-Id: I5676354f5e53540273a9029411507f91864735a1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This reverts commit 51169b7dda4a1978d622e329a1c40e384471c165.
I was not ready to enable this option yet, until it is enabled
in depthcharge it needs to stay off in coreboot or depthcharge
will attempt to do software sync without a proper driver.
Change-Id: I4840812d0541f822502cfc5c66bed27edf4d2ecc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32007
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will be used to distinguish the mainboard SKU so that the
correct EC firmware can be bundled with the board.
This is read from EC RAM so it can be used by an ACPI method in
the future.
BUG=b:119490232
Change-Id: I71b8017fc4b88e793dfe709e1cb1ab0f0bcdc4fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable software sync by default if VBOOT is enabled.
The slow update option is also needed, but this is moving
to depthcharge so it is not defined here.
Change-Id: I046661fae7315f84e96293532b4e1568558df962
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If the command does not respond the driver should not wait for
it to complete before returning.
Tested with SMI debug enabled to ensure that the final command
does not report a failure.
Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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To ensure the power button functions as expected in firmware ensure
that the EC is not in "S0ix supported OS" mode and expecting the
power button to be handled by the virtual button interface.
BUG=b:128409889
TEST=Verify that the power button works at the developer screen
when the system is rebooted from within Chrome OS. Also ensure
that it works when external warm reset signal is asserted by H1.
Change-Id: Ic323515e3b8be08bac4f0f82e25f2f78c2f22833
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Both tent mode (0x01) and tablet mode (0x02) should be considered tablet
mode by ChromeOS.
BRANCH=none
BUG=b:122052438
TEST=ChromeOS enters tablet mode when lid angle exceeds 180
Change-Id: I89ba8141350fc628c8cff89d5f33aa47c6ae6afe
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31698
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function (preprocessor macro) we need is defined
in <endian.h> not <swab.h>.
Change-Id: I3a86c7050bf853e3a56a15421132240e19f40912
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change fixes the power status events for AC and battery
events from the EC. The register that was being used is not
returning the expected information.
BUG=b:125472740
TEST=enable ACPI debug in the kernel and verify that AC and
battery insert/remove are detected properly.
Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add an ACPI device that is compatible with the Intel Virtual
Button kernel driver for reporting tablet mode state and various
virtual button events that may come from the EC.
This driver is used in Windows and in the Linux kernel at
drivers/platform/x86/intel-vbtn.c
Because of a check in the kernel driver it expects the board to
define the SMBIOS enclosure type as convertible for the check at
driver load time for tablet/laptop and dock/undock to work.
The virtual tablet mode button will proxy the tablet mode state
sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel.
The virtual power button is used during S0ix for the EC to wake
the system with an SCI. There are separate press and release
events which are sent for completeness, although the kernel driver
will ignore the release event.
BUG=b:73137291
TEST=Test that the power button can wake the system from S0ix.
Also verify that the device is reported as laptop mode at boot.
Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31208
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a separate ACPI device for the Wilco EC event interface so that the
OS drivers can bind to it separately. Since the event handling is all
done with ACPI and not mailbox calls this will be implemented as a
standard acpi_driver in the kernel.
BUG=b:119046283
TEST=veriy device exists in DSDT
Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1) In the EC _REG method set the flag indicating S0ix support in the OS.
2) Add a function that can be called by the LPI _DSM method to indicate
to the EC that the OS is entering or exiting S0ix.
BUG=b:73137291
Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31094
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Send required EC command to enable ACPI S3 wake up from lid switch.
BUG=b:120748824
TEST=Put Sarien system into S3 and then wake up from lid switch
successful.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I13f3469847b0886147b8b624311a1ece796f847b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Send the EC command required to turn the camera power on
and verify that it shows up on the USB bus.
Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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There is a dependency issue with the EC DPTF code accessing
methods that are external, but once the mainboard includes the
relevant code they become internal and the current version of
IASL used by jenkins will fail to compile it.
Until the new IASL is deployed everywhere wrap the EC DPTF code
and expect that the mainboard will explicitly enable it.
Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add the support needed for DPTF. This includes the methods to
write trip point values, read temperatures, and handle events.
This was tested on a sarien board by inspecting AML debug output
with the kernel while monitoring temperatures and trip points in
sysfs and controlling temperatures with a fan to ensure that when
a trip point is crossed an SCI is generated and the event is
handled properly.
Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29761
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Disable debug output from read/write methods by default
- Use argument to _REG to disable SCI when EC is unregistered
- Change read/write macros to sync level 2 so they can be called
when a mutex is already held
- Define some missing events
Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29760
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Extended events will be handled by the OS kernel driver, but that
driver needs a method exposed by ACPI to read the event data from
the EC and into a buffer.
Tested by generating a hotkey event and reading the buffer from
the Linux kernel driver with acpi_evaluate_object().
Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29674
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add EC command to enable WiFi radio and send that command at
startup. Tested to ensure WiFi is functional on a sarien board.
Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29673
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the COM1 ACPI device based on the existing Kconfig option
CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to
also define another value for ACPI.
Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29672
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a way for the mainboard to provide a wake pin that the EC
will use to wake the system. This defines a _PRW object.
Change-Id: I94954104bbb8226683c37abc8c0465fe3c62a693
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29408
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The speakers start up muted, and the EC must be told by the BIOS
to unmute it. This helps prevent popping noises on boot/resume.
Change-Id: I693f1d01e46e19362ef8fd0d5b3f4930967b5a12
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI devices for the basic SuperIO functionality provided by the EC
for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART.
The specific defines to enable these devices should be declared by the
mainboard before including this ASL, the same as the Chrome EC behavior.
Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add methods to handle ACPI EC events at runtime. Currently only
some common events are handled like lid switch and battery info,
and the event status is printed for debug on other events.
Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the expected objects (_BST, _BIF, _BIX) for reading battery
information and status from the embedded controller, and the
expected objects for reporting AC power status.
The battery was tested by booting with a battery attached and checking
that it is present in /sys/class/power_supply/BAT0 and that the values
are consistent and within expected ranges.
The AC device was tested by checking the AC status in sysfs when AC
is inserted or removed while the system is running.
Change-Id: Ie996891c383c9e990736690aef9795512ad6d35a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the base ACPI support for the Wilco embedded controller, using
ASL 2.0 syntax throughout.
This includes the EC device and its resources, as well as the layout
for the EC RAM and the functions needed to read and write to the EC RAM.
The EC RAM address space is typically read/write, and so the ACPI EC
device expects that a defined Field can be read and/or written. With
this EC the read and write address spaces are different. For example,
a read from address zero will return data that is unrelated to what a
write to address zero expects.
This makes using a typical OperationRegion to describe the EC RAM
address space somewhat impracticle, since field definitions would
overlap. Instead, methods are provided for reading and writing to an
EC RAM offset, and the EC RAM layout is defined as a Package that
describes offset+mask for read or write fields within the EC RAM.
Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a function for use in bootblock stage that performs early init
of the EC, in particular setting it up for UART passthrough so a
legacy serial port can be used by the host.
This needs to be called by the mainboard that intends to use it
in bootblock in order for the UART to be available in later stages.
Some of the PNP style programming may look odd, but it is following
the EC specification which is not entirely standard. This code has
been tested on a board with this EC and it is functional.
Change-Id: I9d6935a9fdf0d7290a94bf2ee565ef2a7c00ecc7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Send a command to the EC on the way into S3 suspend state telling
it to save the PS/2 data, and on resume send it a command for
restoring the PS/2 data that was previously saved.
Change-Id: Ic4b5d6d2656dbb1c476b9211b0d60c71b0cd7b32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add EC handlers for specific SMM actions:
- on entry to sleep state tell the EC to save state and to prepare for
the host to enter sleep
- on ACPI enable/disable send command to the EC
- add a function to print SMI reasons when eSPI SMI is received
These need to be called by the mainboard handlers which will be done
when a board is added that uses this EC.
Change-Id: Ibabdc1462e0a8df405f9520244b83684e2ccf2f5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29119
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EC expects to receive updates about the BIOS boot progress. This is
used for the EC logging to track system boot completeness. If the EC is
not informed about BIOS progress it will turn the system off 30 seconds
after the boot starts.
Change-Id: I693c3930117db2b69a119aee0380d6f303c4881c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a chip_operations structure for Wilco EC and hook it into the device
tree so it can be initialized at boot.
Reserve the device resources specified in Kconfig, which will also
create the device IO windows if they have not been created in bootblock.
If the IO windows already exist (becauase they were specified in the
mainboard devicetree.cb) then this will find the existing entry instead.
During device init stage prepare the keyboard for use, which is required
for it to be functional in firmware and OS with this EC. Also send a
command to the EC telling it to pass the power button through to the
host for processing.
Change-Id: I0adb01cf394f939f4a28aeb47fe4d0bcda5957d9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add EC mailbox commands that are related to the power and state of the
system. These commands include:
- read the power status registers from the EC
- read & clear the power status registers
- helper function to read the current lid state
- tell the EC why the host is about to power off
- tell the EC that the host is about to enter a sleep state
Change-Id: Iaa7051b4006e3c1687933e0384d962516220621f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add basic supported mailbox commands for this embedded contrlller,
and define some command functions to retrieve and print information
about the EC.
Change-Id: Ibcef7d58e1852fdb2e52b97acd4b51a26dd8cd77
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add helper functions that make it more convenient to send and receive
the most common types of commands to the Wilco embedded controller.
Change-Id: I9cee1a3b2f9d507f6ecdfae9f4a34ba59056cb91
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29114
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Google "Wilco" Embedded Controller is a new embedded controller that
will be used in some future devices. The mailbox interface is simliar
to the existing Chromium EC protocol version 3, but not close enough
that it was convenient to re-use the full Chrome EC driver.
This commit adds the basic mailbox interface for ramstage which will be
used by future commits to send varous mailbox commands during the boot
process. The IO base addresses for the mailbox interface are defined in
Kconfig so they can be changed by the mainboard if needed.
Change-Id: I8520dadfa982c9d14357cf2aa644e255cef425c2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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