summaryrefslogtreecommitdiff
path: root/src/ec/google/chromeec/acpi
AgeCommit message (Collapse)Author
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-22chromeec: Support accessing memmap data over port 62/66Shawn Nematbakhsh
Some platforms cannot access the 900h-9ffh region over the LPC bus, so it's necessary to access memmap data over the ACPI cmd / data ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d Original-Reviewed-on: https://chromium-review.googlesource.com/262314 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-02chromeec: Add battery status event and re-enable _BIXDuncan Laurie
Add a new host event to send a notify(0x80) to the battery when the EC indicates that battery status has changed. The kernel has fixed the bug with _BIX method so it can be enabled now. BUG=chrome-os-partner:32196 BRANCH=samus TEST=build and boot on samus Change-Id: I1b8068df7abf1c8ebdc3a89602896b863accb7f3 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a779fc7f32729adb60d8bc220325444ebc20e0d2 Original-Change-Id: I0ebb17e5441e875875d98168ce3c31486d57330e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220320 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-27chromeec: Add ACPI device for PD MCU and handle related EC host eventShawn Nematbakhsh
Add ACPI device for PD MCU, if present. Call Notify routine when the corresponding EC host event is received. BUG=chrome-os-partner:31361 TEST=Manual on Samus. Enable EC_ENABLE_PD_MCU_DEVICE, unmask PD MCU host event, and verify ACPI Notify routine is called when host event is sent from EC. BRANCH=None. Original-Change-Id: I6db61031e434d7ecb211802a4caeaba051e22a28 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214809 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit 226b349e40ed8eacce20d0a8063877382f707c69) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iecff6c06f1b37651ff61e36d6085d397d66f861c Reviewed-on: http://review.coreboot.org/8968 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-09chrome ec: Add ACPI Device for ALS if enabledDuncan Laurie
The EC can export ALS information if the sensor is attached to it directly rather than to the host. This adds a basic ACPI ALS device and implements the required information. The kernel does not use the _ALR tuple set but it is required by the ACPI spec so this just adds the sample two point response curve defined in ACPI 5.0 section 9.2.5. The EC does not currently send events for lux value changes so a polling interval of 1 second is defined. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f Reviewed-on: http://review.coreboot.org/8132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-09-29google/chromeec: Notify DPTF charger participant on AC state changeDuncan Laurie
The DPTF charger particpant device needs to be notified when the AC state changes so it can re-evaluate the PPCC object and apply the proper charge rate limit if necessary. Change-Id: I6723754e2fe12862f50709875140fcadcddb18eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189029 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brad Geltz <brad.geltz@intel.com> (cherry picked from commit ed1ee577014421b021e8814edc91a1b696bf9eed) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-09-19chrome ec: Add support for limiting charger currentDuncan Laurie
Update the ec_commands header (direct from EC source) and add support for the new charger current limit interface which will be used by DPTF. Change-Id: Ia9a2a84b612a2982dbe996f07a856be6cd53ebdb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/185758 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1fcca2d75856ecefd3aeb1c551182aa76d649466) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6925 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-08-08chromeec: Implement full battery workaround at 6%Duncan Laurie
Currently the workaround for indicating a "full" battery kicks in at 3%, but this turns out to be too high for some devices. So move the workaround start point to 6% from full, or 94%. Change-Id: Ib4305df3a68e89f3a10a096d0e89d8105ea9037b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 982dc496a0553c90dee56fda6411b7c21a5d7da9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6521 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-04chrome ec: Add Methods for new EC eventsDuncan Laurie
The EC recently added events for Thermal and Battery shutdown to provide some sort of notification to the OS that it is about to pull power. Original-Change-Id: Ibbdb5f11b8fa9fc80612a3cc10667c612420b1bb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167301 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@google.com> (cherry picked from commit 03a53ed5e58caa018d49df193510d95bdf5bed7b) Change-Id: I0cdf89a60b541840029db58d49921340e7ab60eb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16d00848f48da83f6d6c813137a35af45bb05c4b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-13chrome ec: Fix temperature calcualtion in PATx methodsDuncan Laurie
The PATx methods will be passed a temperature in deci-kelvin, so it needs to be converted back to kelvin before being sent to the EC. The PAT disable method is changed to take the temperature ID as an argument so individual sensors can be disabled. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and esif_uf userspace application. Start and stop DPTF and see that temperature thresholds are set to sane values. Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182023 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: call DPTF thermal threshold event handlerAaron Durbin
When an EC thermal event occurs call the DPTF thermal threshold event handler to handle notifications. Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13chrome ec: Update header and add functions to support DPTFDuncan Laurie
The EC now supports two auxiliary programmable trip points for thermal monitoring. These are expected to be used by DPTF and need to be exported. In order to support these the header was updated from the latest chrome ec source. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181661 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09baytrail: Basic DPTF frameworkDuncan Laurie
This is not complete yet but it compiles and doesn't cause any issues by itself. It is tied into the EC pretty closely so that is part of the same commit. Once we have more of the EC support done it will need some more work to make use of those new interfaces properly. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: I4b27e38baae18627a275488d77944208950b98bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179459 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-30chromeec: allow override of i8042 interruptAaron Durbin
Some boards need to override which IRQ the i8042 keyboard controller has its interrupt on instead of the default IRQ#1. The SIO_EC_PS2K_IRQ macro provides the mainboard an ability to override the interrupt location. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi using this option. New IRQ is correctly picked up by kernel allowing keyboard support. Change-Id: Ic2b222018dfc3aa30e24a31009e832ae0fb7e9cf Reviewed-on: https://chromium-review.googlesource.com/177222 Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4978 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-30chrome ec: Fix ASL to use IO() instead of FixedIO()Duncan Laurie
FixedIO seems like a nice short version of IO but in reality it is limited to 10-bit ISA addresses and so should not really be used in most situations. Change all the references to use IO() directly instead. BUG=chromium:311294 BRANCH=none TEST=emerge-samus chromeos-coreboot-samus and check for iasl warnings using updated iasl compiler revision 20130117. Boot the imge and ensure that EC regions are still exported in /proc/ioports. Change-Id: I54de65892bed9e43dbba916990cf2b70c370843c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174810 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4910 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-21chromeec: Add event methods for EC requested throttleDuncan Laurie
Two new events possible from the EC for starting and stopping throttle. These are handled in a per-board method that is defined under the thermal zone. This is not quite where I wanted it but the scoping rules in ACPI don't let me have a defined external object in the same scope. Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63988 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4415 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-07-10ec: Reserve correct ioport regions for Chrome OS EC to useBill Richardson
The LPC-based ChromeOS EC uses several ioport regions to communicate with the AP. In order for the new unified userspace access method to work, we need them to be reserved by the BIOS. Before /proc/ioports shows: 0800-0803 0804-08ff We'd like just a single 256-byte region at 0x800, but ASL can't handle that. So this will work: 0800-087f 0880-08ff Change-Id: I3f8060bff32d3a49f1488b26830ae26b83dab79d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: http://review.coreboot.org/3746 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10chrome ec: Update EC header from EC repositoryDuncan Laurie
- Updated ec_commands.h is copied in directly from EC repo - Removed "old" interface and update resources for "new" interface - Updated temp sensor constants and added "not calibrated" - Update mainboards to remove check for EC_SWITCH_KEYBOARD_RECOVERY Change-Id: Ic93c1914f86b6f5bc224178270624ed92b5c1e15 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10ec: Remove hardcoded GPI offset in EC SCIDuncan Laurie
With LynxPoint-LP the SCI GPE is no longer a GPIO that is offset by 16. Remove the Add and fix up the link definition so it is still accurate. Change-Id: I091141183a09345b5ffe28365583e48019f9f5e5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3742 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-22Add support for Google ChromeECStefan Reinauer
Google ChromeEC is an EC with completely open source firmware. See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary for the EC firmware source code (aka more information about the ChromeEC) This patch adds support for the ChromeEC on coreboot's side. Great thanks to the ChromeEC team for this amazing work. It's another important milestone towards a free and open firmware stack on modern hardware. Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2481 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 01:58:33 +0000