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2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14AGESA binaryPI: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: I4571e8b560559b3d7afe429eca8caa1512e244a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-12drivers/i2c/generic: Ensure config is not NULL before accessing itFurquan Shaikh
This change checks to ensure that config is not NULL before it is accessed for the first time. Reported by: Coverity CID #1393312 Change-Id: Ic248c79783da9c2bfdf3b7f737e5963feff7558c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-11drivers/spi: Remove Kconfig prompt from SPI_FLASH_SMMNico Huber
Why would that be a user visible option? Drop the prompt and the `default n` and select it automatically when needed. I hope I caught all its users. TEST=Confirmed that systems with ELOG_GSMI or DEBUG_SMI compile and link. Change-Id: I44aeec530cc333f4ed4c8cfe67c7b5c9d8fb0049 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-11drivers/spi: Treat all stages commonly when adding driversNico Huber
Clean it up and add all flash chip drivers to postcar stage thereby. There seem to be SPI controllers that don't need the individual flash chip drivers. For those postcar support was added in b6b1b23 (console/flashconsole: Enable support for postcar). However for SPI controllers that need the individual drivers (i.e. those with CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y), linking of the postcar stage was broken. For all other stages, the set of compilation units stays the same. Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26871 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11drivers/spi: Remove DEBUG_SMI guardNico Huber
Let the linker take care of it. Change-Id: I67d2636ceb042f833c1b44888b98135d728940e0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-08arch/x86: Drop leftover ROMCC console supportKyösti Mälkki
Change-Id: I3e52569a34e1f7bfea8be9da91348c364ab705e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
Change-Id: Ia637d32ffaa5d280320955d34141eddc8b7df981 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22222 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06src/driver/i2c/{generic,hid,tpm,max}: Update device name based on devicetree.cbNaresh G Solanki
Name i2c device structure based on that in devicetree.cb Now log looks like: I2C: 01:0a (WCOM Touchscreen) I2C: 03:13 (Realtek RT5663) I2C: 03:39 (SSM4567 Right Speaker Amp) I2C: 03:3a (SSM4567 Left Speaker Amp) BUG=None BRANCH=None TEST=Build & boot Soraka Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04src/drivers: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia9ca055679c0332613afb2bb2ed86df165de3baf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04drivers/generic/ioapic/ioapic.c: Remove unneeded includeElyes HAOUAS
Change-Id: I670702f092e49bac8d7733d6fa77861e28e09093 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-01drivers/intel/wifi: Add PCI ID for Intel TP2 Wi-FiFurquan Shaikh
This change adds PCI ID for Intel TP2 Wi-Fi and adds that to pci_device_ids in Intel wifi driver. Change-Id: I51abf615fca6001d564e7cd672cc16f3a0fb8dd6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-31i210: Add additional PCI-ID to the i210 driverWerner Zeh
When the i210 MACPHY is operated in the SERDES Backplane mode (which depends on the programmed firmware image), its PCI-ID will be 0x1537. This does however not change the programming interface for the MAC address. Therefore add this new PCI-ID to the driver so that the MAC address can be programmed in this operation mode as well. Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/26683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-31cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDENico Huber
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-28drivers/i2c/max98373: update DT property namesSathyanarayana Nujella
Upstream Kernel side codec driver expect DT properties to have 'maxim' prefix. Update accordingly while filling SSDT entries. BUG=b:79362472 TEST=dump DT properties in kerenl side and cross checked TEST=Audio playback works with this change Change-Id: Iaa4b14492dbb5a0087242f1485493f3192336f60 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-25elog: Only log POST code from previous boot on non-S3 resumeDaniel Kurtz
It doesn't make sense to log post codes from a previous (failed) boot if we are resuming from S3, since the previous boot has to have been successful in order to enter S3 in the first place. While we are at it, use a helper function to combine conditionals and improve readability. BUG=none TEST=boot, suspend & resume grunt Change-Id: I4f3bb8526a0c8c0ea1efd924628b33c147543b88 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26528 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25elog: Only print TYPE_BOOT on S3-resume if CONFIG_ELOG_BOOT_COUNTDaniel Kurtz
Previously, we were unconditionally adding a TYPE_BOOT message to the ELOG on every boot (even S3 resume) if CONFIG_ELOG_BOOT_COUNT was disabled. Now that boot_count_read() returns 0 for the !CONFIG_ELOG_BOOT_COUNT case, the code becomes a bit simpler. BUG=b:79865267 TEST=firmware_EventLog Change-Id: I803fa4c3e03b6cc94751cf0ce34b78021ae2124e Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26527 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25drivers/intel/fsp2_0: Make use of xmalloc for FSP-S UPDSubrata Banik
Don't allocate FSP-S UPD over stack. This patch reduces stack usage for Cannonlake platform. TEST=On CNL platform stack usage reduces from ~3.6KiB to ~1KiB. Change-Id: I07ef0db6720d7e6865ac1641ce2661009332907c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26501 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22src: Remove non-ascii charactersMartin Roth
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-18drivers/usb/acpi: Add a driver for generating USB ACPIDuncan Laurie
Add a support for generating USB port descriptors for ACPI based on their definition by the board in devicetree.cb. This will generate a _UPC and _PLD for each port, using a generic _PLD by default. The _PLD can also be customized for more accurate descriptions if necessary. This sample devictree.cb shows a USB 2.0 type-A port behind a root hub connected to an xHCI controller: device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 on chip drivers/usb/acpi register "desc" = ""USB 2.0 Type-A"" register "type" = "UPC_TYPE_A" device usb 2.0 on end end end end end It will generate the following ACPI code in the SSDT: Scope (\_SB.PCI0.XHCI.RHUB.HS01) { Name (_DDN, "USB 2.0 Type-A") Name (_UPC, Package (0x04) { 0xFF, 0x00, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "RECTANGLE", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) } Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26173 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15ACPI: Set the correct number of arguments in ACPI methodsMartin Roth
These methods had unused arguments and could be corrected by setting the correct number in the method initializer. Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-15drivers/net: Check "ethernet_mac" when the device index is 1David Wu
It is a special case for the Fizz firmware branch, when the device index is 1, it will check "ethernet_mac" first and then "ethernet_mac0". For single NIC: config.device_index = "1", maps to "ethernet_mac" For multiple NICs: config.device_index = "1", maps to "ethernet_mac0" BUG=b:77836343 BRANCH=Fizz TEST=Add device index in device tree && Program the mac address to VPD in shell vpd -s ethernet_mac=<mac address> or vpd -s ethernet-mac[0-9]=<mac address> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: I67fd2e999c8f9d8782f294fcafa84b8da970a3a6 Signed-off-by: David Wu <david_wu@quantatw.com> Reviewed-on: https://review.coreboot.org/26051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-13drivers/pc80/tpm: get ioport from pnp recordsKevin Cody-Little
Had 0x2e hardcoded, which is often the SuperIO chip. Instead, pull the port from the PNP tree generated from devicetree.cb, where either 0x4e or 0x2e will be specified. Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-11drivers/intel/gma: honor vbt_size parameter to locate_vbt()Aaron Durbin
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve cooperation) the vbt_size parameter was not honored leading to the use of unitialized variables from the caller. Instead, keep track of if the vbt is already loaded by using the size returned from the load. If it's non-zero the vbt has been loaded. BUG=b:79562868 Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26236 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09drivers/intel/gma, soc/intel/common: improve cooperationPatrick Georgi
Instead of both featuring their own VBT loaders, use a single one. It's the compression-enabled one from soc/intel/common, but moved to drivers/intel/gma. The rationale (besides making all the Kconfig fluff easier) is that drivers/intel/gma is used in some capacity on all platforms that load a VBT, while soc/intel/common's VBT code is for use with FSP. BUG=b:79365806 TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected code paths. Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08drivers/aspeed/ast2050: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I31f53f5f0e3f1fd6bd9bdbb47ea67c12b3840850 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08drivers/xgi/z9s: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ia9c705d34b90ad44272a06790fbb1041029ef77d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26069 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04drivers/ricoh/rce822: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I6f6c4330ad88e013b24761a3aa1c29bc869da39d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/uart/oxpcie.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/drivers/lenovo/wacom.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Idb139d5cb2ac10f4051407137242ccee1a09b785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/intel/i210.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: If9c122efbb7dbab7d834372da3c1c70463be7a77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/intel/gma/opregion.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Idff2ec30f0b8c9a49f4369e231be92cbc8070dc0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/i2c/da7219: Add mclk-name propertyAkshu Agrawal
Non-dts based systems can pass mclk to da7219 driver by this property. BUG=b:74570989 TEST=Enabled clock in kernel driver using the property Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02drivers/generic/bayhub: Add driver for BayHub BH720Simon Glass
Add a driver which puts the device into power-saving mode. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: Idbfb114f3782c9386ce9b487c3abdb0afbc4a0d9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02src/drivers: Add reset/enable/stop_off_ms variables to ACPI devicesShelley Chen
Some touchscreens need to adhere to certain timings during the power off sequence as well as during the power on sequence. Adding reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to accommodate these devices. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-02intel/common: compress VBTPatrick Georgi
It's pretty well compressible which helps when space is tight. The code encodes the assumption that the VBT is 8kb or less. Haven't seen a larger one yet. BUG=b:77971803,b:78541692 TEST=build, see that vbt.bin is compressed, boot, check log that the reported VBT size is correct. Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-01drivers/intel/fsp2_0: Include MP services header for UDK2017 supported platformSubrata Banik
BRANCH=none BUG=b:74436746 TEST=Able to include EFI_MP_SERVICES_PPI without any error. Change-Id: I5add8e533dfd3f6d03abf7b2ca1a83f81f1c5920 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-29drvs/lenovo/wacom: Clean ACPI codePatrick Rudolph
Use acpigen method to return _STA instead of hardcoding unreadable bytecode. Change-Id: I290fb918675857e8ef798e3ab820bcfbdc6f5bdc Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-27drivers/usb: Add spaces around '=='Elyes HAOUAS
Change-Id: If72ce868cdd06183e5055deb94b9d0cf12ed8738 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25858 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27drivers/i2c/lm63: Remove unneeded headersElyes HAOUAS
Change-Id: Id13eef7f0fca0b929372490859aa4734ea7a9f23 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-27drivers/i2c/adm1026: Remove unneeded headersElyes HAOUAS
Change-Id: Iaed9c0882847511642d8eaab25e10d1ecf24bf90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-27drivers/i2c/adm1027: Remove unneeded headersElyes HAOUAS
Change-Id: I147b3a2c79cd5e6b0e5fa3d23221a6afda8ba8f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-27drivers/asmedia: Add ASPM blacklistNico Huber
To be selected by mainboard Kconfig if the board hosts an ASMedia chip that spuriously advertises ASPM features. Change-Id: I05f9789bc14db56d2ac085f4f14047d80c3aefb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25619 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27drivers/uart: Allow the 8250IO driver only on x86Jonathan Neuschäfer
The driver relies on I/O space access functions (inb, etc.), which are only available on x86. Rather than explicitly disallowing it on ARM, allow it only on x86. TEST=Configure for RISC-V, and see that "Serial port on SuperIO" is not available in the "Generic Drivers" menu anymore. Change-Id: Ib8e8c402264afeba6dc098683c5464af6edb3ba3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-04-26src: Fix a typo on "mtrr"Elyes HAOUAS
Change "mttrs" to mtrrs. Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26drivers/i2c/ck505: Remove unneeded headersElyes HAOUAS
Change-Id: Ic525c92e73097752a7c690186dc2034785cac678 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25821 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26drivers/uart: Add helper function to allow bit-bangingJulius Werner
In some cases it may be useful to be able to bitbang a UART, such as during early bring-up when a driver for the actual controller isn't available yet. On some platforms we may even want to use this permanently, such as on the SDM845 where the hardware UART controller needs to have firmware loaded and is thus unavailable for most of the bootblock. This patch adds some helper code that makes it easy to implement this on a platform, you just have to pass it a function to control the Tx pin state and it will do the rest. It relies on the mono_time API and is thus bound to microsecond timing granularity, but that seems to be barely good enough for 115200 baud if the bit times are calculated carefully. Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25812 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25drivers/uart: Add a driver for SiFive's UARTJonathan Neuschäfer
This UART is used in the SiFive FU540 SoC, and will probably be used in other SoCs in the future. Change-Id: I915edf39666b7a5f9550e3b7e743e97fe3cacfd3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23drivers/spi: reduce confusion in the APIAaron Durbin
Julius brought up confusion about the current spi api in [1]. In order alleviate the confusion stemming from supporting x86 spi flash controllers: - Remove spi_xfer_two_vectors() which was fusing transactions to accomodate the limitations of the spi controllers themselves. - Add spi_flash_vector_helper() for the x86 spi flash controllers to utilize in validating driver/controller current assumptions. - Remove the xfer() callback in the x86 spi flash drivers which will trigger an error as these controllers can't support the api. [1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-16drivers/pc80/tpm: Add some optional delay to tis_readresponse()Bill XIE
Certain TPMs (observed on Infineon SLB9635 installed on revolve 810 g1) seem to need some delay between tis_wait_valid() and tis_has_valid_data(), or tis_has_valid_data() may invalidly return 0, ending the loop immaturely with some bytes left unread, and fail to pass the check below, causing the current command not finalized by tis_command_ready(), and blocking any later tis_wait_ready(). This time the added delay is controlled by a Kconfig option TPM_RDRESP_NEED_DELAY. Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/25322 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13drivers/uart/pl011.c Add read supportMarcello Sylvester Bauer
Implement uart_rx_byte Change-Id: I5a33b3cd4b333fb244bc55747014a301021e25e0 Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com> Reviewed-on: https://review.coreboot.org/25623 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-133rdparty/libgfxinit: Update submodule pointerNico Huber
Update libgfxinit to current master. Changes include: * a fix to decode the size stolen memory correctly on pre-SandyBridge hardware, * a PCI id based generation check, obsoleting the old check based on PCH audio ids, * some minor improvements around rarely used DDI ports (D and E), and * added support for tiled and rotated framebuffers on Skylake+ hardware (less interesting for coreboot, I guess?). TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6 (Skylake) both with text and linear framebuffers and observed FILO's prompt showing up. Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25453 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11Correct "MTTR" to "MTRR"Jonathan Neuschäfer
The term MTRR has been misspelled in a few places. Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-11drivers/aspeed/Kconfig: Select HAVE_VGA_TEXT_FRAMEBUFFERDaniel Gröber
This allows VGA output in SeaBIOS to be enabled using the SEABIOS_VGA_COREBOOT Kconfig option. Currently, it’s impossible to select the VGA text frame buffer in the Kconfig menu. I'm not sure why this wasn't enabled in the first place, but SeaVGABIOS seems to work just fine with this patch. Tested on KCMA-D8. Change-Id: Ic924a12fbe89940b5f26d211eb8de6cab0be767a Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/25554 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-11drivers/intel/wifi: Add support for Harrison Peak (HrP)Subrata Banik
Move all Intel WIFI PCI ids into device/pci_ids.h file. TEST=HrP module is getting detected during PCI enumeration. Change-Id: Ia2d15f3f4a68887521ddbb1b99daf9d98cfa5c8b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09ioapic: extend definition name to avoid collisionMarc Jones
Change EN/DISABLED to INT_EN/DISABLED to avoid collision with other EN/DISABLE definition. Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25540 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06drivers/intel/gma: Depend less on default fb valuesNico Huber
Instead of hard-coding a lot of default values of the framebuffer config, we use the values provided by Display_Probing.Scan_Ports() and only overwrite what is necessary. This way we are more independent from changes inside libgfxinit. Change-Id: I121bbd926532c27321446282aa334cc45cdbeef1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-06drivers/intel/gma: Amend stride calculation of linear fbNico Huber
Aligning the stride up to a multiple of 64 pixels was flawed: We want to actually align up to one cacheline (64 bytes) as that's the mini- mum what the hardware supports. Change-Id: I3f824ffd7d12835935e4e4bde29fe82dc3e16f9d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-05src/drivers/pl011: Add verstage supportPatrick Rudolph
Build pl011 to support building vboot on arm platforms. Change-Id: I1ddc372d558b380065ff944fccb0d84eb37d4213 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-04-03spi: Add helper functions for bit-bangingJulius Werner
Sometimes when bringing up a new board it can take a while until you have all the peripheral drivers ready. For those cases it is nice to be able to bitbang certain protocols so that you can already get further in the boot flow while those drivers are still being worked on. We already have this support for I2C, but it would be nice to have something for SPI as well, since without SPI you're not going to boot very far. This patch adds a couple of helper functions that platforms can use to implement bit-banging SPI with minimal effort. It also adds a proof of concept implementation using the RK3399. Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-01drivers/spi/flashconsole.c: Fix broken headerArthur Heymans
Change-Id: I61d28791fa75a32591448fc2c40186acfddca86d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25413 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-26drivers/intel/fsp: Fix TPM initialization when vboot is disabledYouness Alaoui
A change introduced by commit fe4983e5 [1] in order to prevent re-initialization of the TPM if already set up in verstage had the wrong logic in the if statement, causing the TPM to never be initialized if vboot is disabled. The RESUME_PATH_SAME_AS_BOOT config is enabled by default for ARCH_X86, resulting in the if statement to always evaluate to false. Remove that condition from the if statement to allow it to function as intended. This patch also enables TPM initialization for FSP 2.0 with the same conditions. [1] intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage https://review.coreboot.org/#/c/coreboot/+/14106/ Change-Id: Ic43d1aa31a296386c7eab6d997f9b701e9ea0fe5 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23680 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21drivers/i2c/designware: Fix indentationMaulik V Vaghela
Remove extra tab before printk statement. Change-Id: Id82239f74ac030f25000a08764637f6d1b52b87b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/25295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-19drivers/intel/wifi: Add Jefferson Peak Device IDLijian Zhao
The following PCI device ID can be included for jefferson peak wifi devices driver support, and they are: 9df0 for jefferson peak on Cannonlake-LP w/CNVi A370 for jefferson peak on Cannonlake-H w/CNVi 31dc for jefferson peak on Geminilake w/CNVi BUG=None TEST=None Change-Id: I48886cea5578a302f6ef033cb35df4a38bd64ea8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-14drivers/intel/gma: fix opregion SCI register for Atom platformsMatt DeVillier
Most Intel platforms use separate registers for software-based SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single combined register (0xe0) for both. Adjust opregion implementation to use the correct register for Atom-based platforms. Test: Boot Windows on Atom-based ChromeOS device with Tianocore payload and non-VBIOS graphics init; observe Intel display driver loaded correctly and internal display not blank. (requires additional change for Atom platforms to select CONFIG_INTEL_GMA_SWSMISCI) Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-28drivers/intel/fsp2_0: Fix build error while DISPLAY_HOBS is selectedSubrata Banik
This patch fixes brokenness issues in coreboot with CONFIG_DISPLAY_HOBs config selection due to recent UDK2017 package changes. TEST=Build and boot UDK2017 platforms with DISPLAY_HOBS select. Change-Id: I5c779c86870c62253d64c6af456bf017553e269c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-21driver/uart: Introduce a way for mainboard to override the baudrateJulien Viard de Galbert
The rationale is to allow the mainboard to override the default baudrate for instance by sampling GPIOs at boot. A new configuration option is available for mainboards to select this behaviour. It will then have to define the function get_uart_baudrate to return the computed baudrate. Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-20driver/spi: Warn when probed SF size differs from CONFIG_ROM_SIZEArthur Heymans
Some assumptions are made with respect to CONFIG_ROM_SIZE being the actual size of the boot medium, e.g. when automatically creating an fmap with and RW_MRC_CACHE region. With this patch the user is warned when this is detected. Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-15drivers/generic/adau7002/adau7002.c: Fix null pointer dereferenceRichard Spiegel
Procedures acpi_device_scope() and acpi_device_name() can under certain conditions return NULL. Check the return before using them. This fixes CID 1385944 BUG=b:73331544 TEST=Build kahlee. Change-Id: Ifcdf905100d22a1d828394f8685641eb432bb836 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23760 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15drivers/i2c: Add chip driver for I/O expander PCA9538Werner Zeh
The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C bus. Add a chip driver to support this chip. Beside the pure chip driver two interface functions are provided to read the state of the pins and write output values to the pins. As the slave address of this chip is hardware configurable the function pca9538_get_dev() is used to get the right slave address. This function needs to be implemented in mainboard code if one needs to use the interface functions to read and write I/O state. Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/23748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14drivers/i2c/designware: Remove spurious word ("familuar")Jonathan Neuschäfer
Fixes: b8dc63bdfe ("ic2/designware: Move Intel i2c logic to shared driver") Change-Id: Ic521a2d60b403b322ae583bb2c26da6019bf0ab0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23714 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14drivers/adau7002: Fix include fileDaniel Kurtz
Add missing license and include guard and remove unneeded include. BUG=b:72121803 TEST=compiles Change-Id: Ic359ed262086596a98131669f8eecd531857187a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23721 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-13drivers/uart/pl011: Improve PL011 driverDavid Hendricks
This adds a struct for registers along with some bits from ATF to the generic PL011 driver. It also adds a naive implementation of uart_tx_flush() which was previously stubbed out. Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/23031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-10drivers/adau7002: Add driver for handling ADAU7002Daniel Kurtz
The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from Analog Devices. On some boards they are a used to convert a PDM audio data stream from a DMIC to an I2S signal. Add a driver for populating ACPI table entries for this part. BUG=b:72121803 TEST=With grunt audio kernel patches, "aplay -l" shows playback devices: **** List of PLAYBACK Hardware Devices **** card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 [] Subdevices: 1/1 Subdevice #0: subdevice #0 Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Martin Roth <martinroth@google.com>
2018-02-10drivers/i2c/da7219: Allow GPIO based interruptDaniel Kurtz
Allow specifying the DA7219 interrupt pin as either an Interrupt or GpioInt. BUG=b:72121803 TEST=(with whole patch series) Grunt Kernel discovers DA7219 on i2c0 Change-Id: I2d26731bf4c0ad590dad2c5d26c252371f415f9a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-02-09drivers/intel/fsp2_0: Remove fsp_find_smbios_memory_info() from FSP2.0 driverSubrata Banik
As per FSP 2.0 specification and FSP SOC integration guide, its not expected that SMBIOS Memory Information GUID will be same for all platform. Hence fsp_find_smbios_memory_info() function inside common/driver code is not generic one. Removing this function and making use of fsp_find_extension_hob_by_guid() to find SMBIOS Memory Info GUID from platform code as needed. Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-02drivers/i2c/designware: conform to controller restrictionsAaron Durbin
The designware i2c controller indicates that the slave address shouldn't be programmed while the controller is enabled. Therefore, switch the ordering of the slave target address and the enable. Additionally, ensure the controller is disabled prior to the start of the slave programming sequence. Lastly, chunk up the i2c_msg segments at differing slave address boundaries. That allows for simpler programming for the controller by only doing one slave address transaction chunk at a time. BUG=b:70232394,b:69250772 Change-Id: Iebc08e2db847cb182fad98e0ff3d799b9a64aca7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01drivers/i2c/designware: Unset IC_ENABLE when setting target addressChris Ching
To set address on AMD, IC_ENABLE == 0. BUG=b:69416132 BRANCH=none TEST=Test communication with i2c TPM on grunt and coral Change-Id: I7faee8e11439deceab946cc82d30d274b529b90d Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/23293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-31drivers/intel/fsp2_0: Add support to display FSP version info HobSubrata Banik
This patch locates FSP FVI hob in order to extract all firmware ingredient version information. So far this feature is only supported for CannonLake SoC onwards. Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31drivers/intel/fsp2_0: Make use of Resource Type macro from EDK codeSubrata Banik
Users are getting build error due to duplicate macro definitions of same resource type between fsp driver code and UEFI headers. Hence this patch ensures to refer a single source location for macro definitions to avoid compilation error. Change-Id: If022eb29550a9310b095bff6130b02fb0a25ef7a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driverSubrata Banik
Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31drivers/gpio_keys: Add driver for handling gpio-keysFurquan Shaikh
This change adds the required device node in SSDT for defining gpio-keys/gpio-keys-polled. Currently, it supports only one gpio-key per device node. BUG=b:71329519 TEST=Verified by adding details to devicetree that device node is added to SSDT: Device (PENH) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionInputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x002B } }) Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "compatible", "gpio-keys" } }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { Package (0x02) { "button-0", "EJCT" } } }) Name (EJCT, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x04) { Package (0x02) { "linux,code", 0x0F }, Package (0x02) { "linux,input-type", 0x05 }, Package (0x02) { "label", "pen_eject" }, Package (0x02) { "gpios", Package (0x04) { \_SB.PCI0.I2C0.PENH, Zero, Zero, One } } } }) } Change-Id: I6f11397b17d9de1c87d56f6a61669ef4052ec27b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23236 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30drivers/i2c/tpm: Add irq_gpio support to tpm.Justin TerAvest
Grunt (a amd-stoneyridge based platform) uses a GPIO to interface with the tpm. This change allows devicetree entries to use a irq_gpio entry to describe the interface with the TPM. BUG=b:72655090 Change-Id: I08289891408d7176f68eb9c67f7a417a2448c2de Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30drivers/spi: support cmd opcode deduction for spi_crop_chunk()Aaron Durbin
spi_crop_chunk() currently supports deducting the command length when determining maximum payload size in a transaction. Add support for deducting just the opcode part of the command by replacing deduct_cmd_len field to generic flags field. The two enums supported drive the logic within spi_crop_chunk(): SPI_CNTRLR_DEDUCT_CMD_LEN SPI_CNTRLR_DEDUCT_OPCODE_LEN All existing users of deduct_cmd_len were converted to using the flags field. BUG=b:65485690 Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23491 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-29intel: Prepare registers so Windows drivers are happierPatrick Georgi
Change-Id: I12ebed30de4df9814ccb62341c7715fc62c7f5b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/23431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-26drivers/spi/spi_flash: honor spi controller fifo size for readsAaron Durbin
The spi_flash_cmd_read_fast() and spi_flash_cmd_read_slow() were just passing full size buffers to the spi controller ops. However, the code wasn't honoring what the spi controller can actually perform. This would cause failures to read on controllers when large requests were sent in. Fix this by introducing a spi_flash_cmd_read_array_wrapped() function that calls spi_flash_cmd_read_array() in a loop once the maximum transfer size is calculated based on the spi controller's settings. BUG=b:65485690 Change-Id: I442d6e77a93fda411cb289b606189e490a4e464e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-25drivers/i2c/designware: reduce API complication for bus configAaron Durbin
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement that callback for obtaining the bus config. However, we're currently forcing another parameter of struct device so one can do the lookup. This works for Intel-based systems since the struct device was needed to program the BAR, etc. However, from an API standpoint, it just complicates matters by needing to obtain the struct device. The SoC already has knowlege of its own devices so it can get the config itself by bus number. Therefore, remove that contraint from the API. BUG=b:70232394 Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23420 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24drives/i2c/designware: incorporate device_operations supportAaron Durbin
In ramstage the device_operations are needed for the i2c designware host controller. Move the intel/common/block/i2c implementation into the generic driver so other platforms can take advantage of it. BUG=b:72121803 Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-24drivers/i2c/designware: namespace soc functionsAaron Durbin
Rename the following functions to ensure it's clear that the designware i2c host controller driver is the one that these functions are associated with: i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg() i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base() i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus() i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn() BUG=b:72121803 Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23371 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24device/i2c_bus: allow i2c_bus and i2c_simple to coexistAaron Durbin
If one wants to implement both i2c_bus.h and i2c_simple.h APIs the compilation unit needs to be guarded or coordinated carefully with different compilation units. Instead, name the i2c_bus functions with _dev such that it indicates that they operate on struct device. One other change to allow i2c_bus.h to be built in non-ramstage environments is to ensure DEVTREE_CONST is used for the dev field in struct bus. BUG=b:72121803 Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-23AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki
With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23drivers/i2c/max98373: Add driver for generating device in SSDTN, Harshapriya
Add a device driver to generate the device and required properties into the SSDT for max98373. TEST=verified SSDT contained relevant params BUG=None Change-Id: Id45f74e52855f4b19276e1d3d673d5448207ef4b Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: N, Harshapriya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/22673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22drivers/net: Add device index for multiple NIC cardsGaggery Tsai
This patch adds a member device_index to r8168 chip information which allows driver to identify which NIC card requests MAC address. In this implementation, only 10 NIC cards are supported, the device index is in the range of 0 to 10. Regarding to MAC address mapping, when there is only one NIC on DUT, it is treated as a special case mapping to "ethernet_mac" in VPD for backward compatibility. When there are multiple NICs on DUT, they are mapping to "ethernet_macN" where N is [0-9]. Device tree configuration: For single NIC: .device_index = "0", maps to "ethernet_mac" For multiple NICs: .device_index = "[1-10]", maps to "ethernet_mac[device_index - 1]" BUG=b:69950854 BRANCH=None TEST=Added device_index = [0-10] under /drivers/net in device tree && Programmed the mac address to VPD in shell vpd -s ethernet_mac=<mac address> or vpd -s ethernet-mac[0-9]=<mac address> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/22984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 03:23:10 +0000