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2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-14driver/i2c/max98390: add dsm_param_nameWisley Chen
Maxim driver look for "maxim,dsm_param_name" to load dsm parameter file. dsm param file name consist of {dsm_param_file_name} filled in devicetree, {MAINBOARD_VENDOR} and {MAINBOARD_PART_NUMBER}. => {dsm_param_file_name}_{MAINBOARD_VENDOR}_{MAINBOARD_PART_NUMBER}.bin BUG=b:197076844 TEST=build, and check ssdt Change-Id: I006572d6a6ea55298374c688dfd9d877835da82d Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13SMBIOS: Allow skipping default SMBIOS generationAngel Pons
The call to the `get_smbios_data` device operation is followed by calls to unconditional default functions, which lacks flexibility. Instead, have devices that implement `get_smbios_data` call these default functions as needed. Most `get_smbios_data` implementations are in mainboard code, and are bound to the root device. The default functions only operate with PCI devices because of the `dev->path.type != DEVICE_PATH_PCI` checks, so calling these functions for non-PCI devices is unnecessary. QEMU also implements `get_smbios_data` but binds it to the domain device, which isn't PCI either. Change-Id: Iefbf072b1203d04a98c9d26a30f22cfebe769eb4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13spi-generic: Print an error when trying to use a non-existent busJulius Werner
...because I just spent hours chasing a refactoring bug that would have been way more obvious with a little more error transparency in here. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3354ff0370ae79f05e5c37d292ac16d446898606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-13drivers/analogix/anx7625: prevent video clock jitter on IVO panelsXin Ji
The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz), anx7625 defines K ratio for matching MIPI input video clock and DP output video clock. A bigger k value can match a bigger video data variation. IVO panel has smaller variation than DP CTS spec, so decrease k value to 0x3b. BUG=b:194659777 BRANCH=none TEST=Display is normal on Asurada Change-Id: If3a09811999babda45e9a9a559dd447920109204 Signed-off-by: Xin Ji <xji@analogixsemi.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-11mipi: Make panel init callback work directly on DSI transaction typesJulius Werner
Our MIPI panel initialization framework differentiates between DCS and GENERIC commands, but the exact interpretation of those terms is left to the platform drivers. In practice, the MIPI DSI transaction codes for these are standardized and platforms always need to do the same operation of combining the command length and transfer type into a correct DSI protocol code. This patch factors out the various platform-specific DSI protocol definitions into a single global one and moves the transaction type calculation into the common panel framework. The Qualcomm SC7180 implementation which previously only supported DCS commands is enhanced to (hopefully? untested for now...) also support GENERIC commands. While we're rewriting that whole section also fix some other issues about how exactly long and short commands need to be passed to that hardware which we identified in the meantime. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-10elog: move MAX_EVENT_SIZE to commonlib/bsd/includeRicardo Quesada
Moves MAX_EVENT_SIZE to commonlib/bsd/include, and renames it ELOG_MAX_EVENT_SIZE to give it an "scoped" name. The moving is needed because this defined will be used from util/cbfstool (see next CL in the chain). BUG=b:172210863 TEST=compiles Ok Change-Id: I86b06d257dda5b325a8478a044045b2a63fb1a84 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-09wifi: Update deny list entry size to uint16_tSugnan Prabhu S
As per the connectivity document deny list entry size should be uint16 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf Fixes: cc50770cd0("wifi: Add support for wifi time average SAR config") Change-Id: I045c21350cf4c2266df108eede6350d090322ba0 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09drivers/intel/fsp2_0: Retype loop variable from int to uint32_tAngel Pons
Retype loop variable `i` to `uint32_t` for consistency with the types of the `number_of_phases` and `phase_index` struct fields and the parameter of the `platform_fsp_multi_phase_init_cb()` function. Change-Id: I82916f33c2dc5dab6a31111c9acba2a18a5cfb0b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57491 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selectedFelix Held
Platforms that rely on the FSP for parts of the hardware initialization likely won't boot successfully when no FSP binaries are added during the build, so print a warning at the end of the build in this case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Suggested-by: Martin Roth <martinroth@google.com> Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05drivers/intel/dptf: Add new thermal control mechanism for pch deviceSumeet Pawnikar
Add new thermal control mechanism for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05drivers/intel/fsp/Makefile: error out when FSP files aren't specifiedFelix Held
Error out when the FSP binaries that are supposed to be added aren't specified. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-03drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS fileFelix Held
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends on both, so also check if both are selected in the Makefile where it tries to add the FSP-T to the CBFS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-02wifi: Add support for DSM methods for intel wifi cardSugnan Prabhu S
Add support for DSM methods as per the connectivity document 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:191720858 TEST=Check the generated SSDT tables for DSM methods Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for wifi time average SAR configSugnan Prabhu S
Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the WTAS related configuration values and verified that the SSDT has the WTAS ACPI table. Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for per-platform antenna gainSugnan Prabhu S
Add support for the PPAG ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the PPAG related configuration values and verified that the SSDT has the PPAG ACPI table. Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for new revisions of SAR table entriesSugnan Prabhu S
Existing SAR infrastructure supports only revision 0 of the SAR tables. This patch modifies it to extend support for intel wifi 6 and wifi 6e configurations as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf The SAR table and WGDS configuration block sizes were static in the legacy SAR file format. Following is the format of the new binary file. +------------------------------------------------------------+ | Field | Size | Description | +------------------------------------------------------------+ | Marker | 4 bytes | "$SAR" | +------------------------------------------------------------+ | Version | 1 byte | Current version = 1 | +------------------------------------------------------------+ | SAR table | 2 bytes | Offset of SAR table from start of | | offset | | the header | +------------------------------------------------------------+ | WGDS | 2 bytes | Offset of WGDS table from start of | | offset | | the header | +------------------------------------------------------------+ | Data | n bytes | Data for the different tables | +------------------------------------------------------------+ This change supports both the legacy and the new format of SAR file BUG=b:193665559 TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different binaries generated by setting different versions in the config.star Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02drivers/mipi: Make orientation a property of the mainboard, not panelJulius Werner
It doesn't make sense to store the orientation field directly in the panel information structure, which is supposed to be reuseable between different boards. The thing that determines orientation is how that panel is built into the board in question, which only the board itself can know. The same portrait panel could be rotated left to be used as landscape in one board and rotated right to be used as landscape in another. This patch moves the orientation field out of the panel structure back into the mainboards to reflect this. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01drivers/intel/fsp1_1/romstage.c: Remove MCU updateArthur Heymans
On Braswell this is done in the bootblock before C code is executed. Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-08-26elog: Define constant for RW region nameRicardo Quesada
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the hardcoded "RW_ELOG" value. This constant will be used also by elogtool (see CL in the commit chain). BUG=b:172210863 Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56986 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26elog: move functionality to commonlib/bsdRicardo Quesada
This commit moves some drivers/elog/ functionality to commonlib/bsd since they will be called from util/cbfstool/. In particular: * elog_fill_timestamp(), elog_update_checksum(), elog_checksum_event() were moved to commonlib/bsd/elog * elog_fill_timestamp() receives the time parameters and updates the event based on the "time" arguments. The original elog_*() functions were written by Duncan Laurie (see CB:1311) and he gave permission to re-license the code to BSD. BUG=b:172210863 Change-Id: I67d5ad6e7c4d486b3d4ebb25be77998173cee5a9 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26drivers/intel/fsp2_0: rename soc_validate_fsp_versionFelix Held
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it can not only be used to check the version info in the FSP-M binary's header, but also to check every other field in the binary's header. This is a preparation for a follow-up patch that implements this function to check the FSP-M binary's size. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26device/mipi: Move to drivers/mipiJulius Werner
Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-23include/bcd: move bcd code to commonlib/bsd/includeRicardo Quesada
Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/ Also, the license is changed from GPL to BSD. This is because it is needed from "utils" (see CL in the chain). For reference bin2bcd() & bcd2bin() are very simple functions. There are already BSD implementations, like these ones (just to name a few): https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67 http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c BUG=b:172210863 TEST=make (everything compiled Ok). Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/common: Add TGL-H PCI IDsJeremy Soller
Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-12drivers/generic/alc1015: Add HID to support alc1019Eric Lai
ALC1019 will use the ACPI compatible and share the same driver with ALC1015. Add HID to support more compatible ICs. BUG=b:195891240 TEST=ALC1019P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09drivers/uart/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most UARTs that do have wake capabilities support wake from D3hot rather than D3cold. BUG=b:187228954 TEST=compile Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/spi/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most SPI peripherals that do have wake capabilities support wake from D3hot rather than D3cold. This also allows coreboot to expose a power resource to perform power sequencing for a SPI peripheral that is intended to retain power in S3/S0ix. If support for a device with d3cold wake support is needed, it could be added in later as an option. BUG=b:187228954 TEST=compile Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/i2c/da7219: Update _S0W to D3hotTim Wawrzynczak
The DA7219 does not support wake from D3cold, therefore update the return value of _S0W from D3cold to D3hot. BUG=b:187228954 TEST=compile Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-04Move elog_internal.h to commonlib/bsd/includeRicardo Quesada
Move elog_internal.h to commonlib/bsd/include/bsd/. And rename it from elog_internal.h to elog.h. Since this file will be included from util/ it also converts the "uNN" types into "uintNN_t" types. The two defines that are not used by util/ are moved to drivers/elog/elog.c, the only file that includes them. Move also the function elog_verify_header() from drivers/elog/, to commonlib/bsd/elog.c since this function will be called from util/ as well. The rationale behind moving elog's defines & structs to commonlib/bsd/include is to make them available to util/ tools and/or payloads (should it be needed in the future). The files that are being relicensed to BSD were coded by Duncan Laurie, and he is Ok with the relicense. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-24src/drivers/intel/fsp2_0: allow larger FSP 2.0 headerNikolai Vyssotski
This is in preparation for migrating EDK2 to more recent version(s). In EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0 header (FspMultiPhaseSiInitEntryOffset). This increases the length of the header from 72 to 76. Instead of checking for exact length check reported header length against known minimum length for a given FSP version. BUG=b:180186886 TEST=build/boot with both header flavors Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23drivers/intel/i210: Set PCI bus master bit only if allowedWerner Zeh
Set the bus master bit only if the global Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE is enabled. For now the bus master bit is needed for i210 because of some old OS drivers that do not set it and won't work properly without it. Change-Id: I6f727e7f513f4320740fbf49e741cea86edb3247 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-23drivers/pc80/rtc: Make use of alt-century byte configurableNico Huber
This legacy alt-century byte sits amidst CMOS and conflicts many option tables. It usually has no meaning to the hardware and needs to be main- tained manually. Let's disable its usage by default if the CMOS option table is enabled. Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-22drivers/spi: Increase sector number to 14 for Winbond W25Q512NW-IMShaik Sajida Bhanu
Update proper number of sectors info for winbond W25Q512NW-IM chip BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I12a22321bb9180e32cd47faa6ac3960ba5b2dfb8 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56038 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17drivers/intel/gma: Support IGD Opregion 2.1Meera Ravindranath
List of changes: 1. Define new configs for Opregion versions. 2. Assign RVDA to relative address of the Opregion buffer in case of opregion 2.1+. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-15drivers: spi_flash: Add Fast Read Dual I/O supportJulius Werner
The Fast Read Dual Output and Fast Read Dual I/O commands are practically identical, the only difference being how the read address is transferred (saving a whooping 2 bytes which is totally irrelevant for the amounts of data coreboot tends to read). We originally implemented Fast Read Dual Output since it's the older command and some older Winbond chips only supported that one... but it seems that some older Macronix parts for whatever reason chose to only support Fast Read Dual I/O instead. So in order to make this work for as many parts as possible, I guess we'll have to implement both. (Also, the Macronix device ID situation is utter madness with different chips with different capabilities often having the same ID, so we basically have to make a best-effort guess to strike a trade-off between fast speeds and best chance at supporting all chips. If this turns out to be a problem later, we may have to add Kconfig overrides for this or resort to SFDP parsing, although that would defeat the whole point of trying to be fast.) BUG=b:193486682 TEST=Booted CoachZ (with Dual I/O) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-15drivers/intel/gma: Restructure Opregion version info codeMeera Ravindranath
Define a structure for opregion version information to align with spec/kernel. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-14drivers/usb/acpi: Avoid dereferencing maybe-NULL pointerAngel Pons
Do not dereference a pointer before checking whether it is NULL. Change-Id: Icbe9ae99d91fd587d8e56cf3a0dcb59834ee6d07 Found-by: Coverity CID 1458232 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56266 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14drivers/usb/acpi: Replace unneeded `memcpy` useAngel Pons
A regular assignment works just as well and also allows type-checking. It also avoids a common mistake where `sizeof` is applied to a pointer to obtain the size of the data it points to, without dereferencing it. Found-by: Coverity CID 1458231 Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56265 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14src: Use initial_lapicid() instead of open coding itArthur Heymans
Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before. Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"Felix Held
This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was originally introduced as a workaround for the bug that the Linux kernel doesn't know what to do with type 16 memory region in the e820 table where CBMEM resides and disallowed accessing it. After depthcharge was patched to mark the type 16 region as a normal reserved region, the Linux kernel now can access the BERT region and print BERT errors. When SeaBIOS was used as payload it already marked the memory region correctly, so it already worked in that case. After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the usage of the BERT memory region reserved by the FSP driver by the AMD Picasso and Cezanne SoCs and made them use CBMEM for the BERT region, no other SoC code uses this functionality. The Intel Alderlake and Tigerlake SoCs put the BERT region in CBMEM and never used this reserved memory region and the change for the Intel server CPU to use this was abandoned and never landed in upstream coreboot. AMD Stoneyridge is the only other SoC/chipset that selects ACPI_BERT, but since it doesn't select or use the FSP driver, it also won't be affected by this change. TEST=Behavior of the BERT code doesn't change on Mandolin Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12drivers/intel/usb4/retimer: remove redundant structure member group(PLD)Maulik V Vaghela
Currently, we get PLD information from USB port structure itself, so devicetree does not need to fill PLD structure anymore. Thus remove obsolete variable. Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/intel/usb4/retimer: Update code to assign correct port numberMaulik V Vaghela
Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Update the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. Get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/usb/acpi: Create function to get PLD informationMaulik V Vaghela
Create a separate function to get PLD information from USB device. This is helpful in retimer driver where we can attach same USB port information to retimer instance and we can avoid duplication of information. BUG=None BRANCH=None TEST=Check if code compiles and function returns correct value Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08IMOK: Add IMOK method support for DPTFSumeet Pawnikar
Add IMOK method support for DPTF BRANCH=None BUG=b:187797417 TEST=Built and tested on dedede board Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-02drivers/intel/fsp2: Change FSPS returned message to INFORaul E Rangel
This message is not an error, but just informational. BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-01drivers/intel/gma: Move extended VBT just below opregionMaulik V Vaghela
Currently the flow for opregion init is as below: 1. Allocate memory for opregion first (cbmem_add(opregion)) 2. Check if VBT size > 6 KiB (this requires extended VBT support) 3. In case of extended VBT requirement, we allocate another chunk of memory which is equal to size of VBT (cbmem_add(extended_vbt)) 4. Pass physical address pointer to OS via RVDA We can optimize the above flow to allocate single chunk of memory by checking VBT size in earlier step. The new optimized flow for opregion init is as below: 1. Check if VBT size > 6 KiB (this requires extended VBT support) 2. In case of extended VBT requirement, total memory to be allocated is calculated as sizeof(opregion) + sizeof (extended_vbt) In case where VBT size is < 6 KiB, total memory requirement would be equal to sizeof(opregion) 3. Based on above calculation, allocate single chunk of memory based on total size. This will also be helpful for the case of virtualization where guest users don't have access to physical address and when it needs relative address of VBT compared to absolute address. In case of opregion 2.1 spec, we need to pass relative address of VBT from opregion base in RVDA. This optimization will help in meeting this requirement since relative address of extended VBT is easy to get. This change will ensure that it meets opregion specification requirement and will be compatible with future versions as well. BUG=b:190019970 BRANCH=None TEST=check the address of extended VBT region and address is coming correctly. Change-Id: Ic0e255df63145409096b0b9312c6c51c05f49931 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01drivers/intel/dptf: Add OEM variables supportSumeet R Pawnikar
This adds OEM variables feature under DPTF as per BWG doc #541817. Using this, platform vendors can expose an array of OEM-specific values as OEM variables to be used in determining DPTF policy. These are obtained via the ODVP method, and then simply exposed under sysfs. In addition, these gets updated when a notification is received or when the DPTF policy is changed by userspace. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-01SMBIOS: Drop now-unnecessary unionsAngel Pons
Now that the refactoring is complete, the unions for the table header are no longer needed. Therefore, drop them. Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_full_table_len` functionAngel Pons
Introduce the `smbios_full_table_len` function to consolidate table length calculation. The case where the length of a table equals the length of the structure happens when a table has no strings. Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01SMBIOS: Introduce `smbios_carve_table` functionAngel Pons
Factor out some boilerplate code into a helper `smbios_carve_table` function, which zeroes out the table memory and fills in the header fields common to all tables. Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01SMBIOS: Introduce struct for SMBIOS table headerAngel Pons
All SMBIOS `type X` tables start with the same 4-byte header. Add a struct definition for it, and use it where applicable. The union is temporary and allows doing the necessary changes in smaller commits. Change-Id: Ibd9a80010f83fd7ebefc014b981d430f5723808c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Avoid `sizeof` on struct typeAngel Pons
Where applicable, use the size of the associated variable. Change-Id: Ibbac2a82893232a6f87182a6a965b84a599d633e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01drivers/mrc_cache: Avoid `sizeof` on struct typeAngel Pons
Where applicable, use the size of the associated variable. Change-Id: Icf4f1c8fe9f54c44b041a65eb46d6ec9f9fd6367 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-21drivers/intel/mipi_camera: Change type for gpio_num to uint16_tVarshit B Pandya
gpio_num is used to indicate the GPIO which is taken from gpio_soc_defs.h file. Support for dynamic generation of ASL file for Camera was added for JSL when there were less than 256 GPIOs. ADL now has more GPIOs and therefore uint8_t is not enough any more Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I0a5fdb612c8cf689d356af8591b9ad101360c25d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55538 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18intel/fsp2_0: Add FSP_ARRAY_LOAD macroLean Sheng Tan
Add FSP_ARRAY_LOAD macro for checking and loading array type configs into array type UPDs to increase readability. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I307340a2bfc0a54f2ab7241af2f24dfbf8bb111d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55559 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18drivers/intel/gma/opregion.c: Re-add lost log messageAngel Pons
Commit 926949d64c1d8ef49dcc6774dd8535a2cb1fd423 (drivers/intel/gma: Restructure IGD opregion init code) accidentally dropped this print statement. As it can be useful for debugging purposes, add it back. Change-Id: Iebd9e02bccc77538c0eed1e549294408586322f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55567 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18drivers/intel/mipi_camera: Remove unnecessary __packed attributeSugnan Prabhu S
This patch removes unnecessary __packed attribute from the structure defined in chip.h BUG=None TEST=Tested WFC camera on Brya Change-Id: I1174606cd22cd353f01d865d0c25bb6f8f8de055 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55566 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16arch/x86/ioapic: Drop irq_on_fsb as a configurable itemKyösti Mälkki
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11drivers/intel/gma: Restructure IGD opregion init codeMAULIK V VAGHELA
Restructuring opregion VBT related code to make it more generalize for future revision of opregion spec. Moved logic to locate VBT from different region (CBMEM, PCI option ROM or VBIOS) into separate function. Created a new function to check if extended VBT region is required. This will be helpful in the subsequent changes to determine if extended VBT region is needed and handle memory allocation accordingly. BUG=None BRANCH=None TEST=check the address of extended VBT region and address is coming correctly. Change-Id: I479d57cd326567192a3cd1969f8125ffe1934399 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-11drivers/spi: Add winbond chip detailsShaik Sajida Bhanu
Added winbond W25Q512NW chip details. Change-Id: I5545c9431891f7fa74c1527591fb7c3cd3aba687 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-06-10drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPSMartin Roth
The loads of the FSPM and FSPS binaries are not insignificant amounts of time, and without these timestamps, it's not clear what's going on in those time blocks. For FSPM, the timestamps can run together to make it look like that time is still part of the romstage init time. Example: 6:end of verified boot 387,390 (5,402) 13:starting to load romstage 401,931 (14,541) 14:finished loading romstage 420,560 (18,629) 970:loading FSP-M 450,698 (30,138) 15:starting LZMA decompress (ignore for x86) 464,173 (13,475) 16:finished LZMA decompress (ignore for x86) 517,860 (53,687) ... 9:finished loading ramstage 737,191 (18,377) 10:start of ramstage 757,584 (20,393) 30:device enumeration 790,382 (32,798) 971:loading FSP-S 840,186 (49,804) 15:starting LZMA decompress (ignore for x86) 853,834 (13,648) 16:finished LZMA decompress (ignore for x86) 888,830 (34,996) BUG=b:188981986 TEST=Build & Boot guybrush, look at timestamps. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-07drivers/generic/ioapic: Use arch/x86/ioapicKyösti Mälkki
Change-Id: Ibfaf6693288005463e45831fe100a5052e97cf2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07drivers/pcie/rtd3/device: Add PCIe RTD3 driverRaul E Rangel
This driver was inspired from soc/intel/common/block/pci/rtd3. I decided to copy and modify it because the Intel driver has a lot of Intel specific code. This driver has been stripped down to only provide a power resource and set the StorageD3Enable property. This driver is SoC agnostic and does not handle suspending the actual PCIe root port. That should be implemented by an SoC specific driver. This is required for Guybrush to suspend/resume properly because the NVMe power is tied to the S0 power rails, so the kernel needs to place the device into D3. BUG=b:184617186 TEST=Guybrush is able to suspend/resume properly. Also see power resource get enabled / disabled. [ 56.075559] power-0416 __acpi_power_off : Power resource [RTD3] turned off [ 56.075562] device_pm-0279 device_set_power : Device [PXSX] transitioned to D3cold [ 56.075567] pci_pm_suspend_noirq: nvme 0000:02:00.0: PCI PM: Suspend power state: D3cold [ 56.075569] nvme 0000:02:00.0: pci_pm_suspend_noirq+0x0/0x413 returned 0 after 15978 usecs [ 123.464874] nvme 0000:02:00.0: calling pci_pm_resume_noirq+0x0/0x11d @ 7, parent: 0000:00:02.4 [ 123.464891] acpi_device_set_power: ACPI: \_SB_.PCI0.GP14.PXSX: Power state change: D3cold -> D0 [ 123.464982] power-0360 __acpi_power_on : Power resource [RTD3] turned on [ 123.464984] device_pm-0279 device_set_power : Device [PXSX] transitioned to D0 [ 123.465039] nvme 0000:02:00.0: pci_pm_resume_noirq+0x0/0x11d returned 0 after 158 usecs Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07drivers/smmstore: Enable SMMSTORE V2 by default for Tianocore UEFIPAYLOADMatt DeVillier
Tianocore UEFIPAYLOAD now supports SMMSTORE V2, so enable it by default Change-Id: I33582427fe9d3fc7c15014d3a04fcdc533cb1ac8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-04drivers/i2c/designware: Report I2C timings for additional bus speedsWerner Zeh
Since the OS provides its own driver for the I2C controller it can choose to use a bus speed other than the one used at coreboot runtime. In this case it would be good to provide a way how the needed bus timings are communicated to the OS, since these are very board-specific and there is no way that the OS can know them other than read the appropriate ACPI reported timings. This patch adds some code to report additional bus speed timings if there are some defined in the devicetree. Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-06-04intel/common/block: Move mainboard api to tcss common blockDeepti Deshatty
As per the comments in CB:54090 mainboard api mainboard_tcss_get_port_info() is simplified and moved to tcss common block code. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-06-01drivers/intel/mipi_camera: Add macros to increase code readabilityVarshit B Pandya
This will be used to pass information to driver through ACPI in devicetree. Example https://review.coreboot.org/c/coreboot/+/52013 register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" TEST=Add these macros in devicetree, build and check static.c for consistency Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.corp-partner.google.com> Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/55097 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30drivers/pc80/mc146818rtc: Check date and time for sanityWerner Zeh
There are cases where the RTC_VRT bit in register D stays set after a power failure while the real date and time registers can contain rubbish values (can happen when RTC is not buffered). If we do not detect this invalid date and/or time here and keep it, Linux will use these bad values for the initial timekeeper init. This in turn can lead to dates before 1970 in user land which can break a lot assumptions. To fix this, check date and time sanity when the RTC is initialized and reset the values if needed. Change-Id: I5bc600c78bab50c70372600347f63156df127012 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54914 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI supportWerner Zeh
In commit b64db833d6 a basic ACPI support was added to the driver. With this support an SSDT-entry is created for this RTC and it is now visible to the OS via ACPI. In Linux the PNP-devices, which are reported over ACPI, are scanned rather early and if the entry is found, the device is claimed even if there is no driver available yet. In this case, when the native RTC-driver without ACPI-support is loaded and tries to register this device, the RTC is already blocked by the PNP-drivers and cannot be used anymore. This leads to a non-usable RTC on kernels where the needed ACPI-extension is not yet merged into the RTC driver. This patch provides a way to disable the ACPI-support for the RTC if needed. Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55003 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30Apply more uses for Kconfig TPMKyösti Mälkki
Change-Id: I54b296563940cd46fe9da9fe789b746f2fc1987d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-29drivers/intel/fsp2_0: Make fsp_temp_ram_exit() function staticSubrata Banik
fsp_temp_ram_exit() function is only getting called by late_car_teardown() function inside temp_ram_exit.c file. Hence, make function as static and removed from include/fsp/api.h. Change-Id: I2239400e475482bc21f771d41a5ac524222d40fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-27drivers/intel/fsp1_1: Drop empty weak functionsAngel Pons
The only FSP 1.1 platform is Braswell. Drop unnecessary functions which only have a weak stub definition. Change-Id: Ie60213e5a6ae67bd8b982ee505f4b512253577c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-05-27drivers/intel/fsp1_1: Drop weak function definitionAngel Pons
The only FSP 1.1 platform is Braswell, which has a non-weak definition for the `soc_silicon_init_params` function. This changes the resulting BUILD_TIMELESS=1 coreboot image for Facebook fbg1701, for some reason. Change-Id: I2a1b51cda9eb21d7af8372c16a43195a4bdd9543 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27drivers/intel/fsp1_1: Drop unused weak definitionsAngel Pons
The only FSP 1.1 platform is Braswell. Drop unused weak definitions for functions where a non-weak definition always exists. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: Ifaf40a1cd661b123911fbeaafeb2b7002559a435 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27drivers/intel/fsp1_1: Drop some MMA leftoversAngel Pons
Commit 736a1028fbaef97d32221cadb1f512c9a8960a76 (drivers/intel/fsp1_1: Drop dead MMA code) dropped FSP 1.1 MMA code, but missed a few things. Change-Id: I556e7125eff21c49609bb1e5e1f23e99e692756f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-27nb/amd/pi/00630F01: Remove unused directory and codeAngel Pons
No board uses AMD PI 00630F01, so drop it. And drop a single reference to the now-removed `NORTHBRIDGE_AMD_PI_00630F01` Kconfig option inside the `drivers/amd/agesa/acpi_tables.c` file. Change-Id: Ibc45a4a6041220ed22273c1d41f9b796e1acb901 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54897 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26Add Kconfig TPMKyösti Mälkki
Defined as TPM1 || TPM2. Change-Id: I18c26d6991c2ccf782a515a8e90a3eb82b53b0e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26option: Decouple API from CMOS backendAngel Pons
Prepare to allow using other backends to store options. Change-Id: I3f838d27bf476207c6dc8f2c1f15c3fa9ae47d87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-20drivers/gpio_keys: Add SW_MUTE_DEVICEBen Zhang
Added SW_MUTE_DEVICE event type for mic mute switch. BUG=b:184593945 BRANCH=puff TEST=build image and verify with evtest on puff: /dev/input/event3: mic_mute_switch UI event_device_info receives the proper name. Change-Id: I09c52dc3df63e266c73741b102a22f8a2b896791 Signed-off-by: Ben Zhang <benzh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20drivers/gpio_keys: Add label to set input device nameBen Zhang
Added the label field to the gpio_keys _DSD so that the kernel driver can use a meaningful name instead of the generic _HID PRP0001. BUG=b:184593945 BRANCH=puff TEST=build image and verify with evtest on puff: /dev/input/event3: mic_mute_switch UI event_device_info receives the proper name. Change-Id: I0377851b9cf23bab31930aed6e7de91b4ac3505b Signed-off-by: Ben Zhang <benzh@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-20drivers/acpi: Add a chip driver to generate thermal zoneRaul E Rangel
Given the following device tree entry: chip drivers/acpi/thermal_zone register "description" = ""CPU"" use chrome_ec as temperature_controller register "sensor_id" = "0" register "polling_period" = "10" register "critical_temperature" = "91" register "passive_config" = "{ .temperature = 85, }" register "use_acpi1_thermal_zone_scope" = "true" device generic 0 on end end It will generate the following: Scope (\_TZ) { ThermalZone (TM00) { Name (_STR, "CPU") // _STR: Description String Name (_RTV, Zero) // _RTV: Relative Temperature Values Name (_TZP, 0x64) // _TZP: Thermal Zone Polling Name (_CRT, 0x0E39) // _CRT: Critical Temperature Name (_PSV, 0x0DFD) // _PSV: Passive Temperature Name (_PSL, Package (0x10) // _PSL: Passive List { \_SB.CP00, \_SB.CP01, \_SB.CP02, \_SB.CP03, \_SB.CP04, \_SB.CP05, \_SB.CP06, \_SB.CP07, \_SB.CP08, \_SB.CP09, }) Name (_TC1, 0x02) // _TC1: Thermal Constant 1 Name (_TC2, 0x05) // _TC2: Thermal Constant 2 Name (_TSP, 0x14) // _TSP: Thermal Sampling Period Method (_TMP, 0, Serialized) // _TMP: Temperature { Return (\_SB.PCI0.LPCB.EC0.CREC.TMP (Zero)) } } } BUG=b:186166365 TEST=Boot guybrush to OS and verify thermal zone works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iee2a42db749f18eef6c3f73cdbb3441567301e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-18drivers/intel/usb4: Update driver to support Retimer firmware upgradeJohn Zhao
Along with upstream kernel for Retimer firmware upgrade, coreboot provides DFPx under host router where each DFP has its PLD and DSM. The DFPx's functions encapsulates power control through GPIO, PD suspend/resume and modes setting for Retimer firmware update under NDA scenario. BUG=b:186521258 TEST=Booted to kernel and validated host router's DFPx properties after decomposing SSDT table. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I81bef80729f6df57119f5523358620cb015e5406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52712 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optionalVitaly Rodionov
HSBIAS_SENSE_EN configures HSBIAS output current sense through the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce the potential pop noise during the headset plug out slowly. But on some platforms ESD voltage will affect it causing test to fail, especially with CTIA headset type. For different hardware setups, a designer might want to tweak default behavior. Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/52981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12include/console: Fix FSP Notify phase postcodes discrepancySubrata Banik
List of changes: 1. Make the FSP notify phases name prior in comments section. 2. Fix discrepancies in FSP notify before and after postcode comments. 3. Add FSP notify postcode macros for after pci enumeration(0xa2) and ready to boot(0xa3) call. Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52894 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08trogdor: Add backlight support for sn65dsi86bridge for HomestarVinod Polimera
Add backlight support in sn65dsi86bridge through the AUX channel using eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board. Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08drivers/sn65dsi86: Switch EDID reading to use "indirect mode"Julius Werner
The SN65DSI86 eDP bridge supports two ways to read the EDID: for now we've been using "direct mode", which works by basically making the bridge I2C device listen to another chip address besides its own and proxy all requests received there directly to the eDP AUX channel. The great part about that mode is that it is super easy and hassle-free to use. The not so great part about it is that it doesn't work: for EDID extensions, the last byte (which happens to contain the checksum) is somehow always read as zero. We presume this is a hardware bug in the bridge part. The other, much more annoying way is "indirect mode", where each byte transmitted over the AUX channel has to be manually set up in the I2C registers of the bridge, just like we're already doing with DPCD transactions. Thankfully, we can reuse most of the DPCD code for this so it's not a lot of extra code. It's a bit slower but not as much as you'd expect (26ms instead of 18ms on my board), and the difference is not very relevant compared to common total times for display init. Also, some of the (previously unused) enum definitions for the AUX_CMD mode field of the bridge had just been plain wrong for some reason, and needed to be fixed to make this work. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52959 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06drivers/pc80/rtc/option.c: Constrain API to integer valuesAngel Pons
None of the options accessed within coreboot is a string, and there are no guarantees that the code works as intended with them. Given that the current option API only supports integers for now, do not try to access options whose type is 's' (string). Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-06security/tpm: Add option to init TPM in bootblockArthur Heymans
When using a hardware assisted root of trust measurement, like Intel TXT/CBnT, the TPM init needs to happen inside the bootblock to form a proper chain of trust. Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51923 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans
The only use case for FSP-T in coreboot is for 'Intel Bootguard' support at the moment. Bootguard can do verification FSP-T but there is no verification on whether the FSP found by walkcbfs_asm is the one actually verified as an IBB by Bootguard. A fixed pointer needs to be used. TESTED on OCP/Deltalake, still boots. Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-05-05drivers/genesyslogic/gl9755: Disable debug mode to enable circuit protectionsBen Chuang
In order for short circuit protection and over current protection to work, the debug mode needs to be turned off. BUG=b:185749961 TEST=build and test Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: Iacfa3c668a52d1bae15fe82f1c614d0ebd93a957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-05-05drivers/i2c/generic: Set S0W to D3hot for wake deviceTony Huang
If device is supported as a wake source, _S0W should be set to D3hot. This ensures that the device is put into D3hot by the OSPM. Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM. The devices we are currently looking at for touchscreen/touchpad do not really support auxiliary power and so do not support wake from D3cold. BUG=b:186070097 TEST=build and check device wake state _S0W set to 3 in ssdt table. Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-04drivers/intel/fsp1_1: Remove verstage compilation unitsArthur Heymans
Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and therefore verstage is not possible either. Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-30drivers/i2c/designware: Use safe defaults for SCL parametersKyösti Mälkki
Inspired by discussion in CB:22822. If I2C bus step response has not been measured, assume the layout to have been designed with a minimal capacitance and SCL rise and fall times of 0 ns. The calculations will add the required amount of reference clocks for the host to drive SCL high or low, such that the maximum bus frequency specification is met. Change-Id: Icbafae22c83ffbc16c179fb5412fb4fd6b70813a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52723 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30drivers/intel/gma/Kconfig: Simplify CFL/WHL/CML conditionsAngel Pons
Change-Id: Id56761b2a57754b8f8d726a4bd2674ffa6fd1159 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-04-28drivers/intel/gma/Kconfig: Simplify Skylake/Kaby Lake conditionsAngel Pons
Use `SOC_INTEL_COMMON_SKYLAKE_BASE` to simplify conditions. Change-Id: Ie69bde31b58bbd973db00bd578a51477c5b21cab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-25drivers/pc80/rtc: Factor out CMOS entry lookupAngel Pons
The procedure is identical for reads and writes. Factor it out. Change-Id: I22b1d334270881734b34312f1fee01aa110a6db4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52636 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23drivers/i2c/cs42l42: Add driver for generating device in SSDTVitaly Rodionov
This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel This was tested on the octopus/variants/fleex ainboard to ensure that the SSDT contained the equivalent parameters that are provided by the current DSDT object Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Change-Id: I7c3145b20a1ba743d91eb64b93cb001db3854c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>