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2023-03-23soc/intel: Rename IA common code module from `TOM` to `RAMTOP`Subrata Banik
This patch renames all references of `top_of_ram` (TOM) in IA common `basecode` module (for example: functions, variables, Kconfig, Makefile and comments) with `ramtop` aka top_of_ram to make it more meaningful and to avoid conflicts with Intel SA chipset TOM registers. BUG=Able to build and boot google/rex with the same ~49ms savings in place. Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-22drivers/intel/fsp2_0: Add support for FSP_ERROR_INFO_HOBRay Han Lim, Ng
Add a new Kconfig CONFIG_ENABLE_FSP_ERROR_INFO option to enable retrieval of FSP_ERROR_INFO_HOB from HobList created by FSP. Such a HOB could be generated by Intel SPR-SP FSP. This HOB data is defined in Intel®Firmware Support Package External Architecture Specification v2.1 Doc#611786-2.1. Change-Id: I812d1c22c1bbe5146630948ca6ca12c46ffd5504 Signed-off-by: Ray Han Lim, Ng <ray.han.lim.ng@intel.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-13drivers/intel/fsp2_0: Have provision for caching TOM regionSubrata Banik
This patch enables early caching of TOM region to optimize the boot time if valid mrc cache is found (i.e. except the first boot after flashing/updating few AP firmware image). TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia575ad0f99d5b0fd015e40b0862e8560700f6c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-07drivers/intel/fsp2_0: Print `mrc_cache` size in decimalSubrata Banik
This patch updates the print msg of mrc_cache size from hex to decimal for easier understanding while debugging the issue. TEST=Able to build and boot google/rex. Without this patch: [SPEW ] MRC cache found, size ee75 With this patch: [SPEW ] MRC cache found, size 61045 bytes Change-Id: I69feeb36423e47a5992c9f27d9a7042803a492cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-03-03drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacksJan Samek
As discused earlier, the callback name 'mb_adjust_cfg' was considered too generic. The new naming is chosen to be consistent with other drivers' callback names designed to be used at mainboard level. Also other functions, namely 'mb_get_edid' and 'mb_select_edid_table' are renamed accordingly. BUG=none TEST=Builds for siemens/mc_apl{1,4,5,7} and siemens/mc_ehl boards complete successfully. Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02drivers/net/phy/m88e1512: Add a way to set output impedance manuallyMario Scheithauer
This patch provides the functionality to set the RGMII output impedance manually. To ensure that no race condition occurs, the driver strength values for PMOS and NMOS should be written to the RGMII output impedance calibration override register first and then the force bit should be enabled with a second write to this register. Link to the Marvell PHY 88E1512 datasheet: https://web.archive.org/web/20230125074158/https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-ethernet-phys-alaska-88e151x-datasheet.pdf Change-Id: I87fa03aa49514cdc33d2911d7f23386c8f69d95b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02drivers/net/phy/m88e1512: Switch the page back to 0 only onceMario Scheithauer
When the configuration of Marvell PHY 88E1512 is finished, then switch the page back to 0 only once at the end of the Init function. Change-Id: I9e516870a7c5928724df2bd3ac9c5c8f3249af2e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73017 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-21vga: Fix the support of extended ASCIIHsuan Ting Chen
VGA defineds the extended ASCII set based on CP437, but there is a bug on printing them: in vga_write_at_offset(), we perform a bitwise or between 'unsigned short' and 'signed char': ``` p[i] = 0x0F00 | string[i]; ``` If we want to show an extended ASCII character, string[i] will be negative and this bitwise operation will fail due to their implicit casting rule: convert signed char to unsigned short by adding 65536. To fix this, we need to cast the string to unsigned char manually somewhere. Since we still want to leverage the built-in string utilities which only accepts const char*, we still preserve the original prototypes before, and cast it until we write into the frame buffer. BRANCH=brya BUG=b:264666392 TEST=emerge-brya coreboot chromeos-bootimage and verify drawing characters with code > 127. Change-Id: I9cd65fe9794e5b0d338147924f28efd27fc8a1e8 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-16drivers/ocp/vpd: Override mainboard_set_smm_log_levelJohnny Lin
VPD variable 'smm_log_level' can be read and passed to SMM for overriding SMM log level. By default it's zero therefore it disables most of the SMM log. When we need to see SMM log we can set this VPD to a larger value to enable it. Implement mainboard_set_smm_log_level() that reads VPD variables for SMM log level. Change-Id: I90d471d1d070d9a0f1a82ca9da8a2c034c9fd574 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71992 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-15pc80/i8254: Add speaker beep functionMichał Żygowski
Some platforms have an onboard speaker which could be used as an indicator of successful boot or critical error, e.g. in die_notify function. The function assumes that SPKR GPIO is properly configured by the platform code. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-02-14drivers/i2c/nau8825: Fix typo: deboune -> debounceMatt DeVillier
Allows Windows/Linux driver to use the proper jack eject debounce time. Credit to coolstar for identifying the issue. Change-Id: I32b94b9285f7c85ff1d67b3d78c845835bbf90d7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-13drivers/smmstore: Fix fmap_config.h dependencyBenjamin Doron
Update the fmap_config.h dependency now that SMMSTORE is compiled into all phases. This makes parallel builds work again. Change-Id: Ie8a44c28ea9f3d4794f06d0fd320f5c765513a32 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-12drivers/smmstore: Expose region devicePatrick Rudolph
Allow other drivers to use the SMMSTORE region device. Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-10drivers/fsp2: Don't print garbage if the FSP signature doesn't matchFred Reitberger
Using a &uint64_t as a string argument does not include the required NULL character termination. Update the format string to only print the 8 desired characters and not continue printing stack memory until a NULL is found. Before: [EMERG] Invalid UPD signature! FSP provided "AMD_01_M;....`", expected was "CEZANE_MAMD_01_M;....`". After: [EMERG] Invalid UPD signature! FSP provided "AMD_01_M", expected was "CEZANE_M". Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib334daa8518a92e0cf3d22c4d95908f4c84afe04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72911 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-10drivers/vpd: Demote FMAP not found printk from error to warnMatt DeVillier
Not all firmware which uses VPD uses both RO and RW regions, so either one not existing is not necessarily an error. Change-Id: I50f43a25ee24a642c39e2f0b52de2d4fef023f3b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72476 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-10drivers/net/r8168: Demote MAC lookup printk from error to warnMatt DeVillier
Some older devices use the vpd key 'ethernet_mac' vs 'ethernet_mac0' for the first/only LAN NIC, so don't treat the key lookup as an error. If no MAC is able to be found, another error will be printed later in the driver init. TEST=build/boot google/fizz, dump cbmem log, verify 'ethernet_mac0' lookup failure printk output at warning level. Change-Id: If5226f4686a819a7020fd14f130181420ee1462b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-08drivers/ocp, mb/ocp/deltalake: move get_loglevel_from_vpd functionJohnny Lin
Move get_loglevel_from_vpd from mb/ocp/deltalake to driver drivers/ocp/vpd/loglevel_vpd.c. Change-Id: I70af1051f63c527fd8150f5ecbe4765b4aaacd20 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71936 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-07src: Move POST_BOOTBLOCK_CAR to common postcodes and use itMartin Roth
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-02drv/i2c/ptn3460: Use PTN_EDID_LEN instead of constantJan Samek
Contents of the EDID are passed by a reference to an array of length 0x80, for which the macro 'PTN_EDID_LEN' has already been around. This patch makes use of this macro within the driver and mainboard implementation utilizing it. BUG=none TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards. Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31drivers/intel/fsp2_0: Simplify check for CONFIG_SAVE_MRC_AFTER_FSPSDavid Hendricks
This uses a simpler form of #if to check if CONFIG_SAVE_MRC_AFTER_FSPS is enabled, referencing the Kconfig variable only once and defaulting to the original behavior if not. Change-Id: I4711c1474d9a3a5c685dd31561619c568fab075c Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72587 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-29drivers/intel/fsp2_0: Add saving MRC data after FSP-S optionJohnny Lin
When Kconfig SAVE_MRC_AFTER_FSPS is selected, save MRC training data after FSP-S instead of FSP-M. For now only SPR-SP server FSP supports this. This issue surfaces with SPR-SP, because of the memory type (DDR5 support) and memory capacity (more memory controllers, bigger DRAM capacity). Therefore Intel decided to save MRC training data after FSP-S with SPR-SP FSP. Change-Id: I3bab0c5004e717e842b484c89187e8c0b9c2b3eb Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71950 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27drivers/i2c/ptn3460: Use cb_err in mb_adjust_cfgJan Samek
Return generic coreboot error codes from the mb_adjust_cfg callback used in mainboards instead of '-1' constant and a driver-specific success-indicating define. BUG=none TEST=Boards siemens/mc_apl{1,4,5,7} and siemens/mc_ehl3 build correctly. Change-Id: I5e0d4e67703db518ed239a845f43047f569b94ec Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-26soc/intel/alderlake: Wait for panel power cycle to completeJeremy Compostella
The Alder Lake PEIM graphics driver executed as part of the FSP does not wait for the panel power cycle to complete before it initializes communication with the display. It can result in AUX channel communication time out and PEIM graphics driver failing to bring up graphics. If we have performed some graphics operation in romstage, it is possible that a panel power cycle is still in progress. To prevent any issue with the PEIM graphics driver it is preferable to ensure that panel power cycle is complete. This patch replaces commit ba2cef5b5493 ("soc/intel/common/block/early_graphics: Introduce a 200 ms delay") workaround patch. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible in the recovery flow Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26drivers/intel/gma: Use libgfxinit Update_Output to turn off graphicsJeremy Compostella
We were using the libgfxinit `Initialize' function with the `Clean_State' parameter because the more appropriate `Update_Output' function was not performing all the necessary clean up operations for the PEIM driver to be successful when libgfxinit was used in romstage. Thanks to a lot of experiments and some log analysis efforts, we were able to identify the missing operation and fix the `Update_Output' function (cf. https://review.coreboot.org/c/libgfxinit/+/72123). The `initialized' global variable is now unnecessary as we track the initialization in the Ada code instead. Since the `Update_Output' function does not return any value, this patch modifies the `gma_gfxstop' prototype accordingly. This does not have any impact as the return value was not used anyway. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-26drivers/intel/gma: Dump output setting only if DEBUG_ADA_CODE is setJeremy Compostella
This patch restricts the dump of the vebose graphics output settings to configuration with the `DEBUG_ADA_CODE' flag set. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Configuration dump is seen only if DEBUG_ADA_CODE is set Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72418 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-20drivers/intel/gma/hires_fb/gma-gfx_init.adb: Remove spaces before tabsElyes Haouas
Change-Id: Ifab3fcd2de8f0c1672d1a9a21c8e0c5dba5b7443 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72077 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-20drivers/intel/gma/text_fb/gma-gfx_init.adb: Remove spaces before tabsElyes Haouas
Change-Id: I421602c81d9a186eb36a289d6e5048b5aa343a2d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-19drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per portKane Chen
This patch supports projects to use _DSM to control USB3 U1/U2 transition per port. More details can be found in https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm- The ACPI and USB driver of linux kernel need corresponding functions to support this feature. Please see https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm BUG=b:253402457 TEST=tested on felwinter and found _DSM method is created. Change-Id: Iffb2498e26352a3f120c097c50587324e311e8ba Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15drivers/uart/acpi: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. This mirrors the change made for drivers/i2c/generic. TEST=untested, as no boards selected this option. Change-Id: Icb60502a4a7c5e7a1fcf1ee60e23c77e00d6de7b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71851 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15drivers/spi/acpi: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. This mirrors the change made for drivers/i2c/generic. TEST=untested, as no boards selected this option. Change-Id: I4f95d0e453d89b7e1978d3efac304518304495d1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71850 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-14drivers/intel/i210/Makefile.inc: Fix "No such file or directory" errorElyes Haouas
Fix: cc1: error: src/drivers/intel/i210: No such file or directory [-Werror=missing-include-dirs] Change-Id: I94b0f99353ed3a582ea590cbc6b12dec6294c75d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13drivers/i2c/pca9538/Makefile.inc: Remove unused pathElyes Haouas
Change-Id: I435837381a966b61081d023447a6e7fdfd9a9348 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-13drivers/intel/i210.h: Remove 'extern' from declarationArthur Heymans
"extern" is always implied with function declarations. Also remove the comment as the linker will just tell you the same if a definition is missing. Change-Id: I53679ab57981790f82affb46a006281b348af574 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71869 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-12treewide: Remove unused <cpu/amd/mtrr.h>Elyes Haouas
Change-Id: Ibff33c08a1d583b19b205a66d5a4267df65ced75 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-12drivers/intel/gma: Enable Alder Lake libgfxinit supportJeremy Compostella
This CL requires the following libgfxinit patches: - https://review.coreboot.org/c/libgfxinit/+/65087 - https://review.coreboot.org/c/libgfxinit/+/65178 - https://review.coreboot.org/c/libgfxinit/+/67489 - https://review.coreboot.org/c/libgfxinit/+/65140 - https://review.coreboot.org/c/libgfxinit/+/67490 - https://review.coreboot.org/c/libgfxinit/+/67491 - https://review.coreboot.org/c/libgfxinit/+/67492 - https://review.coreboot.org/c/libgfxinit/+/67493 - https://review.coreboot.org/c/libgfxinit/+/67494 - https://review.coreboot.org/c/libgfxinit/+/67495 - https://review.coreboot.org/c/libgfxinit/+/67496 - https://review.coreboot.org/c/libgfxinit/+/67497 - https://review.coreboot.org/c/libgfxinit/+/67498 - https://review.coreboot.org/c/libgfxinit/+/67499 - https://review.coreboot.org/c/libgfxinit/+/67500 - https://review.coreboot.org/c/libgfxinit/+/67800 - https://review.coreboot.org/c/libgfxinit/+/67801 - https://review.coreboot.org/c/libgfxinit/+/67802 - https://review.coreboot.org/c/libgfxinit/+/69341 BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit is compiled with the Alder Lake configuration Change-Id: I2de94556f8105447788aaa02340ad669fb68ca0c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70301 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/common/block: Add Intel VGA early graphics supportJeremy Compostella
This patch introduces an early graphics driver which can be used in romstage in cache-as-ram mode. The implementation relies on `libgfxinit' and provide VGA text mode support. SoCs wanting to take advantage of this driver must implement the `early_graphics_soc_panel_init' function to set the panel power sequence timing parameters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Graphics bring up observed on skolas with extra patches Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11drivers/ocp/vpd: add get_cxl_mode_from_vpd()Johnny Lin
cxl_mode VPD variable supports 3 modes: CXL_DISABLED, CXL_SYSTEM_MEMORY and CXL_SPM. Change-Id: Ib3bf85fbe687680db3c11efa908c4fb351be9c44 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11drivers/intel/gma: Hook up libgfxinit in romstageJeremy Compostella
A mainboard port needs to: - select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage (and ramstage) for the graphic device. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit compiles in romstage. libgfxinit successfully executes in romstage and ramstage using the requested MMIO setting on skolas. Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09treewide: Remove unused <cpu/amd/msr.h>Elyes Haouas
Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-08drivers/amd: Update to use defined post codesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2d5700534c07e89b3908a2e6b827db919a48795d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-07drivers/pc80/vga: Add legacy VGA romstage supportJeremy Compostella
This is support for adding legacy VGA support into romstage. Support for this is being provided by libgfxinit. The current use case allows us to initialize the display before memory init (prior to physical memory init) to inform the user when lengthy memory training is needed. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=VGA code compiles for romstage Change-Id: I81309871e8db71657b2a9816708141f121d767d3 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70278 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02drivers/pc80/vga: Add API to write multi-line video messageSubrata Banik
This patch provides an API to allow users to output multi-line messages using VGA framebuffer. The current limitation with multiline message is that, vga_line_write() function is unable to understand newline character hence, eventually output multiple lines separated with a newline character with a single line statement. This patch ensures to parse the entire string and split it into multiple lines based on the newline character and print each line separately to the VFG framebuffer. User can choose to align the output video message as per given choice between left/center/right of the screen (i.e. enum VGA_TEXT_ALIGNMENT ). Additionally, added macros to define the horizontal screen alignment as well. Ideally if user would like to print the video message at the middle of the screen then the vertical alignment would be `VGA_TEXT_CENTER` and horizontal alignment would be `VGA_TEXT_HORIZONTAL_MIDDLE`. TEST=Able to build and boot Google/Taeko. While output a video message such as : "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device." Without this patch: Your device is finishing an update. This may take 1-2 minutes. nPlease do not turn off your device. With this patch: (in Left Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Right Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. (in Center Alignment): Your device is finishing an update. This may take 1-2 minutes. Please do not turn off your device. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27drivers/intel/ish: Add ADL-P ISH DIDSubrata Banik
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is added into SSDT. With this patch: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-26drivers/pc80/vga: Add NULL check for `vga_line_write()`Subrata Banik
This patch ensures vga_line_write() returns if the argument 1 (aka output string) is NULL. TEST=Able to build and boot Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I716ce82c0afe21f7fe2f6d7bdc5229f8087242fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-23Revert "security/tpm/: turn tis_{init,open} into tis_probe"Sergii Dmytruk
This reverts commit d43154486d27323f64334203e9bc8baf08af6845. From CB:68991: This causes CraterLake boot up process to die. Investigation in progress. Change-Id: I4a6c11b0e638a891108fe230bdaea92d5fbca020 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: siemens-bot Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-23Revert "drivers/pc80/tpm: probe for TPM family of a device"Sergii Dmytruk
This reverts commit 907a81e2a79f394c316644429165ae66679bafd6. This reportedly breaks TPM and measured boot flow completely. Change-Id: Id0d98ecc7807faa1617ad16dc9a24343c5a66b06 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-23mb/siemens/mc_apl7: Init I2C controller before PTN3460 is initializedWerner Zeh
When PTN3460_EARLY_INIT is selected, the PTN3460 (DP-2-LVDS-bridge) will be initialized before all devices are initialized. This is necessary to get a valid EDID data set into the PTN3460 before the graphic controller is initialized in order to be able to show a splash screen. For ptn3460_init() to work properly the I2C bus this bridge is connected to needs to be initialized. As this I2C bus initialization would be done too late in the normal flow, it needs to be called here explicitly before ptn3460_init() to initialize the I2C bus with the needed conditions. Otherwise the default I2C settings of the controller will be used which results in a clock rate too high for this mainboard. Test=Measure I2C bus signals and make sure that the clock is <= 400 kHz. Change-Id: I1775fb7c2d29f765224d0e7c7ff9fcd4dbf847c5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71226 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23soc/intel: Drop SoC specific DPTF implementationSubrata Banik
This patch drops the SoC specific implementation as DPTF driver can now fillin those platform specific data using SoC specific macros. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If65976f15374ba2410b537b1646ce466ba02969b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-23drivers/intel/dptf: Implement API to fill DPTF platform infoSubrata Banik
This patch fills in a generic platform info structure based on the inputs from the SoC dptf header file (soc/dptf.h). It will help to make things common and drop unnecessary back and forth call between common code and SoC code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3521882495485cef686655abd65337515bae5faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71111 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b)` with `a & b`. Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where possible. Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22drivers/intel/fsp2_0: Don't include <commonlib/bsd/compiler.h>Elyes Haouas
<commonlib/bsd/compiler.h> is automatically included in all compilation units by the build system. (see Documentation/contributing/coding_style.md) Change-Id: I09ed0c5eb2054c3add026f200c0fd3f609f73197 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67905 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22drivers/ocp: add VPD processing frameworkJonathan Zhang
Add VPD processing framework to be shared by OCP mainboards: * define VPD configuration items in vpd.h. * add helper functions: ** get_bool_from_vpd() ** get_int_from_vpd_range() Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-12-22drivers/intel/dptf: Add new config for EISA HID supportSubrata Banik
This patch adds config to let SoC users (config) to choose if EISA HID is supported. All SoC config would like to support EISA HID need to select `HAVE_DPTF_EISA_HID` config. Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6bf64f74c447b28665d31a64181c33df882d5d06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71108 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22drivers/intel/dptf: Add `soc_` prefix for `get_dptf_platform_info()`Subrata Banik
This patch makes the SoC specific callback code more readable by adding `soc_` prefix into the `get_dptf_platform_info()`. In nutshell this patch renames `get_dptf_platform_info()` to `soc_get_dptf_platform_info()`. TEST=Able to build Google/Rex without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-12-21drivers/pc80/tpm: probe for TPM family of a deviceSergii Dmytruk
At the moment this is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Later this TPM family will be returned to the caller. Change-Id: I5464771836c66bcc441efb7189ded416b8f53827 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69023 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21drivers/spi/tpm: verify device supports TPM2Sergii Dmytruk
This is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Change-Id: Ib2840a21b3be8928d39570281f86a0e26b38b5f9 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69022 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21security/tpm/: turn tis_{init,open} into tis_probeSergii Dmytruk
Init was always followed by open and after successful initialization we need only send-receive function, which is now returned by tis_probe on success further reducing number of functions to export from drivers. Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68991 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21drivers/i2c/tpm: splice tpm_vendor_specific structSergii Dmytruk
Move `locality` field to `struct tpm_inf_dev` and put the rest directly into `tpm_chip`. Change-Id: Ic3644290963aca9f8dc7cd8ef754352865ef8d2c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-19tree: Replace Or(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b)` with `a | b`. Change-Id: I73842cd4843ebb0b48440059ae9dcf6c82235a76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70845 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19drivers/intel/fsp2_0: Implement `mps2_noop_get_number_of_processors()`Subrata Banik
This patch implements mps2_noop_get_number_of_processors() API with minimal information required for Intel MTL FSP to utilise the `MP_SERVICES_PPI_V2_NOOP` config. The major difference between Intel ADL and MTL FSP in terms of doing CPU feature programming aka utilizing MP PPI wrapper code is that, starting with MTL, FSP has dropped the `SkipMpInit` UPD. It means now, coreboot doesn't have any way to skip FSP doing MP Init operation. But during ADL, coreboot had introduced the MP_SERVICES_PPI_V2_NOOP config that is used to skip FSP about actually running any CPU feature programming on APs. The idea is to use the same config even in MTL to provide only the must have information (to bypass any assert in FSP during debug image) to FSP. Passing `FSP_UNSUPPORTED` from mps2_noop_get_number_of_processors() results in `assert` while compiling FSP in debug mode hence, implementing the function to pass only the information about BSP being the active processor along with passing `FSP_SUCCESS` (eventually it makes FSP happy and doesn't run into any issue in debug and/or release mode). TEST=Able to build and boot Google/Rex and Google/Kano while coreboot skip calling into FSP for doing MP init. Change-Id: I75d7e151699782210e86be564b0055d572cacc3f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70555 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-17drivers/generic/nau8315: Change method for HID assignmentDavid Lin
This patch is to change method of HID assignment with compatible id style in nau8315_config and allow mainboards to set it. Signed-off-by: David Lin <CTLIN0@nuvoton.com> Change-Id: Ia6f02e495eeb06290947edc9e44fa25a4ce18956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69965 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-16drivers/i2c/designware: translate return type in dw_i2c_dev_transferFelix Held
dw_i2c_transfer returns an enum cb_err type, but dw_i2c_dev_transfer returns an int, so explicitly translate between the types. Since dw_i2c_transfer only returns either CB_SUCCESS or CB_ERR which are defined as 0 and -1, this won't change behavior of dw_i2c_dev_transfer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf2cbcf6564035d5c0fc13f5d5e7ac0d0425e85d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-16drivers/i2c/designware/dw_i2c: handle bus < 0 in dw_i2c_dev_transferFelix Held
dw_i2c_soc_dev_to_bus will return -1 if it failed to find an I2C bus number for a device. In this case return -1 instead of implicitly casting the -1 to an unsigned int and passing that as bus number to dw_i2c_transfer. The dw_i2c_base_address call inside _dw_i2c_transfer already ended up handling this error case correctly, but better handle the error more directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06b6005cee0c5c43855cb5b388a9911fc286c984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14drivers/wwan/fm: Fix typoSubrata Banik
This patch fixes a typo by adding `Arg0 = 0` to define warm reset. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I92b81697a254c9dab127b200174d32554db1b5cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/70721 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-14drivers/intel/gma/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ifd3a814228df6a399fe1110abf5b5bc18e6fd6d2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-13drivers/intel/ish: Allow adding DmaProperty to _DSDReka Norman
On nissa, the ISH is running closed source firmware, so the ChromeOS security requirements specify it must be behind an IOMMU. Allow adding DmaProperty to the _DSD of the ISH device. This will result in the kernel marking the device as untrusted. BUG=b:249846505 TEST=Check SSDT is correct, and kernel detects the DmaProperty and firmware-name properties. SSDT entry on yaviks with both add_acpi_dma_property and firmware_name set in devictree: Scope (\_SB.PCI0.ISHB) { Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "firmware-name", "adl_ish_lite.bin" } }, ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } Change-Id: Ie1539fc757e72e995e98c3ecf83e705e3bede8c0 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12{drivers,superio}/acpi: Replace ShiftRight(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b)` with `a >> b`. Change-Id: I0751d00186e8dff38e02e7bf7d8ebf5a17514a58 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12drivers/pc80/vga: Fix coding style issuesJeremy Compostella
- Use `size_t' for iteration index variables - Use the `VGA_COLUMN' macro definition instead of the hard-coded value BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Verified on Skolas Change-Id: I1d6595871363ec7602219e72d1260df3722f64de Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70453 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-12drivers/wifi: Move ADL-P CNVi IDs from generic to IA common code CNVi driverKapil Porwal
BUG=b:259716145 TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains the value from the devicetree on google/redrix. Before: Scope (\_SB.PCI0.WFA3) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } After: Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) ... } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12drivers/mrc_cache: Prevent printing errors in expected use casesYu-Ping Wu
The following are considered "expected" situations, where we shouldn't print error messages as in other unexpected errors: 1. When the previous boot is in recovery mode, under certain config combination the normal MRC cache would have been invalidated. Therefore the "couldn't read metadata" error is expected to show in the current normal boot. Special-case this situation by printing a different message. 2. If the platform doesn't have recovery cache (!HAS_RECOVERY_MRC_CACHE) and vboot starts before romstage (!VBOOT_STARTS_IN_ROMSTAGE), then there should be no region for recovery cache. In this case, "failed to locate region type 0" will be shown. Since it's pretty clear from the code that this is the only case for the error to happen, simply change it to BIOS_DEBUG. Also remove a duplicate message when mrc_header_valid() fails. BUG=b:257401937 TEST=emerge-corsola coreboot TEST=Ran `cbmem -1 | grep ERROR` in recovery boot TEST=Ran `cbmem -1 | grep ERROR` in normal boot following recovery boot BRANCH=corsola Change-Id: Ia942eeecaca3f6b2b90bac725279d2dc6174e0fd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69542 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-10drivers/siemens/nc_fpga/nc_fpga_early.c: Use write32p()Elyes Haouas
Change-Id: Ic7139f0adc0ce4556268612f5e77eb01738fc068 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70471 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09drivers/net/atl1e.c: Use {read,write}32p()Elyes Haouas
Change-Id: Idc9dd4434a8023af4758f921f6279d09059166d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-09drivers/generic/bayhub/bh720.c: Use {read,write}32p()Elyes Haouas
Change-Id: I97b073bfc291b13719a199b277f22b477647db8e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70470 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09drivers/ipmi/ipmi_ops.c: Fix typo in error messageArthur Heymans
Change-Id: I43c6dc0eb19d9be908c98fb6316f87747605b91e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51798 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-06drivers/intel/fsp2_0: Update MRC cache in ramstageReka Norman
Currently the MRC cache is updated in romstage, immediately after returning from FSP-M. Since cbmem is not cached in romstage, the update is slow (~6 ms on nissa). Specifically, the new MRC data returned by the FSP is stored in the FSP reserved memory in cbmem, so hashing the new data is slow. Move the MRC cache update to ramstage, where cbmem is cached. On nissa, this saves ~5 ms of boot time. Before: 552:finished loading ChromeOS VPD (RW) 631,667 (16) 3:after RAM initialization 637,703 (6,036) 4:end of romstage 650,307 (12,603) After: 552:finished loading ChromeOS VPD (RW) 631,832 (15) 3:after RAM initialization 633,002 (1,169) 4:end of romstage 645,582 (12,580) In ramstage, save_mrc_data() takes ~138 us. BUG=b:242667207 TEST=MRC caching still works as expected on nivviks - after clearing the MRC cache, memory is retrained on the next boot, but cached data is used on subsequent boots. Change-Id: Ie6aa2dee83a3ab8913830746593935d36a034b8d Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-06drivers/ipmi: Retry ipmi_get_device_id in ipmi_kcs_initwanghao11
Add retry up to 10 seconds maximal in ipmi_get_device_id. Without this retry, on OCP Craterlake with BMC version v2022.28.1, there's a chance that ipmi_get_device_id failed then ipmi device won't be enabled. Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7 Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-05security/tpm: remove tis_close()Sergii Dmytruk
This function was never called from outside of drivers and src/drivers/pc80/tpm/tis.c was the only one doing it in a questionable way. tpm_vendor_cleanup() also isn't needed as one of tis_close() functions was its only caller. Change-Id: I9df76adfc21fca9fa1d1af7c40635ec0684ceb0f Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSDKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70065 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30/: Remove extra space after commaElyes Haouas
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29Revert "src/arch/x86: Use core apic id to get cpu_index()"Arthur Heymans
This reverts commit 095c931cf12924da9011b47aa64f4a6f11d89f13. Previously cpu_info() was implemented with a struct on top of an aligned stack. As FSP changed the stack value cpu_info() could not be used in FSP context (which PPI is). Now cpu_info() uses GDT segments, which FSP does not touch so it can be used. This also exports cpu_infos from cpu.c as it's a convenient way to get the struct device * for a certain index. TESTED on aldrvp: FSP-S works and is able to run code on APs. Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29drivers/net/r8168: Add support for ACPI DmaPropertyKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/osiris. Before: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) } } After: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I647230082362b1093b63793a201eba23a6289121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70016 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29drivers/{wifi,wwan}: Use helper function to add DmaProperty in _DSDKapil Porwal
BUG=b:259716145 TEST=Build google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I991bc822fbb72cfaa9485abe882950fc7bcef498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70023 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25{drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_property`Kapil Porwal
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:259716145 TEST=Verified that the _DSD object is still present in the SSDT. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-25drivers/intel/mipi_camera: Remove IPU ES support entry for RPLjimlai
The current IPU ES entry value is always set to true for RPL and kernel picks the ES version of the main IPU FW even for the production bootloader but loading is not successful due to the authentication failure. On Raptor Lake silicon, the production binaries are backward compatible with ES parts. This change removes the IPU ES support ACPI entry since the kernel needs to load the production IPU main firmware on both the ES/QS parts. BUG=b:258125833 TEST=Verify the Camera functionality by enabling the IPU secure mode on RPL variants with both ES/QS silicon. Signed-off-by: Jim Lai <jim.lai@intel.com> Change-Id: I9fd8ea0dd6ffdb16961bb017ba4388bf99e4d5bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/69929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-24drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSDKapil Porwal
Use correct GUID for DmaProperty in ACPI _DSD. Reference: https://learn.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports Before: Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "DmaProperty", One } } }) After: Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) BUG=b:259716145 TEST=Verified the new GUID is reflected in ACPI SSDT at runtime. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I05b8c3bf23cc43863527bc514d9a96096d45003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69932 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-24drivers/net/phy/m88e1512: Add downshift enableMario Scheithauer
This patch provides the functionality to enable downshift on Marvell PHY. By setting a downshift counter, the PHY is correspondingly often attempted to establish Gigabit link before the PHY downshifts to the next highest speed. The range is limited to 8 trials. To activate downshift, a software reset must follow to take effect. Change-Id: I4224eab6c1fc13824d53556c80435bc130a13bdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69853 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24drivers/net/phy/m88e1512: Add interrupt enableMario Scheithauer
INTn on Marvell PHY can be routed to LED[2] pin. This setting must be made via LED Timer Control Register on page 3. Change-Id: Ida1efbb604c382676b9d13ac8bf14de768f93637 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69433 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24drivers/net/phy/m88e1512: Provide functionality to customize LED statusMario Scheithauer
For Marvel PHY it could be necessary to customize the shown LED status at the connector. The LED status can be changed via Function Control Register on page 3. Link to the Marvell PHY 88E1512 datasheet: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-transceivers/marvell-phys-transceivers-alaska-88e151x-datasheet.pdf Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69386 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24drivers/net/phy/m88e1512: Add new driver for Marvell PHY 88E1512Mario Scheithauer
This driver enables the usage of an external Marvell PHY 88E1512 which should be connected to a SOC internal MAC controller. In a first step it is only the framework of the driver. Functionality will follow with a second patch. Change-Id: I24011860caa7bb206770f9779eb34b689293db10 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69384 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22src/drivers: Remove unnecessary space after castsElyes Haouas
Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69803 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-22drivers/ocp/dmi: move smbios_ec_revision to ocp folderJonathan Zhang
Move smbios_ec_revision to ocp folder so that all ocp boards share the same function without implementing again. TESTED=Execute "dmidecode -t 0" to check corresponding field. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Jonzhang Zhang <jonzhang@meta.com> Change-Id: I898662b78d3dbab1861cee6f1b6e148297a5d11b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20drivers/i2c/rx6110sa/chip.h: Remove confusing bus speed commentJan Samek
There is a note about the default I2C speed of this being 400 kHz despite the logic in rx6110sa.c sets the fallback (correctly) to 100 kHz. This information originally comes from the fact the dw_i2c bus controller default speed is 400 kHz. This is irrelevant to the default speed of this device as it can be used with any bus controller. BUG=none TEST=coreboot builds correctly (no functional changes). Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69545 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistentJan Samek
Set the logging message prefix to the device name instead of the device path in order to make the output consistent with other logging messages in this and other drivers. Change-Id: Ib63b93d52aad220d17f1f4ee0d47a949933ec26d Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69718 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-18drivers/i2c/rv3028c7: Add ACPI generation callbacksJan Samek
Add ACPI generation callback to the driver after obtaining the ACPI HID "MCRY3028" for this device from Microcrystal AG (VID: "MCRY"). Also add I2C bus speed field to the device config structure, which is a required ACPI entry. BUG=none TEST=Disassemble the SSDT table and see whether the device entry "MC28" is generated correctly. Also check whether the RV3028 driver in Linux (drivers/rtc/rtc-rv-3028.c) is bound correctly after adding an ACPI match table to it containing the HID. A proper kernel patch is pending. Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 11:04:30 +0000