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2021-12-31drivers/intel/gma/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b)` with `a + b`. Change-Id: I9d9f1d04f39ffd420655d9297b01b8811339ad08 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-31drivers/intel/gma/acpi: Replace Subtract(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Subtract (a, b)` with `a - b`. Change-Id: I4f6ffd6bbf6a37e041879e50fe41ce3cc856371f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30drivers/intel/gma/acpi: Use ASL 2.0 syntax to access arraysFelix Singer
Replace Index(FOO, 1337) with FOO[1337]. Change-Id: I534c1581e587908feeb06fd7725c5895649dcfb1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-23drivers/net/r8168: Modify to support RTL8125 LEDsRory Liu
The Realtek RTL8125 has four registers for four leds and a feature config register. We use led0 and led2 in brask, so modify ethernet driver. Those registers' IO address are based on RTL8125 datasheet. BUG=b:193750191 TEST=Modify overridetree.cb to verify LEDs' settings. Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-22drivers/generic/bayhub_lv2: Work around known errataTim Wawrzynczak
The Bayhub LV2 has a known errata wherein PCI config registers at offsets 0x234, 0x238, and 0x24C will only correctly accept writes when they are addressed via a DWORD (32-bit) wide write operation on the PCIe bus. Offset 0x234 is the LTR max snoop and max no-snoop latency register, therefore add a finalize callback to this driver which will program the LTR max-snoop/no-snoop register with a 32-bit write using the values from pciexp_get_ltr_max_latencies(). BUG=b:204343849 TEST=verified the PCI config space writes took effect on google/taeko Change-Id: I1813f798faa534fb212cb1a074bc7bcadd17a517 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-15drivers/spi/spi-generic: document SPI_CNTRLR_DEDUCT_CMD_LEN betterFelix Held
This should make it a bit clearer what the differences between SPI_CNTRLR_DEDUCT_OPCODE_LEN and SPI_CNTRLR_DEDUCT_CMD_LEN and the corresponding functionality in spi_crop_chunk are. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I809adebb182fc0866b93372b5b486117176da388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15drivers/spi/spi-generic: fix edge case in spi_crop_chunkFelix Held
In the case of deduct_cmd_len being set and the adjusted cmd_len >= ctrlr_max, ctrlr_max wasn't being adjusted and still had the value of ctrlr->max_xfer_size. Handle this edge case (which we should never run into) by setting ctrlr_max to 0 and printing a warning to the console. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9941b2947bb0a44dfae8ee69f509795dfb0cb241 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-13drivers/intel/usb4/retimer: Add function to correct EC port mappingMAULIK V VAGHELA
Currently coreboot interprets TCSS port number as per physical port number while EC abstracts port number and provides indices as port number. For example, if TCSS port 1 and 3 are enabled on the board, coreboot will interpret port numbers as 0 and 2, but since only 2 ports are enabled in the system EC will assign port numbers as 0 and 1. This creates a port number mismatch while communicating between EC and coreboot. This patch addresses issue where SoC can implement function to map correct EC port as per port enabled in mainboard. BUG=b:207057940 BRANCH=None TEST=Check if code compiles successfully. Functionality will work once function is implemented in SoC code. Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-13drivers/intel/mipi_camera: Add ACPI entry to provide silicon type infoSugnan Prabhu S
Add entry in ACPI table under IPU device to provide silicon type information to IPU driver. IPU kernel driver can decide the type of firmware to load based on this information. BUG=b:207721978 BRANCH=none TEST=Check for the ACPI entry in the SSDT after booting to kernel Change-Id: I4e0af1dd50b9c014cae5454fcd4f9f76d0e0a85f Cq-Depend: chromium:3319905 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03drivers/net/r8168: Add support for Realtek RT8125Alan Huang
The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02drivers/analogix/anx7625: Utilize retry() macroYu-Ping Wu
Utilize retry() macro in wait_aux_op_finish() and anx7625_init() to simplify the code. BUG=none TEST=emerge-asurada coreboot BRANCH=none Change-Id: I207e7075e8ac905efd5f201dd54658dedf531568 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-12-02drivers/analogix/anx7625: Fix edid_read()Yu-Ping Wu
The current implementations of edid_read() and segments_edid_read() have a few problems: 1. The type of variable `c` is incorrect, not matching the return type of sp_tx_aux_rd(). In addition, the meaning of `c` is unknown. 2. It is pointless to do `cnt++` when sp_tx_aux_rd() fails. 3. These two functions ignore the return value of anx7625_reg_block_read(). 4. In segments_edid_read(), anx7625_reg_write() might return a positive value on failure. Fix all of the 4 issues, and modify the code to be closer to kernel 5.10's implementation (drivers/gpu/drm/bridge/analogix/anx7625.c). Note that, however, unlike in kernel, anx7625_reg_block_read() here doesn't return the number of bytes. On success, 0 is returned instead. In addition, following coreboot's convention, always return negative error codes. In particular, change the return value to -1 for edid_read() and segments_edid_read() on failure. BUG=b:207055969 TEST=emerge-asurada coreboot BRANCH=none Change-Id: Ife9d7d97df2926b4581ba519a152c9efed8cd969 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-12-01drivers/gfx/generic: Add optional _HID for gfx devicesTim Wawrzynczak
Some boards may want to use a _HID instead of an _ADR to locate a graphics device. This patch provides that option in the devicetree. BUG=b:206850071 TEST=Add `hid` entry in devicetree, dump SSDT and see _HID instead of _ADR Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I32be4abf5c60be1f94aabaa2e9c734215c4e291e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-27drivers/smmstore: Remove SMMSTORE_IN_CBFSJulius Werner
The SMMSTORE_IN_CBFS option was just meant as a workaround for an attempt to backport SMMSTORE into older Chromebooks that never actually happened. All current and future users of coreboot should be using SMMSTORE in an FMAP region. The APIs needed for SMMSTORE_IN_CBFS clash with the CBFS rdev isolation needed for CBFS_VERIFICATION, so let's just get rid of it. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia0604a4ffd20b46774631d585925311b65d5a0e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59680 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-26dptf: Add support for one more temperature sensorTim Wawrzynczak
Some boards may use more than 4 temperature sensors for DPTF thermal control, so this patch adds support for one more temperature sensor. BUG=b:207585491 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-24drivers/i2c/tpm: Fix blank default statementKarthikeyan Ramasubramanian
CB:59479 introduced a blank default statement. This is treated as an error or warning on some older toolchains. Add a break statement on default case. BUG=None TEST=Build the Guybrush mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3d034cfebc8b8ae7d7024d41b4b2207cdeb083e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-23drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750Ben Chuang
The device is a PCIe Gen1 to SD 3.0 card reader controller to be used in the Chromebook. The datasheet name is GL9750S and the revision is 01. The patch disables ASPM L0s. BUG=b:206014046 TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22drivers/tpm: Add firmware-power-managed DSD propertyRob Barnes
Introduce firmware-power-managed DSD ACPI property for TPM devices. This property can be checked by the kernel TPM driver to override how the TPM power states are managed. This is a tri-state flag, true, false, or unset. So an enum used to keep the flag is unset by default. When firmware-power-managed is true, the kernel driver will not send a shutdown during s2idle/s0i3 suspend. BUG=b:200578885 BRANCH=None TEST=TPM shutdown is triggered on s0ix suspend on guybrush with patched kernel Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-22drivers/uart: Let DRIVERS_UART_8250IO also depend on PPC64Krystian Hebel
There seems to be no operational differences between x86 and PPC64 for UART 8250. Port number is the same. References: * https://github.com/open-power/docs/issues/25 * https://github.com/3mdeb/openpower-coreboot-docs/blob/main/devnotes/porting.md#enabling-console Tested on Talos II (https://raptorcs.com/TALOSII/). Works in QEMU as well (actually in QEMU it works even without this change somehow). Change-Id: Ib06001076b8eaa577a8d2159afea20afb610687d Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-19driver/intel/mipi_camera: Add support for _DSC fieldVarshit B Pandya
The _DSC (Device State for Configuration) object evaluates to an integer may be used to tell Linux the highest allowed D state for a device during probe. The support for _DSC requires support from the kernel bus type if the bus driver normally sets the device in D0 state for probe. The D states and thus also the allowed values for _DSC are listed below. Number State Description 0 D0 Device fully powered on 1 D1 2 D2 3 D3hot 4 D3cold Off More details can be found here https://lkml.org/lkml/2021/10/25/397 BUG=none BRANCH=none TEST=Add corresponding field in brya, boot and dump SSDT to check if _DSC field is as per expectation. Name (_ADR, Zero) // _ADR: Address Name (_HID, "OVTI8856") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_DSC, 0, NotSerialized) { Return (0x04) } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18drivers/fsp: Rewrite post code hex values in lowercaseSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I65a83fcd69296f13c63329701ba9ce53f7cc2cb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-17drivers/siemens/nc_fpga: Add POST code over PCIWerner Zeh
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which was connected via the LPC bus to the host CPU. On recent x86 generations the LPC bus was replaced with eSPI and not all Siemens boards have the eSPI routed to the NC FPGA. In order to have POST codes visible on those boards the display is accessible via PCI in addition. This patch adds the feature of sending the POST codes to the NC FPGA via a PCI mapped register. Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-15drivers/wifi/generic: fix package_size to align with WLAN driverMatt Chen
Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3 no matter what the revision is for EWRD. It will pass the WLAN driver check then to retrieve the data properly. BUG=b:204414616 TEST= tested on brya with DRTU tool to verify if SAR table is read properly or not. Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8 Signed-off-by: Matt Chen <matt.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12drivers/amd/agesa/romstage.c: Remove lapic_id checkArthur Heymans
The APs don't execute this codepath but ap_romstage_main(). Change-Id: If884001bc8c5363efbbf00422a9a700896318f7b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-08drivers/intel/fsp2_0: Add preload_fspm and preload_fspsRaul E Rangel
In the non-XIP world, FSP is normally memmapped and then decompressed. The AMD SPI DMA controller can actually read faster than mmap. So by reading the contents into a buffer and then decompressing we reduce boot time. BUG=b:179699789 TEST=Boot guybrush and see 30ms reduction in boot time Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08drivers/intel/fsp2_0: Add FSP_ALIGNMENT_FSP_X optionRaul E Rangel
This option will allow setting the FSP alignment in CBFS. BUG=b:179699789 TEST=Boot with and without the option set and verify -a option was passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08drivers/intel/fsp2_0: Allow FSP-M to be relocatedRaul E Rangel
AMD platforms pass in the base address to cbfs tool: fspm.bin-options: -b $(CONFIG_FSP_M_ADDR) There is no technical reason not to allow FSP-M to be relocated when !XIP. By allowing this, we no longer need to pass in the base address into cbfstool when adding fspm.bin. This enables passing in the `--alignment` argument to cbfs tool instead. cbfstool currently has a check that prevents both `-b` and `-a` from being passed in. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-08drivers/elog/elog: Add timestamps to elog_initRaul E Rangel
elog init requires doing a lot of SPI transactions. This change makes it clear how long we spend initializing elog. BUG=b:179699789 TEST=Boot guybrush and see elog init timestamps 114:started elog init 3,029,116 (88) 115:finished elog init 3,071,281 (42,165) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/58957 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04drivers: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: Ia9a4b62c857f7362d67aee4f9de3bb2da1838394 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02google/trogdor: Add backlight support for Parade ps8640xuxinxiong
Add backlight support in ps8640 through the AUX channel using eDP DPCD registers. BUG=b:202966352 BRANCH=trogdor TEST=verified firmware screen works on homestar rev4 Change-Id: Ief1bf56c89c8215427dcbddfc67e8bcd4c3607d2 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-30drivers/intel/fsp2_0: Check return type against CB_SUCCESSSubrata Banik
commit 6af980a2a (drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially) drops CB_SUCCESS check for mp_run_on_all_aps function hence, this changes bring back the required return type against CB_SUCCESS. Change-Id: I9fc81e6a7eebbf0072ea2acb36b3c33539b517a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run seriallySubrata Banik
As per MP service specification, EDK2 is allowed to specify the mode in which a 'func' routine should be executed on APs. `SingleThread` sets to 'true' meaning to execute the function one by one (serially) or sets to 'false' meaning to execute the function simultaneously. MP service API `StartupAllAPs` was designed to pass such options as part of function argument. But another MP service API `StartupAllCPUs` doesn't specify any such requirement. Running the `func` simultaneously on APs results in a coherency issue (hang while executing `func`) due to lack of acquiring a spin lock while accessing common data structure in multiprocessor environment. BUG=b:199246420 Change-Id: Ia95d11408f663212fd40daa9fd9b0881a07f1ce7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-28drivers/net/r8168.c: Guard against generating power resourceArthur Heymans
Not all platforms need to generate power resources, but the code does not get optimized out at build time because the devicetree gets compiled into a linked list. As this code pulls in some heavy ACPI dependencies that is even implemented with weak empty function it makes sense to optimize out this code using a Kconfig constant. This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l. Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-25drivers/pc80/tpm: Use '%u' as printf formatter for unsigned variablesWerner Zeh
Use %u instead of %d for printing unsigned variables. Change-Id: I0f4bf7b80dfbde0802af8ad96fd553cb75d60e6e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25drivers/pc80/tpm: Use stopwatch for timeout-loopsWerner Zeh
There are manual timeout-loops which use a fixed value and udelay(). In all cases there is a debug printk() inside this loop which, when enabled, takes way longer than the counted microsecond delay. This leads to the result that e.g. a 1 second delay takes nearly an eternity if the debug messages are enabled due to the longer function execution time. This patch uses the stopwatch scheme for the timeout-loops which still makes sure that the timeout period is maintained while it takes longer function calls like printk() into account. In order to keep the minimum delay between two register accesses on the TPM keep the udelay(1)-call. TEST=Enable TPM debug messages on a board where the TPM hits a timeout by failure and make sure that the debug messages occur in the log just in the timeout period. It still works as expected if the debug messages are disabled. Change-Id: I8fd261c9d60a9a60509c847dbc4983bc05f41d48 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-17drivers/generic/ioapic: Drop enable_virtual_wireKyösti Mälkki
All boards with DRIVERS_GENERIC_IOAPIC select it. Presumably the related configuration of routing IRQ0 when IOAPIC is enabled should be always done to provide i8259 legacy compatibility for payloads. Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-17drivers/emulation/qemu: Add missing include for MMIONico Huber
Change-Id: Ie3c820e2e20f8f71908319e89e49e5d66f58adc9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-13drivers/pc80/tpm: Fix wrong debug messageWerner Zeh
There is the wrong register offset printed in the debug log when the data register is written: 'lpc_tpm: Write reg 0x18 with 0xnn' should be 'lpc_tpm: Write reg 0x24 with 0xnn' for data FIFO access. This can be confusing when searching for issues with the help of the TPM debug messages since the code itself is correct. Fix this error. Change-Id: Ic28ee5a07146e804574b887ea05c62e7e88e9078 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-10-11drivers/intel/dptf: return package with valueSumeet Pawnikar
Return the package with a value for the dptf user space service. This is required in write tpch method for pch device under dptf driver. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11drivers/intel/dptf: Add support for PCH methodsSumeet Pawnikar
Add various methods support for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-05drivers/intel/fsp2_0: don't force-use `python2`Michael Niewöhner
Some distributions (e.g. NixOS, Debian) are actively working on getting rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and Python 3 as of upstream commit 0bc2b07, use whatever version is present by utilizing `python`. Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-10-05src/acpi to src/lib: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05driver/intel/pmc_mux/conn: Add type-c port info to cbmemNick Vaccaro
This change adds type-c port information for USB type-c ports to cbmem. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.hNick Vaccaro
Move the locally declared typec_orientation enum from chip.h to coreboot_tables.h. Change enum typec_orientation name to type_c_orientation for consistency with contents of coreboot_tables.h. Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE. BUG=b:149830546 TEST="emerge-volteer coreboot" and make sure it compiles successfully. Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-01drivers/gic: Remove unnecessary codeJulius Werner
On AArch64 platforms, GIC initialization is generally the job of Trusted Firmware and shouldn't be necessary in coreboot. Only the ancient T210 platform (which was started before we had decided on using Trusted Firmware) calls this code, and even there they have a comment wondering "do we still need this?". I'm just gonna assume (without testing because that board is ancient and I'm lazy) that they don't, and that the TF GIC initialization[1] is sufficient here. Remove this obsolete driver. [1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-24drivers/genesyslogic/gl9755: Disable ASPM L0s supportBen Chuang
When the entry delay of L0s is less than the entry delay of L1, GL9755 will enter L0s state first. When it exits from L0s state, the time of L1 entry will be reset. Therefore, the conditions for entering L1 state cannot be met. In order to enter L1 state, L0s needs to be disabled. BUG=b:195611000 TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21drivers/gfx/generic: Drop unused find_gfx_devFurquan Shaikh
This change drops the function `find_gfx_dev()` as it is unused now. Change-Id: Ie42707bd45348dc7485ca0ca12ebff2994897e6b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20driver/i2c/max98390: Add vmon_slot_no/imon_slot_no propertyWisley Chen
Add two properties (maxim, vmon-slot-no/maxim, imon-slot-no) in maxim9839 driver. This is I/V source destination definition that from below properties . maxim,vmon-slot-no => PCM_IVADC_V_DEST maxim,imon-slot-no => PCM_IVADC_I_DEST BUG=b:197076844 TEST=build and check SSDT Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Idb24d19c7cfea559bf6d53f401d66cadb8b3acc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-17drivers/ipmi/ocp: add missing commonlib/bsd/cb_err.h includeFelix Held
This include provides the definition of enum cb_err. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfee720de920377796e3fd64cb47514b8cb08c34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17drivers/gic/gic: add missing arch/cpu.h includeFelix Held
smp_processor_id is defined in src/arch/arm64/include/armv8/arch/cpu.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b610189bf439774cb900f74559dee314cbc5854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-16mb/google/trogdor: Add mipi panel for wormdinglerZanxi Chen
Add mipi panel support for wormdingler - Add the following panel for wormdingler: INX P110ZZD-DF0 BOE TV110C9M-LL0 - Use panel_id to distinguish which mipi panel to use. - Setup panel orientation BUG=b:195898400,b:198548221 BRANCH=none TEST=emerge-strongbad coreboot Change-Id: I8cd28e024ecbfdcd473bc39efb529eb4aca1b5d0 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-09-16drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling methodSubrata Banik
FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-14driver/i2c/max98390: add dsm_param_nameWisley Chen
Maxim driver look for "maxim,dsm_param_name" to load dsm parameter file. dsm param file name consist of {dsm_param_file_name} filled in devicetree, {MAINBOARD_VENDOR} and {MAINBOARD_PART_NUMBER}. => {dsm_param_file_name}_{MAINBOARD_VENDOR}_{MAINBOARD_PART_NUMBER}.bin BUG=b:197076844 TEST=build, and check ssdt Change-Id: I006572d6a6ea55298374c688dfd9d877835da82d Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-13SMBIOS: Allow skipping default SMBIOS generationAngel Pons
The call to the `get_smbios_data` device operation is followed by calls to unconditional default functions, which lacks flexibility. Instead, have devices that implement `get_smbios_data` call these default functions as needed. Most `get_smbios_data` implementations are in mainboard code, and are bound to the root device. The default functions only operate with PCI devices because of the `dev->path.type != DEVICE_PATH_PCI` checks, so calling these functions for non-PCI devices is unnecessary. QEMU also implements `get_smbios_data` but binds it to the domain device, which isn't PCI either. Change-Id: Iefbf072b1203d04a98c9d26a30f22cfebe769eb4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13spi-generic: Print an error when trying to use a non-existent busJulius Werner
...because I just spent hours chasing a refactoring bug that would have been way more obvious with a little more error transparency in here. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3354ff0370ae79f05e5c37d292ac16d446898606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-13drivers/analogix/anx7625: prevent video clock jitter on IVO panelsXin Ji
The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz), anx7625 defines K ratio for matching MIPI input video clock and DP output video clock. A bigger k value can match a bigger video data variation. IVO panel has smaller variation than DP CTS spec, so decrease k value to 0x3b. BUG=b:194659777 BRANCH=none TEST=Display is normal on Asurada Change-Id: If3a09811999babda45e9a9a559dd447920109204 Signed-off-by: Xin Ji <xji@analogixsemi.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-11mipi: Make panel init callback work directly on DSI transaction typesJulius Werner
Our MIPI panel initialization framework differentiates between DCS and GENERIC commands, but the exact interpretation of those terms is left to the platform drivers. In practice, the MIPI DSI transaction codes for these are standardized and platforms always need to do the same operation of combining the command length and transfer type into a correct DSI protocol code. This patch factors out the various platform-specific DSI protocol definitions into a single global one and moves the transaction type calculation into the common panel framework. The Qualcomm SC7180 implementation which previously only supported DCS commands is enhanced to (hopefully? untested for now...) also support GENERIC commands. While we're rewriting that whole section also fix some other issues about how exactly long and short commands need to be passed to that hardware which we identified in the meantime. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-10elog: move MAX_EVENT_SIZE to commonlib/bsd/includeRicardo Quesada
Moves MAX_EVENT_SIZE to commonlib/bsd/include, and renames it ELOG_MAX_EVENT_SIZE to give it an "scoped" name. The moving is needed because this defined will be used from util/cbfstool (see next CL in the chain). BUG=b:172210863 TEST=compiles Ok Change-Id: I86b06d257dda5b325a8478a044045b2a63fb1a84 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-09wifi: Update deny list entry size to uint16_tSugnan Prabhu S
As per the connectivity document deny list entry size should be uint16 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf Fixes: cc50770cd0("wifi: Add support for wifi time average SAR config") Change-Id: I045c21350cf4c2266df108eede6350d090322ba0 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09drivers/intel/fsp2_0: Retype loop variable from int to uint32_tAngel Pons
Retype loop variable `i` to `uint32_t` for consistency with the types of the `number_of_phases` and `phase_index` struct fields and the parameter of the `platform_fsp_multi_phase_init_cb()` function. Change-Id: I82916f33c2dc5dab6a31111c9acba2a18a5cfb0b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57491 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06drivers/intel/fsp2_0: add warning when ADD_FSP_BINARIES isn't selectedFelix Held
Platforms that rely on the FSP for parts of the hardware initialization likely won't boot successfully when no FSP binaries are added during the build, so print a warning at the end of the build in this case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Suggested-by: Martin Roth <martinroth@google.com> Change-Id: I6efc184ecc4059818474937fd31574f703c9bdc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-05drivers/intel/dptf: Add new thermal control mechanism for pch deviceSumeet Pawnikar
Add new thermal control mechanism for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05drivers/intel/fsp/Makefile: error out when FSP files aren't specifiedFelix Held
Error out when the FSP binaries that are supposed to be added aren't specified. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ie5f2d75d066f0b4e491e9c8420b7a0cbd4ba9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-03drivers/intel/fsp2_0/Makefile: add condition for FSP-T CBFS fileFelix Held
Make adding the FSP-T file to CBFS depend on both ADD_FSP_BINARIES and FSP_CAR Kconfig options being set. The FSP_T_FILE Kconfig option depends on both, so also check if both are selected in the Makefile where it tries to add the FSP-T to the CBFS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Id347336f2751c6d871f31d89c30a1222037c2d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-02wifi: Add support for DSM methods for intel wifi cardSugnan Prabhu S
Add support for DSM methods as per the connectivity document 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:191720858 TEST=Check the generated SSDT tables for DSM methods Change-Id: Ie154edf188531fe6c260274edaa694cf3b3605d3 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for wifi time average SAR configSugnan Prabhu S
Add support for the WTAS ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the WTAS related configuration values and verified that the SSDT has the WTAS ACPI table. Change-Id: I42cf3cba7974e6db0e05de30846ef103a15fd584 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for per-platform antenna gainSugnan Prabhu S
Add support for the PPAG ACPI BIOS configuration table as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf BUG=b:193665559 TEST=Generated SAR file with the PPAG related configuration values and verified that the SSDT has the PPAG ACPI table. Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02wifi: Add support for new revisions of SAR table entriesSugnan Prabhu S
Existing SAR infrastructure supports only revision 0 of the SAR tables. This patch modifies it to extend support for intel wifi 6 and wifi 6e configurations as per the connectivity document: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf The SAR table and WGDS configuration block sizes were static in the legacy SAR file format. Following is the format of the new binary file. +------------------------------------------------------------+ | Field | Size | Description | +------------------------------------------------------------+ | Marker | 4 bytes | "$SAR" | +------------------------------------------------------------+ | Version | 1 byte | Current version = 1 | +------------------------------------------------------------+ | SAR table | 2 bytes | Offset of SAR table from start of | | offset | | the header | +------------------------------------------------------------+ | WGDS | 2 bytes | Offset of WGDS table from start of | | offset | | the header | +------------------------------------------------------------+ | Data | n bytes | Data for the different tables | +------------------------------------------------------------+ This change supports both the legacy and the new format of SAR file BUG=b:193665559 TEST=Checked the SSDT entries for WRDS, EWRD and WGDS with different binaries generated by setting different versions in the config.star Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-02drivers/mipi: Make orientation a property of the mainboard, not panelJulius Werner
It doesn't make sense to store the orientation field directly in the panel information structure, which is supposed to be reuseable between different boards. The thing that determines orientation is how that panel is built into the board in question, which only the board itself can know. The same portrait panel could be rotated left to be used as landscape in one board and rotated right to be used as landscape in another. This patch moves the orientation field out of the panel structure back into the mainboards to reflect this. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2b716aa4dae036515730c12961fdd8a9ac34753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57324 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01drivers/intel/fsp1_1/romstage.c: Remove MCU updateArthur Heymans
On Braswell this is done in the bootblock before C code is executed. Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-08-26elog: Define constant for RW region nameRicardo Quesada
This CL indroduces the ELOG_RW_REGION_NAME. This constant replaced the hardcoded "RW_ELOG" value. This constant will be used also by elogtool (see CL in the commit chain). BUG=b:172210863 Change-Id: Ie8d31204e65fd67d52b0f8ced7b8c1ffdcf5b539 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56986 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26elog: move functionality to commonlib/bsdRicardo Quesada
This commit moves some drivers/elog/ functionality to commonlib/bsd since they will be called from util/cbfstool/. In particular: * elog_fill_timestamp(), elog_update_checksum(), elog_checksum_event() were moved to commonlib/bsd/elog * elog_fill_timestamp() receives the time parameters and updates the event based on the "time" arguments. The original elog_*() functions were written by Duncan Laurie (see CB:1311) and he gave permission to re-license the code to BSD. BUG=b:172210863 Change-Id: I67d5ad6e7c4d486b3d4ebb25be77998173cee5a9 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26drivers/intel/fsp2_0: rename soc_validate_fsp_versionFelix Held
Rename soc_validate_fsp_version to soc_validate_fspm_header, since it can not only be used to check the version info in the FSP-M binary's header, but also to check every other field in the binary's header. This is a preparation for a follow-up patch that implements this function to check the FSP-M binary's size. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ifadcfd1869bea0774dc17b69c5d1e1c241a45de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-26device/mipi: Move to drivers/mipiJulius Werner
Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-23include/bcd: move bcd code to commonlib/bsd/includeRicardo Quesada
Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/ Also, the license is changed from GPL to BSD. This is because it is needed from "utils" (see CL in the chain). For reference bin2bcd() & bcd2bin() are very simple functions. There are already BSD implementations, like these ones (just to name a few): https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67 http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c BUG=b:172210863 TEST=make (everything compiled Ok). Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/common: Add TGL-H PCI IDsJeremy Soller
Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-12drivers/generic/alc1015: Add HID to support alc1019Eric Lai
ALC1019 will use the ACPI compatible and share the same driver with ALC1015. Add HID to support more compatible ICs. BUG=b:195891240 TEST=ALC1019P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3e98297f3a39048b24d61e61ca95c60cd2037eb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-09drivers/uart/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most UARTs that do have wake capabilities support wake from D3hot rather than D3cold. BUG=b:187228954 TEST=compile Change-Id: I24d6d0e81d980fc9c910d8f47f557c88990b6400 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/spi/acpi: Update _S0W return value to D3hotTim Wawrzynczak
In order to support wake from D3cold, most devices require extra circuitry and possibly out-of-band communications to the host. Therefore, assume that most SPI peripherals that do have wake capabilities support wake from D3hot rather than D3cold. This also allows coreboot to expose a power resource to perform power sequencing for a SPI peripheral that is intended to retain power in S3/S0ix. If support for a device with d3cold wake support is needed, it could be added in later as an option. BUG=b:187228954 TEST=compile Change-Id: I1d739b49c1a43007eb0199fe39b3b7d7375e6577 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-09drivers/i2c/da7219: Update _S0W to D3hotTim Wawrzynczak
The DA7219 does not support wake from D3cold, therefore update the return value of _S0W from D3cold to D3hot. BUG=b:187228954 TEST=compile Change-Id: If03f83bb00ec90a2a6646d2c99d8bcc7e5533ac2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-04Move elog_internal.h to commonlib/bsd/includeRicardo Quesada
Move elog_internal.h to commonlib/bsd/include/bsd/. And rename it from elog_internal.h to elog.h. Since this file will be included from util/ it also converts the "uNN" types into "uintNN_t" types. The two defines that are not used by util/ are moved to drivers/elog/elog.c, the only file that includes them. Move also the function elog_verify_header() from drivers/elog/, to commonlib/bsd/elog.c since this function will be called from util/ as well. The rationale behind moving elog's defines & structs to commonlib/bsd/include is to make them available to util/ tools and/or payloads (should it be needed in the future). The files that are being relicensed to BSD were coded by Duncan Laurie, and he is Ok with the relicense. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ia1aefea705ddd417a1d9e978bb18ab6d9a60cad6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-24src/drivers/intel/fsp2_0: allow larger FSP 2.0 headerNikolai Vyssotski
This is in preparation for migrating EDK2 to more recent version(s). In EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0 header (FspMultiPhaseSiInitEntryOffset). This increases the length of the header from 72 to 76. Instead of checking for exact length check reported header length against known minimum length for a given FSP version. BUG=b:180186886 TEST=build/boot with both header flavors Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23drivers/intel/i210: Set PCI bus master bit only if allowedWerner Zeh
Set the bus master bit only if the global Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE is enabled. For now the bus master bit is needed for i210 because of some old OS drivers that do not set it and won't work properly without it. Change-Id: I6f727e7f513f4320740fbf49e741cea86edb3247 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-23drivers/pc80/rtc: Make use of alt-century byte configurableNico Huber
This legacy alt-century byte sits amidst CMOS and conflicts many option tables. It usually has no meaning to the hardware and needs to be main- tained manually. Let's disable its usage by default if the CMOS option table is enabled. Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-22drivers/spi: Increase sector number to 14 for Winbond W25Q512NW-IMShaik Sajida Bhanu
Update proper number of sectors info for winbond W25Q512NW-IM chip BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: I12a22321bb9180e32cd47faa6ac3960ba5b2dfb8 Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56038 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17drivers/intel/gma: Support IGD Opregion 2.1Meera Ravindranath
List of changes: 1. Define new configs for Opregion versions. 2. Assign RVDA to relative address of the Opregion buffer in case of opregion 2.1+. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-15drivers: spi_flash: Add Fast Read Dual I/O supportJulius Werner
The Fast Read Dual Output and Fast Read Dual I/O commands are practically identical, the only difference being how the read address is transferred (saving a whooping 2 bytes which is totally irrelevant for the amounts of data coreboot tends to read). We originally implemented Fast Read Dual Output since it's the older command and some older Winbond chips only supported that one... but it seems that some older Macronix parts for whatever reason chose to only support Fast Read Dual I/O instead. So in order to make this work for as many parts as possible, I guess we'll have to implement both. (Also, the Macronix device ID situation is utter madness with different chips with different capabilities often having the same ID, so we basically have to make a best-effort guess to strike a trade-off between fast speeds and best chance at supporting all chips. If this turns out to be a problem later, we may have to add Kconfig overrides for this or resort to SFDP parsing, although that would defeat the whole point of trying to be fast.) BUG=b:193486682 TEST=Booted CoachZ (with Dual I/O) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-15drivers/intel/gma: Restructure Opregion version info codeMeera Ravindranath
Define a structure for opregion version information to align with spec/kernel. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-14drivers/usb/acpi: Avoid dereferencing maybe-NULL pointerAngel Pons
Do not dereference a pointer before checking whether it is NULL. Change-Id: Icbe9ae99d91fd587d8e56cf3a0dcb59834ee6d07 Found-by: Coverity CID 1458232 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56266 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14drivers/usb/acpi: Replace unneeded `memcpy` useAngel Pons
A regular assignment works just as well and also allows type-checking. It also avoids a common mistake where `sizeof` is applied to a pointer to obtain the size of the data it points to, without dereferencing it. Found-by: Coverity CID 1458231 Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56265 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14src: Use initial_lapicid() instead of open coding itArthur Heymans
Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before. Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"Felix Held
This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was originally introduced as a workaround for the bug that the Linux kernel doesn't know what to do with type 16 memory region in the e820 table where CBMEM resides and disallowed accessing it. After depthcharge was patched to mark the type 16 region as a normal reserved region, the Linux kernel now can access the BERT region and print BERT errors. When SeaBIOS was used as payload it already marked the memory region correctly, so it already worked in that case. After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the usage of the BERT memory region reserved by the FSP driver by the AMD Picasso and Cezanne SoCs and made them use CBMEM for the BERT region, no other SoC code uses this functionality. The Intel Alderlake and Tigerlake SoCs put the BERT region in CBMEM and never used this reserved memory region and the change for the Intel server CPU to use this was abandoned and never landed in upstream coreboot. AMD Stoneyridge is the only other SoC/chipset that selects ACPI_BERT, but since it doesn't select or use the FSP driver, it also won't be affected by this change. TEST=Behavior of the BERT code doesn't change on Mandolin Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12drivers/intel/usb4/retimer: remove redundant structure member group(PLD)Maulik V Vaghela
Currently, we get PLD information from USB port structure itself, so devicetree does not need to fill PLD structure anymore. Thus remove obsolete variable. Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/intel/usb4/retimer: Update code to assign correct port numberMaulik V Vaghela
Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Update the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. Get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/usb/acpi: Create function to get PLD informationMaulik V Vaghela
Create a separate function to get PLD information from USB device. This is helpful in retimer driver where we can attach same USB port information to retimer instance and we can avoid duplication of information. BUG=None BRANCH=None TEST=Check if code compiles and function returns correct value Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 03:51:07 +0000