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1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove unused function declaration spi_fram_probe_ramtron.
BUG=b:38330715
Change-Id: I05e6c5c2b97d6c8a726c0e443ad855f9bcb703f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19706
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of storing spi flash device structure in spi flash driver, use
boot_device_spi_flash callback to obtain pointer to boot device spi
flash structure.
BUG=b:38330715
Change-Id: Idd50b7644d1a4be8b62d38cc9239feae2215103c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This allows callers to retrieve handle to the boot device spi_flash structure.
BUG=b:38330715
Change-Id: I1c07327115e0449cbd84d163218da76a6fa2cea0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There's no users of vbe_mode_info_valid() aside from the local
compilation units. Remove the declaration and make the function
static to the current global implementers.
Change-Id: I4872ac6ad15ba6a86bba69d51a8348b9921c152d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For some reason the "interface" for adding framebuffer information
is sitting in src/include/vbe.h while also guarding the call to
fill_lb_framebuffer() with vbe_mode_info_valid() along with some
macro if CONFIG_* for good measure.
Move the fill_lb_framebuffer() declaration to coreboot_tables.h and
provide a comment about how it should be used. Also, now that
there's no need for the notion of a global vbe_mode_info_valid()
remove it from the conditional call path of fill_lb_framebuffer().
Change-Id: Ib3ade6314624091ae70424664527a02b279d0c9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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We have several different UART implementations of which three support a
timeout when receiving characters. In all of these three implementations
there is a bug where when the timeout is hit the last received character
will be returned instead of the needed 0.
The problem is that the timeout variable i is decremented after it has
been checked in the while-loop. That leads to the fact that when the
while-loop is aborted due to a timeout i will contain 0xffffffff and not
0. Thus in turn will fool the following if-statement leading to wrong
return value to the caller in this case. Therefore the caller will see a
received character event if there is none.
Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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And don't link it. It's for ROMCC.
To make code happy that uses the ROMCC interface read_option(),
read_option_lowlevel() is ported to mc146818rtc.c along with
a message to use get_option() instead.
Change-Id: I54ea08de034766c8140b320075d36d5e811582fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Delay for a while after the switch operations to let the card recover.
TEST=Build and run on Galileo Gen2
Change-Id: I938e227a142e43ed6afda80d56af90df0bae1b05
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This driver enables the usage of the external RTC chip RX6110 SA
(http://www5.epsondevice.com/en/products/i2c/rx6110sab.html) which is
connected to the I2C bus. The I2C address of this device is fixed. One
can change parameters in the device tree so that the used setup can be
adapted to match the configuration of the device on the mainboard.
Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Fix bug detected by coverity to handle the zero capacity case. Specific
changes:
* Reduce loop count by one to handle zero capacity case
* Use structure instead of dual arrays
* Move structures into display_capacity routine
Coverity Issues:
* 1374931
* 1374932
* 1374933
* 1374934
TEST=Build and run on Galileo Gen2
Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove unused field in generic SD/MMC controller data structure.
TEST=Build and run on Galileo Gen2
Change-Id: I7169dca07509a6f2513d62b593742daf764010b2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Provide a failing get_wifi_sar_limits() to allow SAR Kconfig
options to be selected without relying on CHROMEOS which currently
has the only code to provide SAR data.
Change-Id: I1288871769014f4c4168da00952a1c563015de33
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
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tis_close() must be called after tis_open() otherwise the locked
locality isn't released and the sessions hangs.
Tested=PC Engines APU2
Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/19535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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device is run before drivers to generate .config and the first default
takes precedence so this override achieves nothing.
Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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On Chrome OS systems a memory setting change is needed to be deployed
without updating the FSP blob proper. Under such conditions one needs
to trigger retrain of the memory. For ease of use provide an option,
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC
and mainboard memory setting version number into the FSP version
passed to the platform. The lower 8 bits of the FSP version are the
build number which in practice is normally 0. Use those 8 bits to
include the SoC and mainboard memory settings version. When FSP,
SoC, or mainboard memory setting number is bumped a retrain will be
triggered.
BUG=b:37687843
Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19452
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The SD/MMC support is broken into several pieces. There are three main
data structures:
* sdhci_ctrlr - This is SDHCI controller specific and defined in
include/device/sdhci.h
* sd_mmc_ctrlr - This contains generic controller management data and
defined in include/device/sd_mmc_ctrlr.h
* storage_media - This contains the flash storage device management data
and is defined in include/device/storage.h
The SD/MMC driver consists of several components:
* SDHCI controller code
* bouncebuf.c
* bouncebuf.h
* pci_sdhci.c
* sdhci.c
* sdhci.h
* sdhci_adma.c
* sdhci_display.c
* Flash storage device support
* mmc.c
* mmc.h
* sd.c
* sd_mmc.c
* sd_mmc.h
* storage.c
* storage.h
* storage_erase.c
* storage_write.c
Kconfig values enable various portions of the controller and storage
drivers to be built to reduce the overall size of what is included in
the final image.
Full read/write/erase operations are provided for those platforms which
want to take advantage. It is also possible to build the driver to
perform initialization only. By default, this driver is not included in
any platform, platforms must specifically select DRIVERS_STORAGE to add
the SD/MMC support.
After this patch is reviewed and merged, there are some additional
patches:
* Common CAR storage area - Use a predefined region of CAR to pass data
structures between bootblock through to romstage. This allows early
stages to preform the SD/MMC device initialization and later stages
to use the SD/MMC device without further initialization. The example
code initializes the SD/MMC device in bootblock and uses the SD/MMC
device in romstage without further initialization.
* CBMEM ID - Add a CBMEM ID value for the data structures so that they
may be passed from romstage to ramstage and eventually the payload.
The example uses the SD/MMC device in ramstage without further
initialization.
* Move the SD/MMC driver into commonlib
* Have libpayload build the SD/MMC driver from commonlib. The intent
is to pass the controller state to libpayload so that the SD/MMC
device can be used without further initialization.
* On some platforms, have depthcharge use the commonlib SD/MMC driver
History:
Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot
and make the following changes:
* Removed #include "config.h" from mmc.c, allow the lint tests to pass.
* Move include files from drivers/storage into include/device.
* Rename mmc.h to storage.h.
* Add the Kconfig and Makefile and make edits to get the code to build.
* Add support to initialize a PCI controller.
* Fix formatting issues detected by checkpatch.
* Fix data flow issues detected by checkpatch.
* Add the missing voltage (MMC_VDD_35_36) into the voltage mask.
* Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*.
* Replace printf with sd_mmc_error.
* Add sdhc_debug, sdhc_trace and sd_error macros.
* Add Kconfig values to enable storage device debugging and tracing.
* Add tracing and debug support to the SDHCI driver.
* Allow SOC to override more controller features.
* Split out ADMA support.
* Move 1V8 support into SOC routine.
* Move HS400 support into SOC routine.
* Rework clock handling.
* Change all controller references to use ctrlr.
* Update the voltage handling.
* Update modes of operation.
* Move DMA fields into MmcCtrlr.
* Update bus width support.
* Change MMC_TIMING_* to BUS_TIMING_*.
* Rename MMC_MODE_ to DRVR_CAP.
* Move quirks into ctrlr->caps.
* Associate removeable with the controller.
* Statically allocate MmcMedia.
* Replace the SdhciHost structure with the MmcCtrlr structure.
* Split the code to support other SD/MMC controllers.
* Split out erase and write support.
* Update the code to be more consistent with the coreboot coding style.
* Only expose calling APIs.
* Divide up mmc.c into 4 modules: MMC, SD, storage card, common code.
* Update debug and error messages.
* Add partition support.
* Display clock frequencies once in MHz.
* Remove mmc_send_cmd, use ctrlr->send_cmd instead.
* Handle error from sd_send_op_cond.
* Allow mainboard to control delays around CMD 0.
* Support command logging.
* Mainboard may set delay after SD/MMC command.
* Display serial number with sd_mmc_trace.
* Remove cmd set parameter from mmc_switch.
* Display errors for timeout and comm errors.
* Add LED support.
* Move 64bit DMA flag into ctrlr->caps.
* Rework PIO transfer routine.
* Add HS200 bus tuning.
* Add support for HS400.
* Use same format for HS400, HS200 and HS52.
* Reduce storage_media structure size
* Add routine to update code pointers
* Add display of storage setup
* Display controller setup
TEST=Build and run on Reef and Galileo Gen2
Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19208
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The vendor.irq field was originally intended for use as the TPM 1.2
"command complete" interrupt. However, all actual coreboot tpm drivers
and hardware use the vendor.status method of checking command completion
instead, and this irq field is not used.
Let's just remove this unused functionality to simplify the code.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I994c5bfbd18124af9cb81d9684117af766ab0124
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19396
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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The Cr50 TPM uses an IRQ to provide a "status" signal used for hand-shaking
the reception of commands. Real IRQs are not supported in firmware,
however firmware can still poll interrupt status registers for the same
effect.
Commit 94cc485338a3 ("drivers/i2c/tpm/cr50: Support interrupts for status")
added support for the Cr50 driver on X86 platforms to use a KConfig file
to supply an IRQ which it would poll using acpi_get_gpe. If the IRQ is
not supplied, the Cr50 driver inserts a 20 ms wait.
Unfortunately this doesn't work so well when using the i2c connected Cr50
on ARM platforms. Luckily, a more generic implementation to allow a
mainboard to supply a Cr50 IRQ status polling function was solved for SPI
connected Cr50s by commit 19e3d335bddb ("drivers/spi/tpm: using tpm irq to
sync tpm transaction").
Let's refactor the i2c c50 driver to use this same approach, and change
eve and reef boards to make use of DRIVER_TPM_TIS_ACPI_INTERRUPT for
specifying the TPM flow control interrupt.
This essentially reverts these two commits:
48f708d199 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe
94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status
And ports this commit to i2c/tpm/cr50:
19e3d335bd drivers/spi/tpm: using tpm irq to sync tpm transaction
As a side effect the tpm_vendor_specific IRQ field goes back to its
original usage as the "TPM 1.2 command complete" interrupt, instead of
being repurposed to hold the flow control IRQ.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I004329eae1d8aabda51c46b8504bf210484782b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19363
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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MAINBOARD_HAS_SPI_TPM_CR50 describes a capability of the board and SPI_TPM
is only on if we actually want to compile in the TPM code. For example,
in src/drivers/i2c/tpm/Kconfig MAINBOARD_HAS_I2C_TPM_CR50 also doesn't
depend on SPI_TPM.
This problem manifests itself as the following build issue when building
with MAINBOARD_HAS_I2C_TPM_CR50 but without an explict "select TPM2":
src/Kconfig:296:error: recursive dependency detected!
src/Kconfig:296: symbol MAINBOARD_HAS_TPM2 is selected by MAINBOARD_HAS_TPM_CR50
src/Kconfig:408: symbol MAINBOARD_HAS_TPM_CR50 depends on MAINBOARD_HAS_SPI_TPM_CR50
src/drivers/spi/tpm/Kconfig:15: symbol MAINBOARD_HAS_SPI_TPM_CR50 depends on SPI_TPM
src/drivers/spi/tpm/Kconfig:1: symbol SPI_TPM depends on TPM2
src/Kconfig:396: symbol TPM2 is selected by MAINBOARD_HAS_TPM2
MAINBOARD_HAS_SPI_TPM_CR50 shouldn't depend on SPI_TPM.
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: I0cb3f6d3aa4159bad563a6a4b006d7f4825e04b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Suggested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19411
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use spi_setup_slave to fill up the spi_slave structure with
pointer to spi_ctrlr structure which can then be used to perform all
spi operations.
Change-Id: I2804ed1e85402426a654352e1ceaf0993546cd8b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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|
Depend on I2C_TPM to prevent showing the menu entry on systems
that do not have an I2C TPM installed.
Change-Id: I7cd647c9c7e9721eab96ab64b844a882f156ee68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19374
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Add SSDT generator for MIPI CSI camera to create ACPI objects
used by the Intel kernel drivers.
* SSDB: Sensor specific database for camera sensor.
* PWDB: Power database for all the camera devices.
* CAMD: ACPI object to specify the camera device type.
BUG=b:36580624
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated SSDT table
has the required entries.
Change-Id: Ief9e56d12b64081897613bf1c7abcdf915470b99
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/18967
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
We're already reading the RTC whenever we file an event, we might as
well print out the value at that time. Having a few RTC timestamps in
the firmware log makes it easier to correlate that part of the log to a
particular boot once we start having multiple boots in the log.
Change-Id: I750dd18aa2c43c95b8c1fbb8f404c1e3a77bec73
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. Move common TIS macros to include/tpm.h.
2. Use common TIS macros while referring to status and access registers.
3. Add a new function claim_locality to properly check for required
access bits and claim locality 0.
BUG=b:36873582
Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19213
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
There is only one user for spi_get_config i.e. SPI ACPI. Also, the
values provided by spi_get_config are constant for now. Thus, get rid
of the spi_get_config call and fill in these constant values in SPI
ACPI code itself. If there is a need in the future to change these,
appropriate device-tree configs can be added.
BUG=b:36873582
Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
In order to be able to use SPI TPM on x86, allow TPM_SPI to be used
with PC80_SYSTEM.
BUG=b:35583330
Change-Id: Ibe626a192d45cf2624368db42d369202a4003123
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19093
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. Use proper CAR semantics for global/static variables.
2. Use spi_* functions directly instead of using a global structure to
store pointers to those functions.
BUG=b:36873582
Change-Id: I1fc52ab797ef0cbd3793a387d68198efc5dde58c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19114
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=b:35647967
TEST=boot from bob
Change-Id: Ib64107b17fb6e93dbe626ce92f3bc9da8b84784e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452284
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19113
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=b:35775002
TEST=boot from bob
Change-Id: I6324f3c02da55a8527f085ba463cbb1f4fb5dc2e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452283
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
These files are required to support recovery MRC cache hash
save/restore in romtage/ramstage.
BUG=b:35583330
Change-Id: Idd0a4ee1c5f8f861caf40d841053b83a9d7aaef8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19092
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The tis.c module is needlessly copying data to/from a 1260 byte
buffer on the stack. Each device's transport implementation (cr50.c
or tpm.c) maintains its own buffer, if needed, for framing purposes.
Therefore, remove the duplicated buffer.
BUG=b:36598499
Change-Id: I478fb57cb65509b5d74bdd871f1a231f8080bc2f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19061
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
The 'ordinal' variable is not used. Remove it.
BUG=b:36598499
Change-Id: I015a6633c0951980658b3c879e48bc84d604d62e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19060
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
There are unused structures/types in the tpm.h header file.
Remove them.
BUG=b:36598499
Change-Id: Iddc147640dcec70e80791846eb46298de1070672
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19059
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
The spi tis_sendrecv() implementation was always returning success
for all transactions. Correct this by returning -1 on error when
tpm2_process_command() returns 0 since that's its current failure
return code.
BUG=b:36598499
Change-Id: I8bfb5a09198ae4c293330e770271773a185d5061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19058
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
The tpm_info object is a global, but its symbol does not need to
be exposed to the world as its only used within tpm.c.
BUG=b:36598499
Change-Id: Idded3dad8d0d1c3535bddfb359009210d3439703
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
In the case of start_transaction() failing the chip select is never
deasserted. Correct that by deasserting the chip select when
start_transaction() fails.
BUG=b:36598499
Change-Id: I2c5200085eb357259edab39c1a0fa7b1d81ba7b2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19056
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Move header and delete duplicates.
Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18903
Tested-by: build bot (Jenkins)
Tested-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
It's confusing to have these Kconfig symbols for non-Intel boards.
Change-Id: I4903c816258e5d2b8ed8704295b777aee175e8bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18795
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are
linked directly into the bootblock or the romstage. However, they're
still compiled with a separate "libverstage" source file class, linked
into an intermediate library and then linked into the final destination
stage.
There is no obvious benefit to doing it this way and it's unclear why it
was chosen in the first place... there are, however, obvious
disadvantages: it can result in code that is used by both libverstage
and the host stage to occur twice in the output binary. It also means
that libverstage files have their separate compiler flags that are not
necessarily aligned with the host stage, which can lead to weird effects
like <rules.h> macros not being set the way you would expect. In fact,
VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86
because their libverstage code that gets compiled into the romstage sets
ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to
run pre-migration.
This patch resolves these problems by removing the separate library.
There is no more difference between the 'verstage' and 'libverstage'
classes, and the source files added to them are just treated the same
way a bootblock or romstage source files in configurations where the
verstage is linked into either of these respective stages (allowing for
the normal object code deduplication and causing those files to be
compiled with the same flags as the host stage's files).
Tested this whole series by booting a Kevin, an Elm (both with and
without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode.
Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18302
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This reuses some of gm45 code to set up the panel.
Panel start and stop delays and pwm frequency can now be set in
devicetree.
Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.
The core display clock is computed according to "Mobile Intel® 945
Express Chipset Family" Datasheet.
This selects Legacy backlight mode since most targets have some smm
code that rely on this.
This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.
A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.
Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Fix the following error and warnings detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18886
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Add support for using GPIO IRQ instead of PIRQ with an I2C device.
This allows a device to use an edge triggered interrupt that will
trigger on both high and low transitions.
The _DSD method for describing these GPIOs has a field for 'active
low' which is supposed to be 1 if the pin is active low, otherwise
is zero. The value in here doesn't mean too much for GpioInt() as
those will end up using the value from GpioInt() when it actually
requests the interrupt.
BUG=b:35581264
BRANCH=none
TEST=test on Eve board that codec IRQ can be delcared as GPIO IRQ
Change-Id: I02c64c7fc28dc2d608ad40db889c7242892f16db
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18835
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The I2C interface for the Atmel AT97SC3204 TPM varies greatly from the
existing I2C TPM support. The Atmel part just passes the commands and
responses from the TIS layer across the I2C interface.
TEST=Build and run on Galileo Gen2 with Crypto Shield and vboot enabled
Change-Id: Ib2ef0ffdfc12b2fc11fe4c55b6414924d4b676dd
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18800
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add debugging support for the TIS transactions for the I2C TPM chips.
TEST=Build and run on reef
Change-Id: Ibc7e26fca781316d625f4da080f34749f18e4f9b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Fix the following warnings detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: braces {} are not necessary for single statement blocks
WARNING: Unnecessary parentheses - maybe == should be = ?
WARNING: line over 80 characters
WARNING: missing space after return type
TEST=Build and run on Galileo Gen2
Change-Id: I56f915f6c1975cce123fd38043bad2638717d88c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18832
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Disable the display of the MMCONF_BASE_ADDRESS if it is not supported.
TEST=Build and run on Galileo Gen2
Change-Id: Ie4f0fbf264662b5bc12ca923f25395e5e91defea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18801
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the following warning detected by checkpatch.pl:
WARNING: Avoid gcc v4.3+ binary constant extension:
TEST=Build and run on Galileo Gen2
Change-Id: Ied50b94ecae4d3bde5812f6b54bbe2421fd48588
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18747
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I0e5acef53d558948b7713cfe608cd346ddc5e9fe
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18746
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the following warning detected by checkpatch.pl:
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: Ibd351703e60acebbacd6ae5b1a2fa1cb34fd3ff9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the following errors detected by checkpatch.pl:
ERROR: space prohibited before that close parenthesis ')'
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before open square bracket '['
ERROR: spaces required around that ':' (ctx:VxE)
TEST=Build and run on Galileo Gen2
Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18744
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the following error detected by checkpatch.pl:
ERROR: "(foo*)" should be "(foo *)"
False positives are generated by checkpatch for the following condition
which is not properly detecting the variable type:
ERROR: need consistent spacing around '*' (ctx:WxV)
The false positives are found in debug.h and upd_display.c
TEST=Build and run on Galileo Gen2
Change-Id: I0e871d64544ebf5eacbae46466cf7aefbfa701eb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18743
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the following warning detected by checkpatch.pl:
WARNING: please, no spaces at the start of a line
TEST=Build and run on Galileo Gen2
Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18742
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Going forward it's important to note when a CR50 is expected
to be present in the system. Additionally, this Kconfig addition
provides symmetry with the equivalent i2c Kconfig option.
BUG=b:35775104
Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18444
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add a function to allow FSP component loading separately from silicon
initialization. This enables SoCs that might not have stage cache
available during silicon initialization to load/save components from/to
stage cache before it is relocated or destroyed.
BUG=chrome-os-partner:63114
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18413
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.
BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.
Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Previously, the file -i command identified vga_font_8x16.c as
application/octet-stream; charset=binary
Now it identifies as:
text/x-c; charset=us-ascii
- Remove non-ascii characters
Change-Id: I6b513e6457a31828a6e94c954a7e2e7ee18fd4d6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18372
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Add support for more ACPI features in the generic SPI ACPI
driver so it can be flexible enough to support more devices,
or devices in different configurations.
- add a wake pin
- add support for using IRQ GPIO instead of PIRQ
- add power resource support with enable and reset gpios
BUG=chrome-os-partner:61233
TEST=ensure existing SSDT generation is unchanged,
and test that new features generate expected code
Change-Id: Ibe37cc87e488004baa2c08a369f73c86e6cd6dce
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18393
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move the function that adds a power resource block from
i2c/generic to the acpi device code at src/arch/x86/acpi_device.c
so it can be used by more drivers.
BUG=chrome-os-partner:61233
TEST=verify SSDT table generation is unchanged
Change-Id: I0ffb61a4f46028cbe912e85c0124d9f5200b9c76
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18391
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.
Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: M Naveen <naveen.m@intel.com>
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://review.coreboot.org/18211
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Similar to I2C driver, add support for generating SPI device and
required properties in SSDT for ACPI.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles succesfully. Verified SPI device generated in SSDT on
poppy.
Change-Id: Ic4da79c823131d54d9eb3652b86f6e40fe643ab5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18342
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add a new callback to spi_ctrlr structure - get_config - to obtain
configuration of SPI bus from the controller driver. Also, move common
config definitions from acpi_device.h to spi-generic.h
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The existing default path of PCI0.LPCB is missing the \_SB prefix and prevents Linux from detecting the TPM.
This is assuming that normally the LPCB device is most commonly on \_SB.PCI0.LPCB.
SSDT excerpt without the patch:
"""
DefinitionBlock ("", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A)
{
External (_SB_.PCI0.GFX0, DeviceObj)
[...]
External (_SB_.PCI0.SATA, DeviceObj)
External (PCI0.LPCB, DeviceObj)
[...]
Scope (PCI0.LPCB)
{
Device (TPM)
[...]
Scope (\_SB.PCI0.GFX0)
{
Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices
[...]
"""
SSDT excerpt with the patch:
"""
DefinitionBlock ("", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A)
{
External (_SB_.PCI0.GFX0, DeviceObj)
[...]
External (_SB_.PCI0.LPCB, DeviceObj)
[...]
External (_SB_.PCI0.SATA, DeviceObj)
[...]
Scope (\_SB.PCI0.LPCB)
{
Device (TPM)
[...]
Scope (\_SB.PCI0.GFX0)
{
Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices
[...]
"""
After the patch the TPM shows up in /sys/bus/acpi/devices/PNP0C31:00.
Previously it was missing and not detected by the kernel.
Change-Id: I615b4873ca829a859211403c84234d43d60f2243
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18315
Tested-by: build bot (Jenkins)
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The selection of the SSC reference frequency for LVDS was based on a
completely unrelated clock.
The `ssc_freq` flag should be set when the SSC reference runs at a
different frequency than the general display reference clock (DREF).
For most platforms, there is no choice, i.e. for i945 and gm45 the SSC
reference always differs from the display reference clock (i945: 66Mhz
SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and
newer, it's the same frequency for SSC/non-SSC (120MHz). The only,
currently supported platform with a choice seems to be Pineview, where
the alternative is 100MHz vs. the default 96MHz.
Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Linux kernel expects that power management with ACPI should always be
handled using PowerResource. However, some kernel drivers (e.g. ELAN
touchscreen) check to see if reset gpio is passed in by the BIOS to
decide whether the device loses power in suspend. Thus, until the kernel
has a better way for drivers to query if device lost power in suspend,
we need to allow passing in of GPIOs via _CRS as well as exporting
PowerResource to control power to the device.
Update mainboards to export reset GPIO as well as PowerResource for
ELAN touchscreen device.
BUG=chrome-os-partner:62311,chrome-os-partner:60194
BRANCH=reef
TEST=Verified that touchscreen works on power-on as well as after
suspend-resume.
Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18238
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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If cmos is invalid, it doesn't make sense to read the value before
finding that out.
Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18236
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The default macaddress in rt8168.c can be changed with a cbfsfile
called macaddress. This patch makes it possible to add such a file
using Kconfig at build time.
This also changes the name of the cbfsfile from "macaddress" to
"rt8168-macaddress" to avoid confusion.
Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18088
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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o Fix indentation and other whitespace issues,
o Use `const` where applicable,
o Avoid retyping the same constant literals,
o Actually read PCI revision from the device (instead of using the
lowest class byte).
Change-Id: I2c64153c61a51a6a87848360d22f981225812a3b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18185
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Currently car_stage_entry is defined only in romstage_after_verstage and
as a result when SEPARATE_VERSTAGE is not selected, there is no
entry point into romstage and romstage will not be started at all.
The solution is move out romstage_after_verstage.S from fsp1.1 driver
to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the
build and boot issue with this change.
Besides that, rename the romstage_after_verstage to romstage_c_entry
in more appropriate naming convention after this fix.
Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0),
romstage can be started successfully.
Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/17976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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To support intel wifi SAR configuration, it is required coreboot
to publish two ACPI objects (WRDS and EWRD) to supply SAR limit
data sets. VPD entry "wifi_sar" is required to supply the raw SAR
limit data.
BUG=chrome-os-partner:60821
TEST=Enable USE_SAR, boot reef to OS, create the VPD entry, reboot,
check the SSDT dump and verify WRDS and EWRD structures.
Change-Id: I6be345735292d0ca46f2f7e7ea61924990d338a8
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/17959
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix SPI flash ops regressions after commit:
c2973d1 spi: Get rid of SPI_ATOMIC_SEQUENCING
When spi_flash_cmd() is called with argument response==NULL,
only send out command without reading back the response.
Change-Id: I28a94f208b4a1983d45d69d46db41391e267891d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18082
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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We've found that the SLB9645 TPM sometimes seems to randomly start
returning 0xFF bytes for all requests. The exact cause is yet unknown,
but we should try to write our TIS code such that it avoids bad
interactions with this kind of response (e.g. any wait_for_status()
immediately succeeds because all "status bits" are set in the response).
At least for status and burstCount readings we can say for sure that the
value is nonsensical and we're already reading those in a loop until we
get valid results anyway, so let's add code to explicitly discount 0xFF
bytes.
BRANCH=oak
BUG=chrome-os-partner:55764
TEST=None
Change-Id: I934d42c36d6847a22a185795cea49d282fa113d9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420470
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/18006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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uart_fill_lb() was added to drivers/uart/uart8250mem.c, so when the
Oxford OXPCIe952 Kconfig option is enabled, we were getting an error.
"multiple definition of `uart_fill_lb'"
The new version of uart_fill_lb sets the regwidth depending on the
Kconfig symbol DRIVERS_UART_8250MEM_32, so if that's selected, don't
give DRIVERS_UART_OXPCIE as a choice.
Change-Id: Ife24ab390553b10b2266809595c2e06463de708c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with
the ability to perform tx and rx of flash command and response at the
same time. Instead of introducing this notion at SPI flash driver layer,
clean up the interface to SPI used by flash.
Flash uses a command-response kind of communication. Thus, even though
SPI is duplex, flash command needs to be sent out on SPI bus and then
flash response should be received on the bus. Some specialized x86
flash controllers are capable of handling command and response in a
single transaction.
In order to support all the varied cases:
1. Add spi_xfer_vector that takes as input a vector of SPI operations
and calls back into SPI controller driver to process these operations.
2. In order to accomodate flash command-response model, use two vectors
while calling into spi_xfer_vector -- one with dout set to
non-NULL(command) and other with din set to non-NULL(response).
3. For specialized SPI flash controllers combine two successive vectors
if the transactions look like a command-response pair.
4. Provide helper functions for common cases like supporting only 2
vectors at a time, supporting n vectors at a time, default vector
operation to cycle through all SPI op vectors one by one.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17681
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown. Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.
Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.
Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There was an assumption that all SPI controllers could
consume a full page of data to write. However, that
assumption doesn't hold when spi_crop_chunk() indicates
sizes smaller than page size. If the requested offset isn't
page aligned from the start then writes will fail corrupting
data since a page boundary isn't honored.
The spansion driver needed quite a bit more work to honor
the spi_crop_chunk() result. It now mimics the other
driver's code. Also, needed to add spi_crop_chunk() to
marvell/bg4cd SoC to make google/cosmos build. SPI obviously
doesn't work on that platform, but it fixes the build error.
Change-Id: I93e24a5a717adcee45a017c164bd960f4592ad50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17910
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Utilize libgfxinit's support for scaling to simplify the framebuffer
configuration. In case of multiple displays of different resolutions,
we had configured one framebuffer big enough for their union, each
display only showing its respective upper left window. Instead, we use
the smallest resolution now and show the whole image on all displays.
Change-Id: I70a9d92f88ef891703829945264f94ac7eff09b0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17492
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
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Add an alternative gfxinit implementation for textmode. The legacy VGA
plane and textmode is configured through coreboot provided functions.
libgfxinit uses this plane as alternative to the usual high resolution
plane.
Change-Id: Iad0754c50fc6faec35f49583fe1c7cb50ac6c0c5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17279
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This change adds the required device node in SSDT for defining
GPIO-based fixed voltage regulator.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that ELAN touchscreen works with exported GPIOs and ACPI
regulator.
Change-Id: I4380aea0929fb7e81dbe83f940e3e51e983819f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17798
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Enable default acpi path PCI0.LPCB if TPM support is
selected in the kconfig system and the acpi path is not set via
acpi_name callback in the platform code.
Thanks to Aaron Durbin for providing this fix.
Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/17855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add power management type config option that allows mainboards to
either:
1. Define a power resource that uses the reset and enable gpios to
power on and off the device using _ON and _OFF methods, or
2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can
directly toggle the GPIOs as required.
GPIO type needs to be updated in drivers_i2c_generic_config to use
acpi_gpio type so that it can be used for both the above cases.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that elan touchscreen works fine on reef using exported
GPIOs.
Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17797
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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When trying to bring up a device with a malfunctioning TPM2 chip, the
driver currently gets stuck waiting for SPI flow control, causing
bricked devices.
This patch puts a 100 ms cap on the waiting time - this should be
enough even for a longest NVRAM save operation which could be under
way on the TPM device.
BRANCH=gru
BUG=chrome-os-partner:59807
TEST=with a matching change in depthcharge, now a gru with corrupted
SPI TPM comes up to the recovery screen (it was not showing signs
of life before this change).
Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/17898
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Add a generic I2C-HID driver for these types of devices that
do not need extra functionality. This allows a new device to
be added without having to write a new driver.
The i2c-hid PNP0C50 is automatically added as the _CID for the
device in the ACPI Device.
BUG=chrome-os-partner:58666
TEST=used on eve to describe a new i2c-hid touch controller
Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Remove any assumptions required for the drivers using i2c_generic to
have drivers_i2c_generic_config structure at the start of the driver
config. Instead pass in a pointer to drivers_i2c_generic_config from
the calling driver.
Change-Id: I51dc4cad1c1f246b51891abf7115a7120e87b098
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17857
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Update the mrc cache implementation to use region_file. Instead
of relying on memory-mapped access and pointer arithmetic
use the region_devices and region_file to obtain the latest
data associated with the region. This removes the need for the
nvm wrapper as the region_devices can be used directly. Thus,
the library is more generic and can be extended to work on
different boot mediums.
BUG=chrome-os-partner:56151
Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17717
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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In the case where the RTC is initialized after the battery is
completely drained the bits for power_mode and cof_selection are set up
with wrongly applied masks.
In the case where the RTC is re-initialized again with no power-loss
after the last initialization the bits for cap_sel, power_mode and
cof_selection are not shifted to the right position.
Both errors lead to a wrong initialization of the RTC and in turn to a
way larger current consumption (instead of 120 nA the RTC current rises
to over 2 µA).
This patch fixes both errors and the current consumption is in the right
range again.
TEST=booted mc_bdx1 and verified current consumption of RTC
Change-Id: I8594f6ac121a175844393952db2169dbc5cbd2b2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17829
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Don't implement arch or driver -specific code under lib/,
Change-Id: If75980ec5efc622582e2b5e124ad0e7ee3fa39a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17793
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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soc_binding.h includes FSP headers which define NULL macro. Because of
this, including stddef.h after soc_binding.h results in NULL being
re-defined. Thus, include stddef.h in soc_binding.h to avoid having
users include stddef.h along with soc_binding.h.
Change-Id: I600083c5d8f672518beaa1119f14f67728a433aa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17773
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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