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2016-07-19drivers/intel/fsp2_0: Split reset handling logicAndrey Petrov
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The rest 6 codes are platform-specific and may vary. Modify helper function so that only basic resets are handled and let SoC deal with the rest. Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPSAaron Durbin
The FSPS component can request resets. Handle those generically. BUG=chrome-os-partner:52679 Change-Id: I41c2da543420102d864e3c5e039fed13632225b4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15748 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPMAaron Durbin
The FSPM component can request resets. Properly handle those. BUG=chrome-os-partner:52679 Change-Id: If21245443761cb993e86c0e383c8bca87f460a85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15747 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: range check stack provided to FSPMAaron Durbin
Ensure that the stack provided to FSPM doesn't overlap the current program which is loading the FSPM component. If there is a conflict that's an error since it could cause the current program to crash. BUG=chrome-os-partner:52679 Change-Id: Ifff465266e5bb3cb3cf9b616d322a46199f802c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15746 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: don't use saved memory data in recovery modeAaron Durbin
If the system is in recovery mode force a full retrain. BUG=chrome-os-partner:52679 Change-Id: I4e87685600880d815fe3198b820a10aa269baf37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15745 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: honor FSP revision for memory training dataAaron Durbin
Utilizing the FSP revision while saving the memory training data is important because it means when the FSP is updated the memory training is redone. The previous implementation was just using '0' as a revision. Because of that behavior a retrain would not have been done on an FSP upgrade. BUG=chrome-os-partner:52679 Change-Id: I1430bd78c770a840d2deff2476f47150c02cf27d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15744 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19drivers/intel/fsp2_0: remove unused fsp_load_binary()Aaron Durbin
Remove the now unused fsp_load_binary() function. BUG=chrome-os-partner:52679 Change-Id: I5667eb71689a69a9e05f7be05cb0c7e7795a55d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15743 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: load and relocate FSPS in cbmemAaron Durbin
The FSPS component loading was just loading to any memory address listed in the header. That could be anywhere in the address space including ramstage itself -- let alone corrupting the OS memory on S3 resume. Remedy this by loading and relocating FSPS into cbmem. The UEFI 2.4 header files include path are selected to provide the types necessary for FSP relocation. BUG=chrome-os-partner:52679 Change-Id: Iaba103190731fc229566a3b0231cf967522040db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15742 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: John Zhao <john.zhao@intel.com>
2016-07-19drivers/intel/fsp2_0: handle XIP and non-XIP for FSPM componentAaron Durbin
The previously implementation for loading the FSPM component didn't handle platforms which expects FSPM to be XIP. For the non-XIP case, romstage's address space wasn't fully being checked for overlaps. Lastly, fixup the API as the range_entry isn't needed any longer. This API change requires a apollolake to be updated as well. BUG=chrome-os-partner:52679 Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15741 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: separate component validation from loadingAaron Durbin
The current FSP component loading mechanism doesn't handle all the requirements actually needed. Two things need to be added: 1. XIP support for MemoryInit component 2. Relocating SiliconInit component to not corrupt OS memory. In order to accommodate those requirements the validation and header initialization needs to be a separate function. Therefore, provide fsp_validate_component() to help achieve those requirements. BUG=chrome-os-partner:52679 Change-Id: I53525498b250033f3187c05db248e07b00cc934d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15740 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: implement common memory_init() tasksAaron Durbin
Instead of performing the same tasks in the chipset code move the common sequences into the FSP 2.0 driver. This handles the S3 paths as well as saving and restoring the memory data. The chipset code can always override the settings if needed. BUG=chrome-os-partner:52679 Change-Id: I098bf95139a0360f028a50aa50d16d264bede386 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15739 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: set BootLoaderTolumSize genericallyAaron Durbin
The amount of reserved memory just below the DRAM limit in 32-bit space is defined in the FSP 2.0 specification within the FSPM_ARCH_UPD structure. There's no need to make the chipset code set the same value as needed for coreboot. The chipset code can always change the value if it needs after the common setting being applied. Remove the call in soc/intel/apollolake as it's no longer needed. BUG=chrome-os-partner:52679 Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: fix hand-off-block types and sizeAaron Durbin
The gcc compiler treats sizeof(void) == 1. Therefore requesting a 1 byte reservation in cbmem and writing a pointer into the buffer returned is wrong. Fix the size of the request to be 32-bits because FSP 2.0 is in 32-bit space by definition. Also, since the access to the field happens across stage boundaries it's important to ensure fixed widths are used in case a later stage has a different pointer bit width. BUG=chrome-os-partner:52679 Change-Id: Ib4efc7d5369d44a995318aac6c4a7cfdc73e4a8c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15737 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-18elog: Use rdev_mmap to find offset of ELOGFurquan Shaikh
In case of elog not being stored in CBMEM, calculate flash offset by using rdev_mmap instead of assuming that the entire flash is mapped just below 4GiB. This allows custom mappings of flash to correctly convert the flash offset to mmap address. BUG=chrome-os-partner:54186 TEST=Verified behavior on reef. mosys able to read out the elog correctly. Change-Id: I3eacd2c9266ecc3da1bd45c86ff9d0e8153ca3f2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15722 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15drivers/intel/fsp1_1: align on using ACPI_Sx definitionsAaron Durbin
The SLEEP_STATE_x definitions in the chipsets utilizing FSP 1.1. driver have the exact same values as the ACPI_Sx definitions. The chipsets will be moved over subsequently, but updating this first allows the per-chipset patches to be isolated. BUG=chrome-os-partner:54977 Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15665 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-14drivers/i2c: Add new driver for RTC type PCF8523Werner Zeh
This driver enables the usage of an external RTC chip PCF8523 which is connected to the I2C bus. The I2C address of this device is fixed. One can change parameters in device tree so that the used setup can be adapted in device tree to match the configuration of the device on the mainboard. Change-Id: I2d7e161c9e12b720ec4925f1acfd1dd8ee6ee5f5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15641 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-12tpm: report firmware versionVadim Bendebury
Some devices allow to retrieve firmware version by reading the same 4 byte register repeatedly until the entire version string is read. Let's print out TPM firmware version when available. Just in case something goes wrong limit the version string length to 200 bytes. CQ-DEPEND=CL:355701 BRANCH=none BUG=chrome-os-partner:54723 TEST=built the new firmware and ran it on Gru, observed the following in the coreboot console log: Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: cr50_v1.1.4792-7a44484 Original-Commit-Id: 1f54a30cebe808abf1b09478b47924bb722a0ca6 Original-Change-Id: Idb069dabb80d34a0efdf04c3c40a42ab0c8a3f94 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355704 Original-Reviewed-by: Scott Collyer <scollyer@chromium.org> Squashed with: tpm: use 4 byte quantities when retrieving firmware version The CR50 device is capable of reporting its firmware version in 4 byte quantities, but the recently introduced code retrieves the version one byte at a time. With this fix the version is retrieved in 4 byte chunks. BRANCH=none BUG=none TEST=the version is still reported properly, as reported by the AP firmware console log: localhost ~ # grep cr50 /sys/firmware/log Firmware version: cr50_v1.1.4804-c64cf24 localhost ~ # Original-Commit-Id: 3111537e7b66d8507b6608ef665e4cde76403818 Original-Change-Id: I04116881a30001e35e989e51ec1567263f9149a6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356542 Original-Reviewed-by: Andrey Pronin <apronin@chromium.org> Change-Id: Ia9f13a5bf1c34292b866f57c0d14470fe6ca9853 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15573 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-11tpm: use proper locality zero SPI bus addressesVadim Bendebury
The "PC Client Protection Profile for TPM 2.0" document defines SPI bus addresses for different localities. That definition is not honored in the cr50 implementation, this patch fixes it: locality zero register file is based off 0xd40000. BRANCH=none BUG=chrome-os-partner:54720 TEST=with the fixed cr50 image and the rest of TPM2 initialization patches applied factory initialization sequence on Gru succeeds. Change-Id: I49b7ed55f0360448b9a6602ebd31a3a531608da3 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 43344fff5d58ec235e50030413fc38c98dd0a9a1 Original-Change-Id: I2de6fa6c05d3eca989d6785228d5adde1f2a7ab7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355620 Original-Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://review.coreboot.org/15568 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-10intel post-car: Consolidate choose_top_of_stack()Kyösti Mälkki
Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15463 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08drivers/i2c/da7219: Add driver for generating device in SSDTDuncan Laurie
Add a device driver to generate the device and required properties into the SSDT. This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. This was tested on the reef mainboard to ensure that the SSDT contained the equivalent parameters that are provided by the current DSDT object. Change-Id: Ia809e953932a7e127352a7ef193974d95e511565 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
There is a second ACPI _DSD document from the UEFI Forum that details how _DSD style tables can be nested, creating a tree of similarly formatted tables. This document is linked from acpi_device.h. In order to support this the device property interface needs to be more flexible and build up a tree of properties to write all entries at once instead of writing each entry as it is generated. In the end this is a more flexible solution that can support drivers that need child tables like the DA7219 codec, while only requiring minor changes to the existing drivers that use the device property interface. This was tested on reef (apollolake) and chell (skylake) boards to ensure that there was no change in the generated SSDT AML. Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15537 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-06siemens/nc_fpga: Add driver for Siemens NC FPGAWerner Zeh
Add driver code to initialize Siemens NC FPGA as PCI device. Beside some glue logic it contains a FAN controller and temperature monitor. Change-Id: I2cb722a60081028ee5a8251f51125f12ed38d824 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15543 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-05intel/i210: Change API for function mainboard_get_mac_address()Werner Zeh
The function mainboard_get_mac_address() is used to get a MAC address for a given i210 PCI device. Instead of passing pure numbers for PCI bus, device and function pass the device pointer to this function. In this way the function can retrieve the needed values itself as well as have the pointer to the device tree so that PCI path can be evaluated there. Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-02drivers/generic/max98357a: Fix naming and ACPI path handlingDuncan Laurie
The upstream kernel driver is not using the of-style naming for sdmode-gpio so remove the maxim prefix, and remove the duplicate entry for the sdmode-delay value as well. Also fix the usage of the path variable, since the device path uses a static variable it can't be assigned that early or it will be overwritten by later calls. This results in the following output for the _DSD when tested on reef mainboard: Name (_DSD, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x02) { Package (0x02) { "sdmode-gpio", Package (0x04) { \_SB.PCI0.HDAS.MAXM, Zero, Zero, Zero } }, Package (0x02) { "sdmode-delay", Zero } } }) Change-Id: Iab33182a5f64c89151966f5e79f4f7c30840c46f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15514 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24drivers/intel/fsp2_0: Add simple reset handlerAndrey Petrov
Any FSP API call may request a reset. This is indicated in API function return code. Add trivial reset handler code. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: Ieb5e2d52ffdaf3c3ed416603f6dbb4f9c25a1a7b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23kconfig: add missing SPI TPM CS config definitionVadim Bendebury
To fully define TPM attachment to a SPI interface both bus and CS (chip select) settings are required. Add the missing CS configuration option. BRANCH=none BUG=chrome-os-partner:50645 TEST=with the rest of the patches applied it is possible to compile in and run TPM2 SPI driver. Change-Id: If297df8e5b9526f156ed1414eb9db317d6af5b33 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353913 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15299 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-23tpm2: add SPI TPM driverVadim Bendebury
This introduces a SPI TPM driver compliant with the TCG issued "TPM Profile (PTP) Specification Revision 00.43" which can be found by googling its title. The driver implements both the hardware flow control protocol and the TPM state machine. The hardware flow control allows to map SPI based TPM devices to the LPC address space on x86 platforms, on all other platforms it needs to be implemented in the driver software. The tis layer is somewhat superficial, it might have to be expanded later. A lot more implementation details can be found in the code comments. Also, it is worth mentioning that this is not a complete version of the driver: its robustness needs to be improved, delay loops need to be bound, error conditions need to propagate up the call stack. BRANCH=none BUG=chrome-os-partner:52132, chrome-os-partner:50645, chrome-os-partner:54141 TEST=with the rest of the patches applied coreboot is able complete Chrome OS factory initialization of the TPM2 device. Change-Id: I967bc5c689f6e6f345755f08cb088ad37abd5d1c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5611c6f7d7fe6d37da668f337f0e70263913d63e Original-Change-Id: I17d732e66bd231c2289ec289994dd819c6276855 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/350124 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15298 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Tested-by: build bot (Jenkins)
2016-06-23kconfig: allow various tpm type and interface permutationsVadim Bendebury
Until now it was assumed that all TPM devices were of the same type (TCG 1.2 spec compliant) and x86 based boards had LPC connected TPMs and all other boards had I2C connected TPMs. With the advent of TPM2 specification there is a need to be able to configure different combinations of TPM types (TPM or TPM2) and interfaces (LPC, I2C and SPI). This patch allows to do it. Picking Chrome OS still assumes that the board has a TPM device, but adding MAINBOARD_HAS_TPM2 to the board's Kconfig will trigger including of TPM2 instead. MAINBOARD_HAS_LPC_TPM forces the interface to be set to LPC, adding SPI_TPM to the board config switches interface choice to SPI, and if neither of the two is defined, the interface is assumed to be I2C. BRANCH=none BUG=chrome-os-partner:50645 TEST=verified that none of the generated board configurations change as a result of this patch. With the rest of the stack in place it is possible to configure different combinations of TPM types and interfaces for ARM and x86 boards. Change-Id: I24f2e3ee63636566bf2a867c51ed80a622672f07 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5a25c1070560cd2734519f87dfbf401c135088d1 Original-Change-Id: I659e9301a4a4fe065ca6537ef1fa824a08d36321 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349850 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15294 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-22drivers/i2c/generic: Fix compile failureDuncan Laurie
This variable name was changed in chip.h but not the consumer and it was submitted before it was caught. Change-Id: I7c492b588b2fd854a9eeac36029a46da324a7b1b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15109 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-17Fix some cbmem.h includesKyösti Mälkki
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-14drivers/intel/fsp2_0: Add FSP return types for resetAndrey Petrov
FSP methods may require reset under certain conditions. That is indicated by returning specific return code. Add the missing return status codes. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I460353c5f835548a98255bd3e11dbfd08260ea52 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15185 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09soc/intel/apollolake: Update FSP header filesBora Guvendik
Update autogenerated FSP 2.0 generic header files based on FSP release 136_30. Changes were made to avoid duplicating some of the structs for every SoC. BUG=chrome-os-partner:50765 TEST=Build coreboot Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7145 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7584 Reviewed-on: https://review.coreboot.org/15081 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h headerAlexandru Gagniuc
Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03drivers/intel/fsp1_1: Make weak routines quietLee Leahy
Now that there is a better way of finding optional routines, make the weak routines quiet so that it may be used for the optional implementation. TEST=Build and run on Galileo Gen2 Change-Id: Ic58c7de216394f80aee3a78dd08bd4682783be42 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03Add Board Checklist SupportLee Leahy
Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-02drivers/intel/fsp1_1: Update weak MRC cache routinesLee Leahy
Update the weak functions for the MRC cache. TEST=Build and run on Galileo Gen2 Change-Id: I54a1252cfff1a2f68b163f0feb65e2bceb37f6a9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15042 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02generic: Add a Maxim 98357A codec driverDuncan Laurie
The Maxim Integrated 98357A codec is an I2S slave device that has no control channel for configuration and instead provides a GPIO that is used for channel selection and power down. This means it does not fit into a bus hierarchy easily and is instead represented as a generic device and found with a static bus scan using the devicetree. This driver provides configuration options for passing the "sdmode" GPIO descriptor as well as a second option for "sdmode delay" which can configure the timing of the sdmode toggling in relation to the I2S channel output. In addition an GPIO can be provided to indicate to the driver whether this device is present or not. This can be used for board designs that may have different codec possibilities that are selected by HW strap. Sample usage for this device driver: device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C6)" register "sdmode_delay" = "100" device generic 0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.HDAS) { Device (MAXM) { Name (_HID, "MX98357A") Name (_UID, Zero) Name (_DDN, "Maxim Integrated 98357A Amplifier") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "maxim,sdmode-gpio", \_SB.PCI0.HDAS.MAXM, 0, 0, 0 } Package () { "maxim,sdmode-delay", 100 } Package () { "sdmode-delay", 100 } } }) } } Change-Id: Ia0bafe49bea9bbe4a3cc0f9f9cdb6f6390da57b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15017 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02i2c: Add a generic i2c driverDuncan Laurie
This adds a generic I2C driver that can be described in the devicetree and used to generate ACPI objects in the SSDT based on the information provided in the config registers. The I2C bus can be configured and the device can provide an interrupt and wake capability to the OS. A configuration option allows for a GPIO to be provided that will be checked to determine if the device is preset on the board before including it in the generated SSDT. The driver is generic enough to be used for basic I2C devices that do not have special configuration needs such as touchpads, touchscreens, sensors, some audio codec/amplifiers, etc. Sample usage for a touchpad device: device pci 15.1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = "ELAN Touchpad" register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15.0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.I2C1) { Device (D015) { Name (_HID, "ELAN0000") Name (_UID, 0) Name (_S0W, 4) Name (_PRW, Package () { 5, 3 }) Method (_STA) { Return (0x0f) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit, "\\_S.PCI0.I2C1", 0, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 } }) } } Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02drivers/intel/wifi: Add support for generating SSDT tableDuncan Laurie
Intel WiFi devices that support wake-on-wifi need to declare a Power Resource for this wake pin. Typically this has been done with a static declaration in the DSDT for each mainboard. By adding it to the existing intel/wifi driver it can be done based on a configuration register in the devicetree. Additionally the WiFi regulatory domain can be set in the SSDT directly instead of needing to use NVS to pass the value to the DSDT. Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that are found on Chromebooks, and clean up a long line and some comment formatting. This was tested by booting on an HP Chromebook 13 device and comparing that the output in the SSDT matches what used to be in the DSDT. The WRDD value is read from VPD, if present, not from devicetree.cb. Additionally the case where CONFIG_DRIVERS_INTEL_WIFI is enabled but the wifi device is not described in devicetree.cb is tested to ensure it still generates the AML but does not include the _PRW wake pin. Example: devicetree.cb: device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end VPD: "region"="us" SSDT.dsl: Scope (\_SB.PCI0.RP01) { Device (WIFI) { Name (_UID, Zero) Name (_DDN, "Intel WiFi") Name (_ADR, 0x00000000) Name (_PRW, Package () { 16, 3 }) Name (WRDD, Package () { Zero, Package () { 0x00000007, 0x00004150 } }) } } Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15019 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01drivers/lenovo: Add hybrid graphics driverPatrick Rudolph
Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Removed Lenovo T430s from the list of supported devices, as the T430s only supports "muxless Optimus". Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01nau8825: Add driver for I2C codecDuncan Laurie
The Nuvoton NAU8825 audio codec is an I2C device that has a number of tunable parameters that can be provided to the kernel device driver for basic configuration and optimal operation. The configuration options are exposed to devicetree as registers and then presented as Device Properties via ACPI to the operation system. This sample configuration in devicetree: device pci 19.2 on chip drivers/i2c/nau8825 register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" register "jkdet_enable" = "1" register "sar_threshold_num" = "2" register "sar_threshold[0]" = "0x0c" register "sar_threshold[1]" = "0x1c" device i2c 1a on end end end Will generate the following code in the SSDT, trimmed for this commit message as there are more properties that can be configured: Scope (\_SB.PCI0.I2C4) { Name (_HID, "10508825") Name (_UID, Zero) Name (_DDN, "Nuvoton NAU8825 Codec") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x1A, ControllerInitiated, 0x61A80, AddressingMode7Bit, "\_SB.PCI0.I2C4", 0, ResourceConsumer) Interrupt (ResourceConsumer, Level, ActiveLow) { 0x3A } }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bff4aa301"), Package () { Package () { "nuvoton,jkdet-enable", 1 }, Package () { "nuvoton,sar-threshold-num", 2 }, Package () { "nuvoton,sar-threshold", Package () { 0x0c, 0x1c } } } }) } Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I480d72daf5ac3dded9b1cbb5fbc737b9dfde3834 Reviewed-on: https://review.coreboot.org/15015 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phaseHannah Williams
Change-Id: Ib39e828c6e3145957ecc2dacc1f72de793165514 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15020 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31drivers/net/r8168: Add driver for realtek nicDamien Zammit
One thing that is vital to this patch is the MAC address setting in case the EEPROM/efuse is unconfigured. Linux now recognises the default MAC address on GA-G41M-ES2L which does rely on the default bios settings for the MAC address. Change-Id: I32e070b545b4c6369686a7087b7ff838d00764e3 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14927 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
Items under DEVICE_SPECIFIC_OPTIONS got selected without the driver being selected. Change-Id: I1797fa6175620a9291873559a6308eaea85a090e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14823 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26drivers/intel/fsp2_0: Send post codes around calls to the blobsAlexandru Gagniuc
By design, FSP will send POST codes to port 80. In this case we have both coreboot and FSP pushing post codes, which may make debugging harder. In order to get a clear picture of where FSP execution begins and ends, send post codes before and after any call to the FSP blobs. Note that sending a post code both before and after is mostly useful on chromeec enabled boards, where the EC console will provide a historic list of post codes. Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFSAndrey Petrov
Add recipes that insert FSP blobs into CBFS and get rid of CBFS names hardcoding. Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-17drivers/intel/fsp1_1: Simplify union referencesLee Leahy
Simplify the union references to enable Coverity to properly process the routine. Found-by: Coverify CID 1349854 TEST=Build and run on Galileo Gen2 Change-Id: I667b9bc5fcde7f68cb9b4c8fa85601998e5c81ff Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14870 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp1_1: Replace for/break with returnsLee Leahy
Coverity does not like the use of for/break, switch to using returns instead. Found-by: Coverity CID 1349855 TEST=Build and run on Galileo Gen2 Change-Id: I4e5767b09faefa275dd32d3b76dda063f7c22f6f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-17drivers/intel/fsp2_0: Fix array indexing errorLee Leahy
Don't allow an array index of 2 to be processed by the code referencing the array. Found-by: Coverity CID 1353337 TEST=None Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14868 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-12drivers/intel/fsp2_0: Add timestamps around all calls to the blobAlexandru Gagniuc
Change-Id: I384cef0f5b4b71dbd7ad6d1d508e7c6395bf3f2d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-11cbfstool/fsp: Rename fsp1_1_relocateFurquan Shaikh
FSP 2.0 uses the same relocate logic as FSP 1.1. Thus, rename fsp1_1_relocate to more generic fsp_component_relocate that can be used by cbfstool to relocate either FSP 1.1 or FSP 2.0 components. Allow FSP1.1 driver to still call fsp1_1_relocate which acts as a wrapper for fsp_component_relocate. Change-Id: I14a6efde4d86a340663422aff5ee82175362d1b0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-05-11util/cbfstool: Allow xip/non-xip relocation for FSP componentFurquan Shaikh
Currently, convert_fsp assumes that the component is always XIP. This is no longer true with FSP 2.0 and Apollolake platform. Thus, add the option -y|--xip for FSP which will allow the caller to mention whether the FSP component being added is XIP or not. Add this option to Makefiles of current FSP drivers (fsp1_0 and fsp1_1). Change-Id: I1e41d0902bb32afaf116bb457dd9265a5bcd8779 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09drivers/uart: Enable override for input clock dividerLee Leahy
Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09coreboot_tables: Extend serial port descriptionLee Leahy
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09spi: Add support for Winbond W25Q256Varadarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ifde289ec004f5d54d5df32011c87e49470e2bb5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 613b5ae45f7b8325863d8be492a451e6d076e293 Original-Change-Id: I93386e058a60b5c9b61d89607cf8c6e0de6a21ca Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/334522 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09lib/prog_loaders: Allow platforms to skip stage cacheFurquan Shaikh
Before multi-CBFS support was added, x86 platforms cached their ramstage in TSEG so that it could be re-used on the resume path. However, more resources/assets are being put in cbfs that are utilized during ramstage. Just caching ramstage does not mean that correct cbfs region is used for all the data. Thus, provide an option to allow platforms to skip caching any component for resume. Change-Id: I0e957a6b859cc7d700aaff67209a17c6558be5de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14636 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-08parade/ps8640: Initialize edid_sizePatrick Georgi
decode_edid either gets EDID_LENGTH bytes or (in the extended case), 2*EDID_LENGTH. See that this is reflected in its size argument. Change-Id: If6c76358db4e9ee01c2bd2dbdd5948c61b7aa5bc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14698 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-06rtc: Do checksum check for all bytesStefan Reinauer
Due to missing braces (that went undetected because of the indentation), I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8 CMOS: add set_option() only takes the last changed byte into regard when determining whether the checksum needs to be updated. This bug went undetected for 5 years. Change-Id: I47cedc801a60959386dfdcda3a13b8e3162a7ecb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14616 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06drivers/intel/fsp2_0: Update to FSP draft 9Andrey Petrov
Recent FSP draft slightly changed FSP_INFO_HEADER structure. This change keeps FSP driver code in sync with header changes. Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04drivers/xpowers: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Idae5ee5f1f48d904b704abe618165c0bec839979 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04soc/intel/common/mrc_cache: Honor MRC data as a constant pointerAlexandru Gagniuc
The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-02drivers/intel/fsp1_1: fix linking romstage when SEPARATE_VERSTAGE usedAaron Durbin
The skylake-based Chromebooks use a separate verstage which runs just after bootblock and prior to romstage. However, that config is not enabled for coreboot.org so when C_ENVIRONMENT_BOOTBLOCK changes were done it wasn't observed that the Chromebook config failed because 2 _start symbols were present. Remedy this failure by using the common car_stage_entry symbol for taking over control flow. Change-Id: I3f29b90ba8e3786b2106a34e49e6d1f9831dcc7c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-04-28drivers/intel/i210: Use uint8_t and friends instead of u8Werner Zeh
Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14515 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-22drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
The previous commit removed Kconfig, but not Makefile.inc Change-Id: If46a0a3e253eea9d286d8ab3b1a6ab67ef678ee4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14419 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ricoh: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I3cf32ec58ba40db11fae3dda6dcb2375002e7cb4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/generic: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Ide0d48405d85ea2e889916f778e1556287651707 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/aspeed: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I8cf021ea5baff05eb5f84cc014612084afe3f858 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14053 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ati: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Iba43630208be02603f4e0de5f62047bb3d23863a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14054 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/emulation: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I6e30a7be510c66fb1aa88314861d95f8ebe80377 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14056 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/i2c: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Ia210e6832c18270043c0cb21b4881d9c802f3b2b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14058 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ics: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I40373768595a085bba9a5c934794e128f396828b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14059 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/aspeed: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I7a053ac1d8ecc3e443e91daeb406bae0b8c13323 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14060 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/sil: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Ifc32b251677f8b75ffca224c0c900e9c34c756b9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/xgi: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I2cd6c1f1712e77ff98a9557519fb8efeeb400a69 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14049 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/parade: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I1313797d60925cc0627987936199e62073c264d7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19drivers/ti: Switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Iac737e15db512eac96cd16fe14983b66a03876bb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Also, fix up the following driver subdirectories by switching to the src/drivers/[X]/[Y]/ scheme as these are hard requirements for the main change: * drivers/intel * drivers/pc80 * drivers/dec Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14047 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08drivers/intel/fsp2_0: Add utility to recover MRC NV Storage dataHannah Williams
Change-Id: I08d3ba8b64459b1f84a5f1318e37c31010d7ae0f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-08drivers/intel/fsp2_0: Add boot mode constantsAndrey Petrov
This adds boot mode constants. They match EDK2 found in PiBootMode.h constants but are part of FSP2.0 spec. Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-07edid: Make framebuffer row alignment configurableJulius Werner
Our EDID code had always been aligning the framebuffer's bytes_per_line (and x_resolution dependent on that) to 64. It turns out that this is a controller-dependent parameter that seems to only really be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper function to calculate bits-per-pixel dependent values) probably actually broke this for some other controllers by applying the alignment too widely. This patch makes it explicitly configurable and depends the default on ARCH_X86 (which seems to be the simplest and least intrusive way to make it fit most cases for now... boards where this doesn't apply can still override it manually by calling edid_set_framebuffer_bits_per_pixel() again). Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14267 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-04-02lib/prog_loading: introduce prog_segment_loaded()Aaron Durbin
In order to not muddle arch vs chipset implementations provide a generic prog_segment_loaded() which calls platform_segment_loaded() and arch_segment_loaded() in that order. This allows the arch variants to live in src/arch while the chipset/platform code can implement their own. Change-Id: I17b6497219ec904d92bd286f18c9ec96b2b7af25 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14214 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-02drivers/intel/fsp2_0: signal that FSP components are loadedAaron Durbin
In order for the platform code to handle situations where special actions are required after a piece of code is loaded use arch_segment_loaded() to signal to the platform code that the component is fully loaded into memory. Change-Id: I119cfc9913f15eb4968fe5bf6a56589e2c53f2d1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-01intel/gma: Fix VBT generationPatrick Rudolph
The log shows the following error on systems that use the native gfx init. The error isn't shown using the VBIOS blob: GET_VBIOS: aa55 8086 0 3 0 VBIOS not found. Don't shift the class-code, as it's already shifted by the PCI layer. Tested-on: x220 Tested-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: I69018940dd51966b45774e0576a1380f90716dce Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-03-29intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstageDuncan Laurie
For platforms that do verification of memory init (and have verstage execute before romstage) FSP should not attempt to re-initialize the TPM again in romstage as it has already been done. BUG=chrome-os-partner:50633 BRANCH=glados TEST=boot and resume on chell and ensure TPM is not re-initialized Change-Id: Ied6f39dc8dacdbc3d76070b6135de2308196ff53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fefd4d4b3fde4c7fe4b6de304790914b7a2f87d8 Original-Change-Id: I60a2e4e2d73270697218f094527e09d444e6ab56 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Previous-Reviewed-on: https://chromium-review.googlesource.com/332433 Original-(cherry picked from commit 2de1fd57fe1db7960e0bb86c64dccf827fa55742) Original-Reviewed-on: https://chromium-review.googlesource.com/332299 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14106 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-24edid: Add helper function to calculate bits-per-pixel dependent valuesJulius Werner
Coreboot and most payloads support three basic pixel widths for the framebuffer. It assumes 32 by default, but several chipsets need to override that value with whatever else they're supporting. Our struct edid contains multiple convenience values that are directly derived from this (and other properties), so changing the bits per pixel always requires recalculating all those dependents in the chipset code. This patch provides a small convenience wrapper that can be used to consistently update the whole struct edid with a new pixel width instead, so we no longer need to duplicate those calculations everywhere. BUG=None TEST=Booted Oak in all three pixel widths (which it conveniently all supports), confirmed that images looked good. Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-16parade/ps8640: Clean upPatrick Georgi
Sort out some style issues that were identified by Paul. Change-Id: I9ed946ae613c87234f8c9824eb14b8d28909dfcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14064 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-14intel/fsp1.1: Mark graphics init done after SiliconInit phaseDuncan Laurie
If the VBT was provided to the FSP GOP driver then graphics init will be done as part of SiliconInit step and we can mark that when it is completed. This will result in the "oprom" flag being set properly in the coreboot gpio table and the netboot firmware will have video. [pg: avoided conflict with Quark that comes without silicon_init_params.GraphicsConfigPtr] BUG=chrome-os-partner:50864 BRANCH=glados TEST=boot image.net.bin on chell and get working graphics without being setuck in a reboot loop thinking graphics needs to be started when it already has been. Change-Id: I0e481b4be57096ed5c60d78e3fa00f3bb2a4eae1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 089d93c712431d1b5923e844137c558994555e95 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331301 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-(cherry picked from commit eeb9d470d8118422feb39ca71106972f2882e240) Original-Change-Id: Ic59bad27eb9f184ca3eba24643851bfadfe23ab5 Original-Reviewed-on: https://chromium-review.googlesource.com/331355 Reviewed-on: https://review.coreboot.org/13986 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-03-12Add a driver for the parade ps8640Jitao Shi
BRANCH=none BUG=none TEST=none Change-Id: Icf397ce2ffdaed5048367daf2086c067984fea0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b5a88793ccfc46af196300791a300be67b70f5b1 Original-Change-Id: I75adf2688c9c8b9a2338f7dee5d0ac10e7181529 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/321056 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-11spi/SST: fix write support for SST25VF064CAlexander Couzens
The SST25VF064C doesn't support the auto incrementing write which all other supported SST chips support. Allow the chips to select their write method. Change-Id: Ic088d35461a625469ee6973d1267d7dd11963496 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14000 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-09drivers/intel/fsp2_0: remove struct resource usageAaron Durbin
There's no need to use a struct resource type for fsp_find_reserved_memory(). struct resource is mainly associated with a device and that memory is added to cbmem after memory init. Other uses ins FSP 2.0 just use struct range_entry. Use that instead for consistency. Change-Id: Id7d39da1c2e23f97cdaafd7f5d281cefa6fee543 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13960 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: add TODOs to fix deficienciesAaron Durbin
The FSP 2.0 implementation doesn't handle FSP modules for SoCs that are required to be XIP. There is no notion of "loading" in that situation where one should be copying anything anywhere. Additionally, the loading code does not handle overlaps within the current running program which is doing the loading. Change-Id: Ide145581f1dd84efb73a28ae51b3313183fa127a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13959 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: don't leak resourcesAaron Durbin
rdev_mmap() was not followed by rdev_munmap(), thus leaking resources. Fix the leak. Change-Id: Ibdd30d6b64616038013b4bb748f2ad4a98db5472 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13958 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-08intel/wifi: Add WRDD ACPI methodDuncan Laurie
Add an ACPI file containing a generic WRDD method that is used by Intel wireless kernel drivers to determine the country code to be used for regulatory domain configuration of the wireless radios. This requires an NVS variable called 'CID1' to provide an ISO-3166-2 alpha-2 country code or it will just return 0 instead. This is implemented as a bare method because this needs to be included directly into the wifi device that is defined by the mainboard as it may have board-specific settings like _PRW that need to be provided as well. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Change-Id: I27a5e27f65d05ff62a0e79a87a32c1ef0c5d0ef3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2da0cf76ca3cc5e3dfbc4a0859733523de780cf5 Original-Change-Id: I9d83c3938cceafc77ef8747a5c47f586ee84437e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329294 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08drivers/intel/fsp2_0: Add framebuffer graphics supportAlexandru Gagniuc
This adds a few helper functions that are intended to assist setting up framebuffer. Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13802 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add hand-off-block parsersAlexandru Gagniuc
FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13801 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add Notify Phase APIAndrey Petrov
This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13800 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>