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2015-05-19ivybridge native gfx init: Adjust state to be compatible with OPROM.Vladimir Serbinenko
My main payload is GRUB and I load SeaBIOS as secondary payload when for some reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom (SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either completely uninited gfx or some special state in gmbus and software scratch registers. Provide this state. The only alternative without this patch for such usecase is to use oprom and I'd like to avoid doing so when going my main boot path to GNU/Linux. Change-Id: I38e78fb845e43b81df084cd4d65f4618bfb2506d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19gma/edid: Fix gma register access.Vladimir Serbinenko
0x20 was incorrectly represented as 4 * 5 while in fact it's 4 * 8 Change-Id: I6053a3baa6de0da9f1d648009353bc1fe542f81f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10237 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-18drivers/gic: reprogram the GIC CPU interface to bypass IRQJoseph Lo
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. So the CPU can exit from WFI when an asserted IRQ is coming. This is critical for power gating a CPU. BRANCH=none BUG=chrome-os-partner:39620 TEST=testing with CPU idle with power down state support and CPU can wake up normally Change-Id: I71ac642e28024a562db898665b74a5791fce325a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a3f098cbf3fbfdab8150ebd4fd688fdb472b529 Original-Change-Id: I20569a18f34a4b11b8c8c67ea255b3d0f021839f Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269116 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10172 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-17lenovo/x200: Enable wacom digitizer support for x200tAlex David
This patch is based on commit f2b3cd63 (lenovo/x60: Support digitizer on X60t and X201t) Tested on Thinkpad X200 Tablet (7450): all pen functionallity works (i.e. movements, presure sensitivity and buttons) Change-Id: I9bd18642a6ea4211dc3be065456a507fc0b72561 Signed-off-by: Alex David <opdecirkel@gmail.com> Reviewed-on: http://review.coreboot.org/10208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-15x230: Fix ricoh driver.Vladimir Serbinenko
Inclusion of ricoh driver was lost in 1d7b9de3504e90f0886fccec3a1f8a783fd4cc58. So the relevant code wasn't even compiled. Fix copy-paste mistakes without significance while on it as well. Change-Id: Ie548cb43f986f147658fc9c67963f8a055250598 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10211 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13verstage: provide support for serial consoleAaron Durbin
verstage previously lacked serial console support. Add the necessary objects and macro checks to allow verstage to include the serial console. Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-12FSP 1.1 Comparison BaseLee Leahy
Add FSP 1.0 source for comparison with FSP 1.1. BRANCH=none BUG=None TEST=None Change-Id: I8df349f97acfa74f4de3607d49633da3d4884546 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10116 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-12usbdebug: Add FTDI FT232H supportKyösti Mälkki
Tested with gizmosphere/gizmo1 Explorer add-on board, which exposes the following device: 0x0403 Future Technology Devices International, Ltd 0x6014 FT232H Single HS USB-UART/FIFO IC For now UART is hard-coded to 115200, 8n1, no flow-control. Change-Id: I4081f84f7700751ccbf079e7fcbb1467aa71d872 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10063 Tested-by: build bot (Jenkins)
2015-05-11secmon: Add some missing filesPatrick Georgi
secmon is referring to uart's default_baudrate() and various coreboot version strings. Change-Id: I40a8d1979146058409a814d94ea24de83ee4d634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-08northbridge/intel/gm45/gma: Add backlight control register fieldTimothy Pearson
This allows the backlight control register to be set via devicetree.cb Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9330 Tested-by: build bot (Jenkins)
2015-05-07kbuild: Use wildcard for driver subdirectoriesStefan Reinauer
Change-Id: Id1685c0b28ec8e3ab972a671af6f2de6f321c645 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9805 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-04drivers/spi/stmicro: Rename N25Q256A to N25Q256David Imhoff
The 'A' indicates the production process(64 nm). All other chips from the same family leave this out. TEST=Build and booted on Minnowboard Max Change-Id: I21e6c01de5d547bbc2252e679a001948e7ab752c Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10078 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-04drivers/spi/stmicro: Add '.op_erase' for N25Q256David Imhoff
'.op_erase' was not specified for this chip. Set it to sub sector erase(CMD_M25PXX_SSE). Adjust page/sector size for sub sector erase to work. TEST=Untested, due to lack of hardware. Change-Id: Icc2748fbd3afeb56693e1c17d97eb490fba67064 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10077 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-04drivers/spi/stmicro: Add N25Q064 supportDavid Imhoff
N25Q064 is similar to N25Q128. TEST=Build and booted twice on Minnowboard Max Change-Id: Iec105f8b81f619846cf40b40042cc59150b81149 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10076 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-04spi: Remove out of date comment and reorder flash tableDavid Imhoff
What is described by the comment has already been fixed in f0d038f4 (flash: use two bytes of device ID to identify stmicro chips). This also means that STM_ID_N25Q128 doesn't have to be at the top of stmicro_spi_flash_table anymore. TEST=Untested, due to lack of hardware Change-Id: I7a9e9a0cdfdb1cf34e914e186fc6957c1d9b5ca6 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10068 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-04spi: Change 'page' to 'sector' in log messageDavid Imhoff
The log message says 'page size' while actually the sector size is printed. This is confusing since for stmicro page size != sector size. Also add '0x' prefix to numbers to make it clear they are in hex. TEST=Build and booted on Minnowboard Max Change-Id: I795a4b7c1bc8de2538a87fd4ba56f5a78d9ca2ac Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10067 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-02drivers/intel/fsp1_0: Remove executable bit from C filesPaul Menzel
Fix up commit c13ad6c6 (driver/intel/fsp: Correct the fastboot data (MRC data) printing length) unintentionally making the changed files executable. Change-Id: I909c323023a9ccfb0c20094d9085ae90043b9e04 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/10060 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-30vboot: split class in library and stagePatrick Georgi
The build system includes a bunch of files into verstage that also exist in romstage - generic drivers etc. These create link time conflicts when trying to link both the verstage copy and romstage copy together in a combined configuration, so separate "stage" parts (that allow things to run) from "library" parts (that contain the vboot specifics). Change-Id: Ieed910fcd642693e5e89e55f3e6801887d94462f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10041 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-30i2c/tpm: add final newlinePatrick Georgi
Change-Id: I0024c4d56f93eb6c9a54103e79c9d8a8b7d8d6fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10043 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-28Kconfig whitespace fixesMartin Roth
trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28fsp platforms: consolidate FspNotify callsMartin Roth
Consolidate the FspNotify calls into the FSP driver directory, using BOOT_STATE_INIT_ENTRY to set up the call times. Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9780 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28Fix some minor Kconfig issuesMartin Roth
- Remove Kconfig files that are no longer used: src/vencorcode/Kconfig src/soc/marvell/Kconfig - Fix the drivers/sil/Kconfig to point to drivers/sil/3114 which had the same code. - Make sure all Kconfig files have linefeeds at the end. This can cause problems, although it wasn't in this case. - Include cpu/intel/model_65x/Kconfig which was not being included. Change-Id: Ia57a1e0433e302fa9be557525dc966cae57059c9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28OxPCIe: Fix UART base addressesKyösti Mälkki
The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8780 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-24driver/intel/fsp: Correct the fastboot data (MRC data) printing lengthYork Yang
Fastboot data in Intel FSP project is printed by hexdump32() in dword length. So the data length needs to be divided by 4 when printing it. Change-Id: I959d538bd6e60282882dd138045cc730b4bd8159 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/9976 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-24fsp: Move fsp to fsp1_0Marc Jones
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22i2c/ww_ring: add a pattern for normal bootVadim Bendebury
It became necessary to indicate the beginning of the normal boot process. This patch adds a new pattern, a slow (over 2 seconds) fade in into the 0, 87, 155 color. BRANCH=storm BUG=chrome-os-partner:39044 TEST=tested by the next patch. Change-Id: Idd977688e5aa2cc55fc295072c0766526ae95016 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 577c8bd6f8c69073cfdd7acd4a87e7ae603d48e6 Original-Change-Id: I9aff3f4558e733ff2e47206075533556e400f183 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265535 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9922 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: update color definitionsVadim Bendebury
After testing on a final assembly the PD team adjusted the wipeout request and recovery request modes' colors. BRANCH=storm BUG=none TEST=verified new colors while booting an SP5 device in recovery mode Change-Id: I9bd2dac63b99140573533c2cda8eaa9213478ab1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 41c34a619dc0317af67907f18ee844c71a73d623 Original-Change-Id: Iab84710ebdeed35ddd4a8a163bbb6b8ac9cdb799 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262602 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: change colors for different display modesVadim Bendebury
Modify colors as suggested by product review folks. This is not final, to make it easier to identify RGB locations in the hex dumps, express their values in decimal as opposed to hex. BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified new all three color schemes while pressing the recovery button at boot for 20 seconds. Change-Id: I7461acd7004e3d10cba6665a9bfe25ec8aa6f3ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a075824a1954eb5d1b65ce887304924724a6d21 Original-Change-Id: I7f5968e361333572fd1f84aa11b7150194ad902a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261690 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: use shorter blinking programVadim Bendebury
The originally loaded blinking program was written to allow gradual change in LED brightness, which required controlling each LED with its own engine. In fact there is no need in gradual brightness changes when the firmware is controlling the ring. This allows to control all LEDs by one engine, making the code simpler and more robust (no need to synchronize the three engines any more). BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified that recovery boot WW ring patterns work as expected. Change-Id: I89d231fb61693f4e834d8d9323ae5a7ddd149525 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19809cf8120df8865da9b5b9e7b8e932334bf4b5 Original-Change-Id: I41038fd976dc9600f223dc0e9c9602331baf68f9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9873 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: stop running programs before loading the new onesVadim Bendebury
The two controllers on the ring are programmed independently, and if the second controller is running the old pattern while the first one was loaded with a new pattern, there is a window of when the two unrelated patterns might interact. To avoid this shut down execution on both controllers before starting downloading the new pattern code. BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified recovery/wipeout LED ring behavior did not change. Change-Id: I163f2983d414fe839208054ae3e9025663a46aeb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3502ca6b119c033855b45388e7b782d35cfdd82b Original-Change-Id: I0f71f94a7e82f6c0e7f98d3aad1f93ece207248f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261200 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9872 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: define display pattern programsVadim Bendebury
Add compiled lp55231 code snippets to allow display certain patterns when booting the device with the recovery button pressed. As soon as the press is detected, the low intensify solid white pattern is enabled. Holding recovery button long enough causes the device transition between the wipeout requested and recovery requested states, with the appropriate changes in the displayed pattern. The patch also includes the source code for the LED controller as well as instructions on how to compile and modify the code to result in different colors, intensities, blink periods and duty cycles. BRANCH=storm BUG=chrome-os-partner:36059 TEST=reboot an SP5 device with the LED ring attached, keep the recovery button pressed, observe the changes in the LED display pattern while the device progresses through the boot sequence. Change-Id: Ic7d45fc7c313b6d21119d4ae6adaeb4f46f7d181 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0fd6a5c0067d705197816629f41640a931d2f7cd Original-Change-Id: Ib5cc5188c2eeedbba128101bf4092a0b9a74e155 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260670 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9870 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: decouple LED display from vbootVadim Bendebury
The patterns displayed on the LED ring while under the coreboot control are not driven by the vboot, but by the board code instead, The four distinct states of the LED display are: - all off - recovery button push detected, waiting for it to be released - wipeout request pending - recovery button was pushed long enough to trigger this request - recovery request pending - recovery button was pushed long enough to trigger this request. BRANCH=storm BUG=chrome-os-partner:36059 TEST=no functional changes Change-Id: I38d9a3028013b902a7a67ccd4eb1c5d533bf071c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bdfff0e646283da6a2faaacf33e0179d2fea221c Original-Change-Id: Ie279151b6060a2888268a2e9a0d4dc22ecaba460 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260649 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9868 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c/ww_ring: various driver fixes and improvementsVadim Bendebury
When in development environment, some SP5 devices might not have the LED ring attached. They are still fully functional, but when booting up are generating massive amount of i2c error messages. This patch prevents accesses to non-existing lp55321 devices. When loading the program into the device the vendor recommends 1 ms delay when accessing the program control register. This patch separates these accesses into a function and add a delay after every access. Another fix - advance the program address when loading multipage programs. Set the global variable register 3c, not used by coreboot programs, to a fixed value. This will allow depthcharge to avoid re-initializing the controller when not necessary. BRANCH=storm BUG=chrome-os-partner:36059 TEST=booted firmware on an SP5 with no LED ring attached, no excessive error messages are generated, saw the default pattern displayed when the recovery button is pressed during reset. Change-Id: I6a2a27968684c40dae15317540a16405b1419e30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e0b4c84aca27460db594da1faf627ddee56f399 Original-Change-Id: I10f1f53cefb866d11ecf76ea48f74131d8b0ce77 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260648 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9867 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22i2c: add support for ww_ringVadim Bendebury
This is a copy of the depthcharge ww ring driver implementation ported into coreboot. The main differences are: - direct use of the i2c driver instead of using the callback driver description - no dynamic memory allocation for the controller structures BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applied the LED ring gets initialized to the default pattern at coreboot start. Change-Id: I6902c8b76fc173ad2ec28b8cc94695e892df338a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eda24b78f8aff311dd6296d458bdfecf26c3d65a Original-Change-Id: I5660dc3f255aab8fbe3a87041c72916a645c193b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/257730 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22elog: use CONFIG_RTCPatrick Georgi
When RTC is not selected, return all 0. Change-Id: I892a9489fc1d82fb8e61cf02666f797dc6412e05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22rtc: add config flag to denote rtc API availabilityPatrick Georgi
RTC drivers now select RTC, so that code which depends on them can implement fallback behavior for systems that lack the hardware or driver. Change-Id: I0f5a15d643b0c45c511f1151a98e071b4155fb5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9953 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22armv8/secmon: Disable and Enable GIC in PSCI pathFurquan Shaikh
Disable and enable GIC before switching off a CPU and after bringing it up back respectively. BUG=None BRANCH=None TEST=Compiles successfully and psci commands work for ryu. Change-Id: Ib43af60e994e3d072e897a59595775d0b2dcef83 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5271d731f0a569583c2b32ef6726dadbfa846d3 Original-Change-Id: I672945fcb0ff416008a1aad5ed625cfa91bb9cbd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265623 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9926 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-22elog: Eliminate CONFIG_ELOG_FULL_THRESHOLD and CONFIG_ELOG_SHRINK_SIZESol Boucher
These Kconfig options provided a level of configurability that is almost never necessary, so they are being moved into ordinary preprocessor defines in elog_internal.h. The new threshold to trigger shrinking is relative to the number of additional (maximum-size) events that can fit, and the new target post-shrink size is a percentage of the total ELOG area size. BUG=chromium:467820 TEST=Add loop at the end of elog_init() that fills the ELOG area to just below full_threshold with dummy events. Observe successful shrinkage when the next event is logged. BRANCH=None Change-Id: I414c4955a2d819d112ae4f0c7d3571576f732336 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce439361e3954a2bf5186292f96936329171cf56 Original-Change-Id: I926097f86262888dcdd47d73fba474bb2e19856a Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260501 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9869 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21Unify byte order macros and clrsetbitsJulius Werner
This patch removes quite a bit of code duplication between cpu_to_le32() and clrsetbits_le32() style macros on the different architectures. This also syncs those macros back up to the new write32(a, v) style IO accessor macros that are now used on ARM and ARM64. CQ-DEPEND=CL:254862 BRANCH=none BUG=chromium:444723 TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu, Storm and Urara. Booted on Jerry. Tried to compare binary images... unfortunately something about the new macro notation makes the compiler evaluate it more efficiently (not recalculating the address between the read and the write), so this was of limited value. Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254866 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Manually clean up the mess left by write32() transitionJulius Werner
This patch is a manual cleanup of all the rubble left by coccinelle waltzing through our code base. It's generally not very good with line breaks and sometimes even eats comments, so this patch is my best attempt at putting it all back together. Also finally remove those hated writel()-style macros from the headers. BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254865 Reviewed-on: http://review.coreboot.org/9837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Globally replace writel(v, a) with write32(a, v)Julius Werner
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21arm(64): Replace write32() and friends with writel()Julius Werner
This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>, src/soc/<arm(64)-soc> and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17flash: use two bytes of device ID to identify stmicro chipsDaisuke Nojiri
stmicro flash chips use 2 bytes as a device id: upper byte for memory type and lower byte for capacity. with this change, we will use all 2 bytes to identify a chip. BUG=none BRANCH=broadcom-firmware TEST=booted purin and verified n25q256a was identified. Change-Id: I8f382eddc4fa70d3deceb4f9d2e82026a7025629 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f70a1d4b7e1142afec9ce097c4a21b6225f66e Original-Change-Id: Id3378a77318fabb74ddb30f1a9549010636872ba Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199387 Original-Reviewed-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/251305 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9774 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17spi: allow inclusion of Micronix and STM drivers in bootblockVadim Bendebury
Bootblock does not allow using malloc, use statically allocated chip structures instead. BRANCH=storm BUG=chrome-os-partner:33489 TEST=both drivers compile when configured in, also booted whirlwind with an STM compatible SPI NOR flash. Change-Id: I154c33ce5fc278d594205d8b8e62a56edb4e177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eedbb959a595e0898e7a1dd551fc7c517a02f370 Original-Change-Id: I29b37107ac1d58a293f531f59ee76b3d8c4b3e7c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/248992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-17spi: Add function to read flash status registerDuncan Laurie
Add a function that allows reading of the status register from the SPI chip. This can be used to determine whether write protection is enabled on the chip. BUG=chrome-os-partner:35209 BRANCH=haswell TEST=build and boot on peppy Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240702 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c58f17689162b291a7cdb57649a237de21b73545) Change-Id: Ib7fead2cc4ea4339ece322dd18403362c9c79c7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbdf0d72892eef4a742a418a347ecf650c01ea5 Original-Change-Id: I2541b22c51e43f7b7542ee0f48618cf411976a98 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241128 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17drivers/spi: Pass flash parameters from coreboot to payloadDan Ehrenberg
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17as3277: Fix month-off-by-one error for RTC driverJulius Werner
The AS3277 RTC code seems to closely follow the corresponding Linux driver. Unfortunately, while coreboot (and even other parts of Linux, like mktime()) directly follows the standard IBM PC RTC time representation (except for the BCD part), Linux' struct rtc_time decided to use 0-based (instead of 1-based) months instead. This patch removes the faulty month offset that was copied into our driver so that we will generate correct timestamps again. BRANCH=nyan BUG=chrome-os-partner:34108 TEST=firmware_EventLog (pre-release version) gets further than before (and then craps up on unrelated problems with suspend/resume events). Change-Id: Ica221a8bcfd7c1c6cd7ba382d760b586d511e3a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b55c3f5bbecc776a71338256b910aecccac1e04 Original-Change-Id: I163fa4778ec534cd9e6f92a6b6dc55e9871a6a82 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238122 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13tpm: Only expose base address Kconfig option when enabledPatrick Georgi
Change-Id: Ia8ddd689a3bf09ed68f94907ea19d4d2ee874542 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/9594 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13spi: support controllers with limited transfer size capabilitiesVadim Bendebury
Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI read and write transactions. Limiting transfer size in the wrapper allows to provide the API user with unlimited transfer size transactions. The tranfer size limitation is added to the spi_slave structure, which is set up by the controller driver. The value of zero in this field means 'unlimited transfer size'. It will work with existion drivers, as they all either keep structures in the bss segment, or initialize them to all zeros. This patch addresses the problem for reads only, as coreboot is not expected to require to write long chunks into SPI devices. BRANCH=none BUG=chrome-os-partner:32441, chrome-os-partner:31438 TEST=set transfer size limit to artificially low value (4K) and observed proper operation on both Pistachio and ipq8086: both Storm and Urara booted through romstage and ramstage. Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4f064fdca5b6c214e7a7f2751dc24e33cac2ea45 Original-Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/232239 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13tpm: wait for valid bit to be set in TPM access register before using tpmSourabh Banerjee
As per the TCG PC Client TPM Interface Specification v1.2, bit 7 of the access register (tmpRegValiSts bit) stays "0" until the TPM has complete through self test and initialization. This bit is set "1" to indicate that the other bits in the register are valid. BRANCH=chromeos-2013.04 BUG=chrome-os-partner:35328 TEST=Booted up storm p0.2 and whirwind sp3. Verified TPM chip is detected and reported in coreboot logs. Change-Id: I1049139fc155bfd2e1f29e3b8a7b9d2da6360857 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 006fc93c6308d6f3fa220f00708708aa62cc676c Original-Change-Id: I9df3388ee1ef6e4a9d200d99aea1838963747ecf Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242222 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9567 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13elog: Fix regression that caused elog to omit "System boot" eventJulius Werner
CL:243671 moved the initialization of elog_initialized around, which is now unfortunately so late that the ELOG_TYPE_BOOT event gets omitted because the code believes the log to be broken at that time. Good thing we now have a FAFT test for these things that I had of course been too lazy to run. -.- The real reason for moving that line was to put it after any point in elog_init() that could still error out. The problem is that we might add the "cleared" event before we try to shrink (which can fail and cause an error)... but those two things cannot happen at the same time, so it should be okay to flip them around and mark the elog as initialized in between. BRANCH=none BUG=chrome-os-partner:35940 TEST=Ran firmware_EventLog on a Pinky, manually confirmed that I once again get "System boot" events. Change-Id: I12dcf4a8e47d302f6cd317194912c31db502bbaf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4a1c0b861017ca25229b1042c4b37dda33e869f9 Original-Change-Id: I4103779790e1a8a53ecabffd4316724035928ce6 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246715 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9503 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13elog: Correct behavior when FMAP section doesn't exist on ChromeOSJulius Werner
The elog driver has a really stupid bug that checks a result which is stored in an unsigned variable for < 0. Surprisingly GCC does not catch this nonsense right now, and I spent an hour trying out different warning options without finding one that doesn't also bring a load of stupid and unavoidable false positives (the biggest offender being -Wtype-limits, which does exactly what we'd want except for flagging things like if ((u8)var >= CONFIG_VAR_MIN) where the VAR_MIN Kconfig may or may not be 0). So, the only thing we can do is fix this one and wait for the next time something like that blows up. -.- Also change some more code to make the behavior more explicit (the old code already intended to work this way since flash_base is statically initialized to 0, never assigned in the error path and checked later in elog_init()... but there was an error message that incorrectly claimed a different fallback behavior, and explicitly assigning the values makes this easier to see). Finally, add another state to the elog_initialized variable to avoid trying to reinitialize a broken eventlog on every event (if it doesn't work the first time, chances are that it won't work later on during the same boot either). BRANCH=None BUG=chrome-os-partner:35940 TEST=Flashed Jerry with RO 6588.4 and RW 6588.23, observed how it now cleanly enters recovery mode without blowing its bootblock away with stray eventlog entries. Change-Id: I0e5348ba961ce4835c30f7108a2453522095f2ee Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f9798dbf0c2b2e337062ecd84d0f45434343c0d9 Original-Change-Id: I4d93f48d2d01d75a04550d419e023aa42ca95a7a Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/243671 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9557 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10TPM: Reduce buffer size to fix stack overflowJulius Werner
The TPM driver by default allocates a 4K transfer buffer on the stack, which leads to lots of fun on boards with 2K or 3K stack sizes. On RK3288 this ends up writing over random memory sections which dependent on the memlayout of the day might contain timestamp data (no big deal) or page tables (-> bad time). This patch fixes the problem by reducing the buffer size to slightly above 1K, which still seems to work as far as I can tell. There was already some really odd code that #undef'ed this value and redefined it with the lower number in one .c file (unfortunately not the one with the buffer declaration), with no explanation whatsoever... I'm removing that and just assume the smaller value will be fine for everything. BRANCH=veyron BUG=None TEST=Booted Pinky and Falco. Change-Id: I440a5662b41cbd8b7becab3113262e1140b7f763 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3d3288041b6629b7623b9d58816e782e72836b81 Original-Change-Id: Idf80f44cbfb9617c56b64a5c88ebedf7fcb4ec71 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236976 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Remove error message for unknown resource typeDuncan Laurie
This is being triggered because the base address is added, but there is nothing that needs done with it in set_resources step and the ERROR message is tripping suspend resume test scripts. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=boot on samus and check for ERROR strings, successfully run suspend_stress_test without failures Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/231603 (cherry picked from commit bb789492965d92e309a913dc7b9f09f7036c5480) Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I565c8af954f1c5a406d2c65f01c274e9259e43ec Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9062734d884f814dc880589ee615b4d7e1fdc61a Original-Change-Id: I2b5f44795f1ee445d509b29bd56f498aea7b7fe3 Original-Reviewed-on: https://chromium-review.googlesource.com/231604 Original-Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Add ramstage driver and interrupt configurationDuncan Laurie
This adds a ramstage driver for the TPM and allows the interrupt to be configured in devicetree.cb. The interrupt vector is set like other PNP devices, and the interrupt polarity is set with a register configuration variable. These values are written into locality 0 TPM_INT_VECTOR and TPM_INT_ENABLE and then all interrupts are disabled so they are not used in firmware but can be enabled by the OS. It also adds an ACPI device for the TPM which will configure the reported interrupt based on what has been written into the TPM during ramstage. The _STA method returns enabled if CONFIG_LPC_TPM is enabled, and the _CRS method will only report an interrupt if one has been set in the TPM itself. The TPM memory address is added by the driver and declared in the ACPI code. In order to access it in ACPI a Kconfig entry is added for the default TPM TIS 1.2 base address. Note that IO address 0x2e is required to be declared in ACPI for the kernel driver to probe correctly. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=manual testing on samus: 1) Add TPM device in devicetree.cb with configured interrupt and ensure that it is functional in the OS. 2) Test with active high and active low, edge triggered and level triggered setups. 3) Ensure that with no device added to devicetree.cb that the TPM is still functional in polling mode. Change-Id: Iee2a1832394dfe32f3ea3700753b8ecc443c7fbf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fc2c106caae939467fb07f3a0207adee71dda48e Original-Change-Id: Id8a5a251f193c71ab2209f85fb470120a3b6a80d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226661 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tpm: Move the LPC TPM driver to a subdirectoryDuncan Laurie
This moves the LPC TPM driver to drivers/pc80/tpm so it can be turned into a ramstage driver with a chip.h It includes no other changes yet. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=emerge-samus coreboot Change-Id: Iac83e52db96201f37a0086eae9df244f8b8d48d9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: be2db391f9da80b8b75137af0fe81dc4724bc9d1 Original-Change-Id: I60ddd1d2a3e72bcf169a0b44e0c7ebcb87f4617d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226660 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9468 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10rtc: Add an RTC driver for the TI TPS65913 PMIC.Furquan Shaikh
The TPS65913 PMIC has an RTC built into it. This change adds a driver for it which implements the new RTC API. BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log verified across multiple boots. Change-Id: I49ec9b78afc53f1cbd4be09e448cdae6077fb710 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c16c11e620c830e7a73a2a24fe4823ccea0f3c39 Original-Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229414 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9425 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Hide elog_flash_offset_to_address() from SMMFurquan Shaikh
Change-Id: Iaef9d4755f07ca03ca823831c3272183b5d6aed1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9450 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10elog: Fix typecast issues related to 64-bit compilation.Furquan Shaikh
BUG=chrome-os-partner:33764 BRANCH=None TEST=Compiles successfully for ryu and nyan. Change-Id: I036fd42d5cd4b71bcb68eea0fdd9a4e1aa4711e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c3db3d5c8e00b6c273ae240da137062597749aa Original-Change-Id: I5e38966fe06aa3302a7c1b536f5ffd8bb22d4947 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9424 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-10tpm: allow 0 as valid i2c bus numberDaisuke Nojiri
tpm driver uses bus=0 as indication of uninitialized tpm device. this change allows 0 as a valid i2c bus number. BUG=None BRANCH=ToT TEST=Built cosmos. Change-Id: Ie8d285abff11643cc3efc0fa30e4afcc3ca1c0d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 493077b68cf46b08f0d1ddfe57bf6064d714d537 Original-Change-Id: Iac55e88db4ef757a292270e7201d8fdd37a90b50 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226294 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9405 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-01cbfs: correct types used for accessing filesAaron Durbin
In commit 72a8e5e751a7fa97c9d198f68cad49f9d9851669 the Makefile's were updated to use named types for cbfs file addition. However, the call sites were not checked to ensure the types matched. Correct all call sites to use the named types. Change-Id: Ib9fa693ef517e3196a3f04e9c06db52a9116fee7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9195 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31cbfs: remove cbfs_core.h includesAaron Durbin
Some of the files which include cbfs_core.h don't even need the header definition while others just need the cbfs API which can be obtained from cbfs.h. Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9126 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-30Update hex values to CBFS binary name types in MakefilesMartin Roth
These binaries were being added to CBFS using hexadecimal values instead of the CBFS binary type names. The same value was being used in different places for different things. For example, the value 0xAB is used for SPDs, MRC & FSP binaries. This patch uses CBFS type names instead of hex values everywhere a hex value was previously used. Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29drivers/pc80/mc146818rtc_early: Honor Kconfig reboot count clear settingTimothy Pearson
Change-Id: I6426ea2ca1732a6edfae059fe5dbf4f398bc9b98 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9155 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-03-28drivers: add GIC supportAaron Durbin
The GIC is ARM's "Generic Interrupt Controller". This change essentially implements the rudimentary support for a GICv2 implementation that routes all interrupts to Group1. This should also work for GICv1 with security extensions. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel using the code. Change-Id: I9c9202c1309ca9e711e00d742085a6728552c54b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d1cd9b6b76035af107b7dc876f90777698162d34 Original-Change-Id: I4c5b84bfe888ac33fa01c8d64a3dffe1b5ddc823 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217512 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9075 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-23vboot2: read secdata and nvdataDaisuke Nojiri
This code ports antirollback module and tpm library from platform/vboot_reference. names are modified to conform to coreboot's style. The rollback_index module is split in a bottom half and top half. The top half contains generic code which hides the underlying storage implementation. The bottom half implements the storage abstraction. With this change, the bottom half is moved to coreboot, while the top half stays in vboot_reference. TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link. BUG=none Branch=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e Original-Reviewed-on: https://chromium-review.googlesource.com/206065 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Luigi Semenzato <semenzato@chromium.org> (cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0) Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-20verstage should include the CBFS SPI wrapper, when configuredVadim Bendebury
Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER configuration option enabled, so the verstage is missing the relevant files in some Makefiles. This patch fixes the problem. BRANCH=none BUG=none TEST=with the rest of the patches applied cosmos target builds fine with COMMON_CBFS_SPI_WRAPPER enabled Change-Id: I3ce78c8afc5f7d8ce822bbf8dd789c0c2ba4b99c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b72693c96f7d8ce94ce6fe12b316d5b88fded579 Original-Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223751 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8772 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: Add GigaDevice GD25LQ64C/GD25LB64C SPI ROM supportMarc Jones
GD25LQ64C and GD25LB64C have the same ID and settings. BUG=chrome-os-partner:25907 BRANCH=baytrail TEST=Boot with GD25LQ64 and check MRC data save/restore works. Change-Id: I8a4aa7cabd9a7657c2f0bae255a87341db3f1061 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 20b5896adbbbdedcb1b7de435466dcc6bfa703cb Original-Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193238 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8770 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi: do not use malloc in Gigadevice driverDavid Hendricks
This allows us to use the driver before ramstage. BRANCH=none BUG=none TEST=built and booted on Pinky Change-Id: I0700388b0e4e0562e3c0a52863c8357097bfd8d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd57587dab74de509d5c50cfc1ad337d765af6c8 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I0ce901331e401274254b8889484ffb41359119fa Original-Reviewed-on: https://chromium-review.googlesource.com/235864 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8774 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20spi: do not use malloc in Winbond driverVadim Bendebury
When the driver is included in bootblock, malloc() is not available. Come to think of it, it is perfectly fine to use a statically allocated structure for the SPI device descriptor - coreboot is unlikely to require concurrent support of multiple SPI devices of the same kind. BRANCH=none BUG=chrome-os-partner:31438 TEST=bootblock on the FPGA board recognizes the installed Winbond device: coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228959 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-20spi_flash: add support for S25FL116KDaisuke Nojiri
S25FL116K family uses the first 3 bytes in response to a legacy identification command (9f) while previously supported models use the last 4 bytes. This change defines identify functions to allow both types to be handled correctly. BUG=none BRANCH=tot TEST=verified romstage is loaded on cosmos development board. Change-Id: I1970a9af17e81299fada5029724d405de4022156 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 65ff436db2355cb68a766a3dedbcd7e2f765e6db Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Icdd2645e356652672c4482e7b805da1bc0f21e71 Original-Reviewed-on: https://chromium-review.googlesource.com/234431 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18bootstate: use structure pointers for scheduling callbacksAaron Durbin
The GCC 4.9.2 update showed that the boot_state_init_entry structures were being padded and assumed to be aligned in to an increased size. The bootstate scheduler for static entries, boot_state_schedule_static_entries(), was then calculating the wrong values within the array. To fix this just use a pointer to the boot_state_init_entry structure that needs to be scheduled. In addition to the previous issue noted above, the .bs_init section was sitting in the read only portion of the image while the fields within it need to be writable. Also, the boot_state_schedule_static_entries() was using symbol comparison to terminate a loop which in C can lead the compiler to always evaluate the loop at least once since the language spec indicates no 2 symbols can be the same value. Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17elog: Fix compilation with CONFIG_CHROMEOS enabledStefan Reinauer
On ChromeOS devices the ELOG section size and offset are provided by the FMAP, rather than KConfig. Some upstream refactoring broke compilation in that case. Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-14OxPCIe952: Fix read8/write8 argumentKyösti Mälkki
This was missed in commit bde6d309 as the driver is not enabled in any configuration by default. Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8660 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-26drivers/i2c/w83793: Use devicetree.cb to set additional valuesTimothy Pearson
This allows devicetree.cb to set: Minimum PWM values Temperature sensor source Voltage sensor high/low limits Fan pin routing Default PWM values Manual PWM values per-fan Change-Id: I3a321406a26ae01a121289d24b41c9f988dd6f30 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8502 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-24drivers/intel/i210: Add new driver for Intel i210 MACPHYWerner Zeh
Add a new driver for Intel i210 MACPHY with the goal to update the MAC address in i210 if it is found during PCI scan. Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8404 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-23drivers/xgi: Avoid double-freePatrick Georgi
xgifb_probe() doesn't own the object it tries to free in its error code path, potentially leading to a double-free in xgi_z9s_init(). Since we don't actually implement free, it doesn't matter too much, but let's keep things proper. Change-Id: I70c8f395fd59584664040ca6e07be56e046c80fc Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/8506 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-23drivers/xgi: terminate file with newlinePatrick Georgi
That's just how we roll. Change-Id: I47ef62476703fdf2544d9cd77c30ae12452afeae Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/8514 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23drivers/pc80/mc146818rtc: Enable RTC reset on power lossWerner Zeh
If function cmos_init() was called with parameter invalid set, this indicates, that the caller has found a power loss event in the RTC registers. In this case, we need to load the default date and time because it can be corrupted. Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/8373 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-23drivers/i2c/w83793: Remove incorrect zeroing of PWM valuesTimothy Pearson
Fan 2 and Fan 3 were inexplicably set to zero after device setup. Change-Id: I37945745dbfaf33eb28808d85cdf75dca401e44b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8520 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-02-20drivers/xpowers/axp209: Adapt to new I²C APIAlexandru Gagniuc
Originally, axp209_(read|write) accessors relied on i2c_(read|write) to return the number of bytes transferred. This was changed in * cdb61a6 i2c: Replace the i2c API. to return an error code or 0 on success. This caused the AXP209 check to fail. Fix the accessors to account for this new behavior. Change-Id: Ib0f492bd52260d224d87f8e8f2d3c1244d1507df Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8432 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-02-16nvram: Add option to reset NVRAM to default parameters on every bootTimothy Pearson
In specific configurations, such as homogeneous supercomputing systems, changeable NVRAM parameters are more of a liability than a useful tool. This patch allows a coreboot image to be compiled that will always set the NVRAM parameters to their default values, reducing maintainance overhead on large clusters. Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8446 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
2015-02-14drivers/xpowers/axp209: Print a message when probing failsAlexandru Gagniuc
Probing is done by reading the ID register and comparing it to a known value. When there is a mismatch, print an error. Change-Id: I36fb1fe9b56e97660556dcb27be25bfe5129ad73 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-13Fix source code permissionsStefan Reinauer
Two source files were accidently marked executable. Switch them back to mode 644 (rw-r---r--) Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9 Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8426 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-12drivers/xgi: Fix user-visible typo in printkTimothy Pearson
Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-09fsp_baytrail: Get FSP reserved memory from the FSP HOB listMartin Roth
Because the pointer to the FSP HOB list is now being saved, we can use that to find the top of usable memory. This eliminates the need to hardcode the size of the FSP reserved memory area. Tested on minnowboard max for baytrail. The HOB structure used does not seem to be present for the rangeley or ivybridge/pantherpoint FSPs. At the very least, the GUID is not documented in the integration guides. Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8308 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-06drivers/pc80/mc146818rtc: Reduce superfluous preprocessor useAlexandru Gagniuc
cmos_init() had layers of preprocessor directives, which resulted in a complete mess. Refactor it to make use of the IS_ENABLED() macro. This improves readability significantly. One of the changes is to remove in inline stub declaration of (get|set)_option. Although that provided the ability for the compiler to optimize out code when USE_OPTION_TABLE is not selected, there is no evidence that such savings are measureable. Change-Id: I07f00084d809adbb55031b2079f71136ade3028e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8306 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06drivers/xgi: Fix legacy VGA text mode initializationTimothy Pearson
TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s Initial text from coreboot appeared, and the Linux console was displayed immediately at the start of kernel initialization. After boot was complete the text mode console continued to behave normally. SeaBIOS does not currently make use of the legacy VGA text-mode display. Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8360 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05drivers/xgi/z9s: Port Linux framebuffer initialization to corebootTimothy Pearson
Add native XGI Z9s framebuffer support to coreboot XGI initialization code largely taken from Linux 3.18.5 TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS with SeaVGABIOS enabled. Text appeared correctly on screen and interaction with graphical comboot menu was successful. However, Linux cleared the framebuffer on boot, rendering the screen useless until Linux loaded its native xgifb driver. Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8331 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-31FSP platforms: Clear area in CAR for cbmemMartin Roth
This patch clears the CAR area. The FSP loads the entire CAR area with a pattern instead of clearing it. At least the cbmem area needs to be cleared or cbmem will not use it. Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8195 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-29drivers/intel/fsp: Add find_saved_temp_mem()Martin Roth
Add a function to retrieve the location of the CAR temporary memory that was saved by the FSP into the HOB structure. Change-Id: I2635de5207cd699740721d333a7706425b837651 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8194 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2015-01-27drivers/intel/fsp: Add HOB tools to work with GUIDsMartin Roth
Add new functions to: - Compare two GUIDs - Find a hob based on its GUID - Print information about GUID_EXTENSION type HOBs - Print a GUID's address and value Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/8066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16coreboot tpm: Fix printk format specifiersFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I828776724dce287d9a7eb732f2c9ecccf8d68229 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209336 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b50c9441ddaeabc5aa039f2141853ed7ba7a9d5b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6e81312609448c531345e592ee371ea53dc0916c Reviewed-on: http://review.coreboot.org/8221 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-01-15drivers/i2c/w83795: Fix tautology from wrong return typeEdward O'Callaghan
The correct type-signature of 'do_smbus_write_byte' is: int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) and so storing the return type in a 'u32' is inappropriate, leading to a tautological compare of 'ret < 0' and 'err < 0'. Change-Id: I65486df7156c70af84fa00c336142d9a45998620 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8209 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-09elog: Add ELOG_TYPE_BOOT event using fake boot count if necessaryDavid Hendricks
This makes it so that we always log the generic "system boot" event. If boot count support has not been implemented, fake it. BUG=chrome-os-partner:28772 BRANCH=nyan TEST=booted on Big, ran "mosys eventlog list" and saw "System boot" event logged with boot count == 0 Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204525 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351 Reviewed-on: http://review.coreboot.org/8142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09spi: Add Spansion flash S25FL128PVadim Bendebury
Storm devices use more recent Spansion flash, add its description to the table of supported devices. BUG=chrome-os-partner:29871 TEST=the updated firmware boots all the way to depthcharge Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205182 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f Reviewed-on: http://review.coreboot.org/8146 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-06Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"Kyösti Mälkki
This reverts commit 9270553fff23462fcb298f154296319bf3639d15. Change-Id: I195f721ce7a18aac6c1aa6f4e0f9284455d531b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8138 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>