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2024-01-24driver/i2c: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I358b878b97adfd9be156a5dd4a9cbaf9e81bca1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24driver/acpi to /driver/gfx: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I2f299920eb7c6d6f8888cfe5e223ae03093a1d88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80077 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-01-24device: Add inline method to identify PATH_ROOTPatrick Rudolph
Add and use inline method to identify the root device. Change-Id: I394c8668245bcfea6414b8ca5f14ef8135897e59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80169 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-14drivers/mipi: Update init code for BOE_NV110WUM_L60Ruihai Zhou
1. Correct bank1 to bank0 2. Adjust CLK duty 3. Fix abnormal power off setting 4. Change VDDE power off frame from VGL to VGH Fixes: 0d50536("drivers/mipi: Add support for BOE_NV110WUM_L60 panel") BUG=b:319398058 TEST=boot Ciri with BOE_NV110WUM_L60 and see firmware screen Change-Id: I2f068ba0ec9dede3e3361b55c38a8eca8793905a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-11drivers/smmstore/ramstage: use call_smmFelix Held
Use call_smm instead of open-coding the same in inline assembly functionality in init_store. The local ebx variable is dropped, since call_smm takes a pointer to the argument instead of an integer, and the local eax variable is renamed to res to make the code a bit clearer, since the EAX register is used for both passing the command and subcommand to the APMC SMI handler and to get the return value from the handler. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-01-11vc/google: Show different logos for different ChromeOS devicesShelley Chen
This commit adds support for showing different logos on the ChromeOS firmware splash screen based on the device model (between Chromebook-Plus and regular ChromeOS devices like Chromebook and Chromebox). This allows OEMs to customize the branding on their devices. This patch also introduces three new Kconfigs: - CHROMEOS_FW_SPLASH_SCREEN - CHROMEOS_LOGO_PATH - CHROMEBOOK_PLUS_LOGO_PATH which allow users to enable the fw splash screen feature in the vendorcode. Previously, we were using the BMP_LOGO Kconfig in drivers/intel/fsp2_0, but we didn't want the top level Kconfigs to be located inside the architecture specific files. BUG=b:317880956 BRANCH=None TEST=emerge-rex coreboot chromeos-bootimage verify that FW splash screen appears Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79775 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-09drivers/mipi: Add support for IVO_T109NW41 panelRuihai Zhou
Add IVO_T109NW41 serializable data to CBFS. Datasheet: T109NW41 R0 Tentative Product Specification.docx BUG=b:319025360 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: Id740e3a21f72bbcd6e5c2b56b31ac90f4990d475 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79844 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-01-08drivers/mipi: Add support for BOE_NV110WUM_L60 panelRuihai Zhou
Add BOE_NV110WUM_L60 serializable data to CBFS. Datasheet: B5NV110WUM-L60 V5.0Product SpecificationRev.P0 BUG=b:308968270 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: I830a41555131cfc51ef6976ac5428bf9bc03c097 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78956 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-04driver/wifi: DDR RFIM _DSM method function 3 report incorrect valueSimon Yang
The DDR RFIM _DSM method function 3 need to return: - 0: Enable DDR RFIM feature. - 1: Disable DDR RFIM feature. BUG=b:302084312 TEST=Build, dump SSDT to check _DSM function 3 return value Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
2023-12-26drivers/intel/gma: Only show the choice when a VBT is to be addedArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3bb71da8ea47f7365ae3895f5477f2a765256e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-12-26drivers/intel/fsp2_0: Add boot mode stringsMarx Wang
The FSP boot mode showing in serial log is a magic number. In order to let user understand its meaning directly, add the strings to describe the modes. TEST=build, boot the device and check the logs: without this change, the log is like: [SPEW ] bootmode is set to: 2 with this change: [SPEW ] bootmode is set to: 2 (boot assuming no config change) Change-Id: I49a409edcde7f6ccb95eafb0b250f86329817cba Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-22drivers/intel/fsp2_0: Log FW Splash Screen feature stateSubrata Banik
This patch implements debug logging to aid debugging and analysis of Firmware Splash Screen feature behavior. BUG=b:284799726 BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/screebo and check the FW splash screen state. [DEBUG] Firmware Splash Screen : Enabled Change-Id: I1ec7badf620e8dbe3d48674d93d640161de6a830 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-21drivers/spi/gigadevice.c: Add GD25LQ255E supportTyler Wang
datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf BUG=b:311336475 BRANCH=firmware-rex-15709.B TEST=Build AP-firmware and test on karis, system can boot to OS. Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79087 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20treewide: Use show_notices target for warningsMartin Roth
This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-18drivers/spi: Add ISSI IS25WP256D flashMaximilian Brune
datasheet: IS25WP256D Rev A13 (2023-08-03) tested: boot SiFive Hifive Unmatched board Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I655776258cbcf464becf38cbb5045cda5bca711c Reviewed-on: https://review.coreboot.org/c/coreboot/+/79369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13drivers/uart/pl011.c Perform basic UART initNaresh Solanki
Configure UART baud rate, Line Control register as 8n1 with FIFO enable and enable UART TX and RX. Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-13drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I926ec4c1c00339209ef656995031026935e52558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16drivers: spi_flash: Add space before colon to fix coding styleTyler Wang
BUG=none TEST=build karis firmware pass Change-Id: I67b4ca4c8fde795d4206eaa0b9ea9d9bfc768ac6 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-13drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksumBill XIE
Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2023-11-13security/tpm/: turn tis_{init,open} into tis_probeSergii Dmytruk
init() was always followed by open() and after successful initialization we only need send-receive function which is now returned by tis_probe() on success, thus further reducing number of functions to export from drivers. This also removes check for opening TIS twice that seems to have no value. Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76954 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-09Allow to build romstage sources inside the bootblockArthur Heymans
Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-08drivers/i2c/lenovo_serials: Use buildtime constantsArthur Heymans
The coreboot_version global variable just gets filled with the COREBOOT_VERSION macro so there is no reason to use a runtime strconcat. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I3a2be7293d07ac591855ebd784bba350cdffa70f Reviewed-on: https://review.coreboot.org/c/coreboot/+/78945 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-07console/spkmodem: Make it work for bootblockArthur Heymans
This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4113dc3208fe15305d1132136dd33417dd086bfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/78935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-07drivers/net/ne2k: Make it work for bootblockArthur Heymans
This code was written in a romcc bootblock time. There is no reason why it would not work in bootblock now. Untested but expected to work. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I708e8a3b503eb3a7fdf6063803d666529096f651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-04Use common GCD functionYidi Lin
Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78799 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-02drivers/intel/gma/opregion: Use CBFS cache to load VBTJeremy Compostella
Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-01drivers/generic/adau7002: Set ACPI status to hiddenMatt DeVillier
No driver available or needed under Windows, so hide from OS. TEST=build/boot Win11 on google/kahlee (liara), verify ADAU7002 device no longer listed as unknown under Device Manager. Boot Linux and verify audio still functional. Change-Id: If6d250a123825a69441b5c4d3cde35d5a68f568d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78510 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-26drivers/intel/gma/Kconfig: Add VBT compression configuration entryJeremy Compostella
Introduce Kconfig choice to pick between lzma, lz4 and no compression at all of the VBT binary. If VBT is needed in romstage, it can be used to set VBT lz4 compression as an alternative to enabling lzma compression support. Indeed, the extra lzma code needed to de-compress VBT undermines the compression size reduction between lzma and lz4. BUG=b:279173035 TEST=Verified that vbt.bin is lz4 compressed with VBT_CBFS_COMPRESSION_LZ4 and not compressed at all with VBT_CBFS_COMPRESSION_NONE Change-Id: I1df6a96c2ec122f0ef8ee6a1e96ffbd621b14941 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-25drivers/elog: Remove NULL check for array created in codeMartin Roth
Checking to see if a the location of a static variable is NULL isn't super useful. If the check ever fails, there are much larger issues. Found-by: Coverity Scan #1452607 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I6d3e012542287511f61807075c998efd6d10441e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78614 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-25cbmem.h: Drop cbmem_possible_online in favor of ENV_HAS_CBMEMArthur Heymans
The macro ENV_HAS_CBMEM achieves the same as this inline function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6d65ca51c863abe2106f794398ddd7d7d9ac4b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-10-24drivers/wwan/fm: Wake up modem on PEWAKE# signal changePaweł Anikiel
Create an event handler for the PEWAKE# GPIO and notify the device driver to wake up the device. BUG=b:301150499 TEST=Compiled and tested on google/redrix: 1. Enable runtime suspend for linux mtk_t7xx driver 2. Wait for device to enter suspended state 3. Modem should be able to wake up driver, e.g. on SIM card insert/eject The interrupts should show up under /proc/interrupts as ACPI:Event Signed-off-by: Paweł Anikiel <panikiel@google.com> Change-Id: I32257689da85ea71f9de781093b3ede0cfe70a0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78297 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-23drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resumeBill XIE
After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1"), Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via bisect). Further inspection shows that DRAM training result of GM45 is stored in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume to restore, but it will be erased by sanitize_cmos(), which now clears both bank 0 and bank 1, leaving only "untrained" result restored, so s3 resume will fail. However, resetting CMOS seems unnecessary during s3 resume. Now, cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true. Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again with these changes. Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-20drivers/generic/bayhub: Add ACPI for BH720CoolStar
The Bayhub BH720 eMMC bridge is a fixed internal device, and needs to me marked as non-removable in order for Windows to properly recognize/ utilize the device. Add the necessary ACPI to be generated at runtime. TEST=build/boot/install Win11 on google/kahlee (liara) Change-Id: I0815abf1d2dc5cfe785dc04670ab91f2a6a1af23 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-20drivers/intel/fsp2_0: Support embedding a second FSP-M/FSP-SJonathon Hall
Support embedding a second FSP-M/FSP-S binary for an SoC that can select one at runtime. Comet Lake v1 and v2 are different steppings of the same SKUs, but they require different FSP binaries. Supporting both in a single build requires embedding both FSPs and selecting one at runtime based on the CPUID. This is desirable for a product that may have different CPU steppings but is not otherwise differentiated enough for a separate firmware build. An SoC can select PLATFORM_USES_SECOND_FSP to indicate that two FSP-M/ FSP-S binaries are required. Implement soc_select_fsp_m_cbfs() and soc_select_fsp_s_cbfs() to choose one based on platform-specific criteria. For Comet Lake, the first FSP is CML v1 and the second is CML v2, but in principle a platform could define any meaning for the first and second FSP. FSP-T is not affected, only one FSP-T can be embedded if FSP_CAR is used. Only one set of FSP headers is used, which is sufficient for Comet Lake v1/v2; their headers are equivalent. ADD_FSP_BINARIES, FSP_USE_REPO, and FSP_FULL_FD are supported for both sets of FSP-S/FSP-M but cannot be configured separately, both use the same configuration. Change-Id: Ied4c6c49a6bdf278238272edd47a2006258be8e5 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78344 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-05spi/winbond: Use spi_flash_bpbits in winbond_bpbits_to_regionDaniel Gröber
This consolidates the bp, tb, cmp, srp0 and srp1 variables under the new spi_flash_bpbits struct to allow treating them as one unit in the refactoring to follow. Change-Id: I2a1a77fb73047df733498c0fa8b8de1153c3b09e Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42113 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04{commonlib, libpayload}: Add "has_external_display" in coreboot tableSubrata Banik
This patch introduces a new coreboot table entry named "has_external_display" to understand if external display is attached. This information is useful to prevent graceful shutdown by payload when the LID is closed but an external display is present. This piece of the information will be gathered by coreboot and passed into the payload using this new entry aka external_display because payload (i.e., deptcharge) doesn't have any other way to determine if external display is available. BUG=b:299137940 TEST=Able to build and boot google/rex. w/o this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > System is powered off by depthcharge w/ this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > Booted to OS and device is alive/usable Change-Id: I0fa7eee4c5a50371a7a66c6ca1ac2c7d046d010b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77796 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-04drivers/intel/gma: Update port select bit definitionsSubrata Banik
This commit updates the port select bit definitions for the TRANS_DDI_FUNC_CTL registers in the Intel GMA driver to accommodate the changes introduced since TGL SoC. Specifically, the following changes were made: - Updated the DDI select bit definitions from 3-bits (bit 28-30) to 4-bits (bit 27-30). - Introduces `INTEL_GMA_VERSION_2` config to accommodate the port and pipe related differences between previous generation GMA register (TRANS_DDI_FUNC_CTL) to the current generation GMA register. This commit backports the change from the following upstream patch: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-3- lucas.demarchi@intel.com BUG=b:299137940 TEST=Able to build and boot google/rex. Change-Id: I815ffa90c2e235afd70baa7e3837e1f9af89b1b0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-10-02drivers/pc80/pc: Split up PS/2 keyboard/mouse ACPI definitionsJonathon Hall
Separate these so a mainboard can describe a PS/2 keyboard without a PS/2 mouse or vice-versa. Librem 11 has a PS/2 keyboard for the volume keys, but does not have a PS/2 mouse, and the presence of a mouse device can cause the cursor to appear on the desktop incorrectly. ps2_controller.asl remains since many boards include it, it now just includes the two new files. Change-Id: I13a4c2caf8dc9e5004b775dc0a9ac2488e39f184 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78096 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28drivers/tpm: Add return codes to TPM driverJon Murphy
Add additional failure mode reporting to the TPM driver to provide additional visibility into what failures are occurring. BUG=b:296439237 TEST=Verify code paths on Skyrim, ensure behavior is unchanged. BRANCH=None Change-Id: I77a653201acf1bddc1ed1e2af701c8d3dd4f0606 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77491 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-09-28treewide: convert to tpm_result_tJon Murphy
Convert TPM functions to return TPM error codes(referred to as tpm_result_t) values to match the TCG standard. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: Ifdf9ff6c2a1f9b938dbb04d245799391115eb6b1 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77666 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28treewide: convert to %#x hex printsJon Murphy
Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-25drivers/sof: Add support for rt5650 speaker/jack topologyMatt DeVillier
Enables correct identification of boards using rt5650 codec for either speaker or headset output (or both) by SOF Windows drivers. Change-Id: Ied9717955fcfca33bd63a34f3f6961deb045239c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78092 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-22drivers/sof: Add support for rt1019 speaker topologyMatt DeVillier
Enables correct identification of boards using rt1019 speaker amplifier by SOF Windows drivers. TEST=tested with rest of patch train Change-Id: I550dc8614e6e21d6d8715c12b7a4af35117497b5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-09-21drivers/generic/gpio_keys: Write device ACPI statusMatt DeVillier
Allows device to be hidden from OS (Windows) via devicetree 'hidden' keyword. TEST=tested with rest of patch train Change-Id: I81482bd19e24627cab80deed2b9057f45b6ac0a0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78037 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-18drivers/tpm: Make temp test value naming consistentJon Murphy
Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-18drivers/pc80/tpm: Rename tis_probe to tis_initJon Murphy
tis_init calls into tis_probe and returns an error or success, simplify the call stack by removing the current tis_init implementation and renaming tis_probe to tis_init. BUG=None TEST=builds Change-Id: I8e58eda66a44abf5858123cf9bcf620626f1b880 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-09-18drivers/crb: Update error messageJon Murphy
Update an invalid error message printed when the timer expires. BUG=None TEST=None BRANCH=None Change-Id: If6d35290e9cb8281cd33892dc052f49277474a59 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-09-15drivers/pc80/tpm: Silence warnings when CONFIG_TPM is unsetArthur Heymans
Add some noop device_operations for devices below chip drivers/pc80/tpm in the case CONFIG_TPM is unset. This avoids the warning "... missing read_resources" when probing all devices for resources. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ibc37642a8b5f37b95c648141e03025a04ffa36bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/77386 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-14x86: Add .data section support for pre-memory stagesJeremy Compostella
x86 pre-memory stages do not support the `.data` section and as a result developers are required to include runtime initialization code instead of relying on C global variable definition. To illustrate the impact of this lack of `.data` section support, here are two limitations I personally ran into: 1. The inclusion of libgfxinit in romstage for Raptor Lake has required some changes in libgfxinit to ensure data is initialized at runtime. In addition, we had to manually map some `.data` symbols in the `_bss` region. 2. CBFS cache is currently not supported in pre-memory stages and enabling it would require to add an initialization function and find a generic spot to call it. Other platforms do not have that limitation. Hence, resolving it would help to align code and reduce compilation based restriction (cf. the use of `ENV_HAS_DATA_SECTION` compilation flag in various places of coreboot code). We identified three cases to consider: 1. eXecute-In-Place pre-memory stages - code is in SPINOR - data is also stored in SPINOR but must be linked in Cache-As-RAM and copied there at runtime 2. `bootblock` stage is a bit different as it uses Cache-As-Ram but the memory mapping and its entry code different 3. pre-memory stages loaded in and executed from Cache-As-RAM (cf. `CONFIG_NO_XIP_EARLY_STAGES`). eXecute-In-Place pre-memory stages (#1) require the creation of a new ELF segment as the code segment Virtual Memory Address and Load Memory Address are identical but the data needs to be linked in cache-As-RAM (VMA) but to be stored right after the code (LMA). Here is the output `readelf --segments` on a `romstage.debug` ELF binary. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x000080 0x02000000 0x02000000 0x21960 0x21960 R E 0x20 LOAD 0x0219e0 0xfefb1640 0x02021960 0x00018 0x00018 RW 0x4 Section to Segment mapping: Segment Sections... 00 .text 01 .data Segment 0 `VirtAddr` and `PhysAddr` are at the same address while they are totally different for the Segment 1 holding the `.data` section. Since we need the data section `VirtAddr` to be in the Cache-As-Ram and its `PhysAddr` right after the `.text` section, the use of a new segment is mandatory. `bootblock` (#2) also uses this new segment to store the data right after the code and load it to Cache-As-RAM at runtime. However, the code involved is different. Not eXecute-In-Place pre-memory stages (#3) do not really need any special work other than enabling a data section as the code and data VMA / LMA translation vector is the same. TEST=#1 and #2 verified on rex and qemu 32 and 64 bits: - The `bootblock.debug`, `romstage.debug` and `verstage.debug` all have data stored at the end of the `.text` section and code to copy the data content to the Cache-As-RAM. - The CBFS stages included in the final image has not improperly relocated any of the `.data` section symbol. - Test purposes global data symbols we added in bootblock, romstage and verstage are properly accessible at runtime #3: for "Intel Apollolake DDR3 RVP1" board, we verified that the generated romstage ELF includes a .data section similarly to a regular memory enabled stage. Change-Id: I030407fcc72776e59def476daa5b86ad0495debe Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-09-14acpi: Comply with ACPI specification by making _STR unicode stringsCliff Huang
_STR should return Unicode string. From ACPI spec: 6.1.10 _STR (String) The _STR object evaluates to an Unicode string that describes the device or thermal zone. BUG=NA TEST=Check the changed _STR in SSDT to see if Unicode() macro is used Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I1f4b55a268c1dadbae456afe5821ae161b8e15a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77695 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-14drivers/intel/mipi_camera: Add DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOCJamie Ryu
This adds DRIVERS_INTEL_MIPI_SUPPORTS_PRE_PRODUCTION_SOC to provide the option to load pre-production or production signed IPU FW from IPU kernel driver. BUG=None TEST=Build rex and brya to check if the build passes without an error. Change-Id: Ib507bceb6fd85d8ed764df82db400526a10e4d6e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77854 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-12drivers/mipi: sta_himax83102: Completely pull GPW to VGL before TP termRuihai Zhou
The sta_himax83102 panel sometimes shows abnormally flickering horizontal lines. The front gate output will precharge the X point of the next pole circuit before TP term starts, and wait until the end of the TP term to resume the CLK. For this reason, the X point must be maintained during the TP term. In abnormal case, we measured a slight leakage at point X. This is because during the TP term, the GPW does not fully pull the VGL low, causing the TFT to not be closed tightly. To fix this, we completely pull GPW to VGL before entering the TP term. This will ensure that the TFT is closed tightly and prevent the abnormal display. BUG=b:299249186 BRANCH=corsola TEST=FW Screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I5dddaaa38917a65990c1474b657db5eb551940b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77692 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-11drivers: Remove space between function name and '('Elyes Haouas
Change-Id: I42e995952a72a23a5f3aeadf428ad13f25546854 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-09drivers/net/ne2k: Remove space before semicolonElyes Haouas
Also move the semicolon on next line. Change-Id: I68412407ec8c8f99c15f39b0ec08d4fb33eb1b3f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-08arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-07drivers/pc80/vga/vga_io: Remove unnecessary parenthesesElyes Haouas
Parentheses are not required. Change-Id: Iad1f766a3eb569af39030e43365e8a0a609f5944 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77706 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-09-07drivers/siemens/nc_fpga/nc_fpga: Remove space before '++'Elyes Haouas
Change-Id: I6ff11df45ddc396391efd651f9938e04646dc0d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77707 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-09-05drivers/wifi: Add PCI ID for Misty Peak WLAN moduleSubrata Banik
This patch adds support for Intel WIFI-7 series PCIe based WLAN module. Change-Id: Ia31fdb87e15b50471dc7664e42b1e2625ce1ac58 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-05drivers/wifi: Avoid camel casing in macro definitionSubrata Banik
Convert camel case macros to uppercase and underscore separated macros, such as: PCI_DID_CyP_6SERIES_WIFI -> PCI_DID_CP_6SERIES_WIFI PCI_DID_TyP_6SERIES_WIFI -> PCI_DID_TP_6SERIES_WIFI This makes the macros more consistent with the rest of the code and easier to read. Change-Id: I9c739aab93dc0d043a3c9d9ce799087952c1e20b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77644 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-09-05drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIsSubrata Banik
This patch refactors the existing MRC cache storing logic, which was spread between the ROM and RAM stages, into a single early MRC cache store stage. The only exception is when SoC user selects FSP_NVS_DATA_POST_SILICON_INIT to store MRC cache from ramstage (after FSP-S). It reverts all the boot-state logic previously used to locate and store MRC cache from NVS HOB into NVS because majority of the platform can potentially use the early MRC cache store with improved memory caching at the pre-RAM phase (with the ramtop implementation). The only exception is the Xeon SP platform, which currently locates the MRC cache post in FSP-S (at ramstage). Therefore, this patch provides an API to the FSP 2.x silicon init code to perform late storing of the MRC cache. In majority cases the updated logic, the romstage (post FSP-M) will attempt to save the MRC cache. Platform that selects FSP_NVS_DATA_POST_SILICON_INIT config performs the same operation post FSP-S. Depending on whether the MRC_STASH_TO_CBMEM config is enabled, the MRC cache will either be written directly to NVRAM at the romstage or stashed into CBMEM for a late NVRAM write at ramstage. Below table captures the change in the boot state w/ and w/o this patch for storing the MRC cache. Overall the goal is to ensure the platform behavior is remain unchanged before and after this patch. w/o this patch: | | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | BS_DEV_INIT | BS_DEV | BS_DEV | | DATA_POST | CHIPS_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | BS_PRE | BS_DEV | BS_DEV | | w/o above | DEVICE_ENTRY | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | | w/ this patch: | | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | Post FSP-S | BS_DEV | BS_DEV | | DATA_POST | (ramstage) | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | Post FSP-M | BS_DEV | BS_DEV | | w/o above | (romstage) | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | | BUG=b:296704537 TEST=Able to build and boot google/rex without any boot time impact. Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77556 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-09-04{drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` configSubrata Banik
This patch renames `SAVE_MRC_AFTER_FSPS` config to `FSP_NVS_DATA_POST_SILICON_INIT` to highlight the violation in the Xeon SP FSP implementation, where the FSP Silicon Init API produces Non-Volatile Storage (NVS) instead of the FSP-Memory Init API. According to the FSP 2.x specification (section 11.3), the FSP populates the NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and expects the boot firmware to parse the FSP_NON_VOLATILE_STORAGE_HOB after the FspMemoryInit() API in API mode. However, not all Intel SoC platforms that support the FSP 2.x specification adhere to this requirement. For example, the FSP binary for XEON SP platform produces NVS data (aka FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() API. Therefore, attempting to locate NVS data after the FspMemoryInit() API on these platforms would result in an error. The `save_mrc_data.c` implementation provides the required hooks to locate the NVS post FSP-Silicon Init and store into Non-Volatile Storage. BUG=b:296704537 TEST=Able to build and boot Intel Xeon SP w/o any functional impact. Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-09-01drivers/mrc_cache: Fix extra space at the beginning of lineSubrata Banik
Change-Id: Ic49cb6c67aa707efa6495788137b550683008868 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-30drivers/genesyslogic/gl9750: Add invert write protect polarityBen Chuang
Add an option to invert write protect polarity for GL9750. Change-Id: I5761f3066291a2400caecbecc79ae893f0a0c146 Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77403 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-29drv/intel/fsp2_0: Add FW Splash Screen event log entriesSubrata Banik
This patch adds logic for logging the FW splash screen event to the event log. There could be three possible scenarios as below: 1. Platform w/o FW splash screen (i.e., either HAVE_FSP_LOGO_SUPPORT or BMP_LOGO configs not enabled) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) not present in the event log. 39 | 2023-08-27 12:42:54-0700 | System boot | 12 40 | 2023-08-27 12:42:54-0700 | ACPI Wake | S5 41 | 2023-08-27 12:42:54-0700 | Wake Source | Power Button | 0 2. Platform w/ FW splash screen (i.e., both HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs are enabled) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is enabled in the event log. 34 | 2023-08-27 12:07:29-0700 | System boot | 11 35 | 2023-08-27 12:07:29-0700 | Firmware Splash Screen | Enabled 36 | 2023-08-27 12:07:31-0700 | ACPI Wake | S5 37 | 2023-08-27 12:07:31-0700 | Wake Source | Power Button | 0 3. Failed to render FW splash screen (due to any reason if FSP failed to render the splash screen) Expectation: Firmware Splash Screen (ELOG_TYPE_FW_SPLASH_SCREEN) is disabled in the event log. 43 | 2023-08-27 13:06:10-0700 | System boot | 13 44 | 2023-08-27 13:06:10-0700 | Firmware Splash Screen | Disabled 45 | 2023-08-27 13:06:11-0700 | ACPI Wake | S5 46 | 2023-08-27 13:06:11-0700 | Wake Source | Power Button | 0 BUG=b:284799726 TEST=Verify that the event shows up in the event log when the user selects the HAVE_FSP_LOGO_SUPPORT and BMP_LOGO configs to display the firmware splash screen. Change-Id: Ie9e09acff5443c31b881c300134bc0bb06c490c6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28drivers/spi/spi-generic: Fix typoElyes Haouas
'useable' -> 'usable'. Change-Id: Iad2e1ef97a5c98ffa6f33806bce5b77722e687e8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28drivers/spi/tpm: Remove space between function name and '('Elyes Haouas
Change-Id: I9804fcd9076b5a4813f099db0852a5af5ac36609 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77523 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-28drivers/lenovo/wacom: Remove space between function name and '('Elyes Haouas
Change-Id: Idc38c759489976cbdf51d9c4bb950ef6d470b93a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-28drivers/intel/gma: Remove space between function name and '('Elyes Haouas
Change-Id: Id7634099e40c0bf97944be124b494c41d6335ad7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-26vc/intel: Remove unnecessary Kconfig optionsMartin Roth
These Kconfig options were being used basically as #define statements, which is unnecessary. This isn't a good use of Kconfig options and would be better just as #defines if actually needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-25drivers/intel/fsp2/Makefile.inc: Deduplicate compression type checksFelix Singer
When LZMA compression is selected, then it's not needed to check if LZ4 compression is selected in addition. So instead of handling both cases separately, check for LZ4 only if LZMA is not selected. This applies to the cases of both, FSP-M and FSP-S. Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-19drivers/intel/fsp2_0: Fix extraneous text after else directiveSubrata Banik
Fix the issue by adding the "ifeq" keyword which makes the extraneous text a correct conditional directive. Change-Id: Id8a8aa7acfdaeb0549f417fb013b2535a7298045 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77286 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-18{driver, soc/intel/cmn/cse}: Refactor ISH FW Version implementationSubrata Banik
This patch uses the CSE firmware specific data to store Intel ISH firmware related information. Sending an ISH partition version information command on every boot cycle would impact the overall boot performance. This information is used by the auto-test framework to ensure the ISH firmware update is proper for in-field devices. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified ISH FW version is getting displayed across warm resets without impacting the boot time. Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-08-17drivers/intel/fsp2_0: Add configurable compression for logo cbfs fileSubrata Banik
This patch adds a new configuration option to allow the compression algorithm for the logo cbfs file to be specified. By default, the logo cbfs file is compressed using LZMA. However, enabling LZ4 compression can save ~2ms of boot time when the BMP_LOGO config is enabled. This patch verified that the logo cbfs file can be booted using either LZMA or LZ4 compression. BUG=b:284799726 TEST=Able to boot google/rex and verified firmware splash screen using either LZMA or LZ4 compression. Change-Id: Ib0aa5320632ae3f734004d2b1d495af11c2e1928 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-11drivers/i2c/sx9310: Set ACPI status to hidden (0xb)Matt DeVillier
Set the ACPI device status to hidden, since no driver is necessary or available under Windows. Linux is unaffected as it does not use the ACPI device status. TEST=build/boot Win11 on google/akemi Change-Id: Ib1e274084400fa47e483267d331e632ceb5be757 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75178 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT bufferSubrata Banik
This patch adds an API to convert BMP images into GOP BLT buffers for Intel FSP-S. This is required to display the OEM splash screen at pre-boot phase. Previously, Intel FSP-S had provision to consume the *.BMP file as is. However, starting with the Alder Lake platform, Intel FSP has dropped this conversion logic and expects the boot firmware to pass the BLT buffer directly. This patch implements the conversion logic in coreboot. BUG=b:284799726 TEST=Able to build and boot google/rex Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-08-11drivers/pc80/rtc: Hide bank register ports from menuArthur Heymans
It makes no sense to expose these symbols to the user in the menu. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I6eb78d12afdc0828bf5e2d305f033d2f0cf4622a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
2023-08-10drivers/uart/pl011: Fix regwidthArthur Heymans
Width of registers are always dwords on pl011, not bytes. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I955319d31bba5c0cd4d50f2b34111d51fea653ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/76883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-10drivers/spi: Remove SPI_FRAM_RAMTRON from makefileMartin Roth
This is unused - other references were removed long ago. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia7a65f54c736db20a5440795fdfaa8be31ef971f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-06drivers: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the drivers directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8442bc18ce228eca88a084660be84bcd1c5de928 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68980 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03drivers/intel/gma/Kconfig: Remove unused INTEL_GMA_OPREGION_2_0Elyes Haouas
Change-Id: I9241d713fb8cc26c768746c8e442b46292036d20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76694 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01drivers/usb/ehci.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-01drivers/mipi: sta_ili9882t: Change TReset-CMD from 1.1 ms to 20 msRuihai Zhou
In the datasheet of ILI9882T [1] section 3.11 Power On/Off Sequence, the TReset-CMD (Reset to First Command in Display Sleep In Mode) should be larger than 10ms, but it's 1.1ms now. This may cause abnormal display as some commands may be lost during power on. Fix this and leave some margins by increasing TReset-CMD to 20ms. Also, to align with the kernel driver structure starry_ili9882t_init_cmd, add 20ms delay at the end of command. [1] ILI9882T_Datasheet_20220428.pdf BUG=b:293380212 TEST=Boot and display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Ifdcaf0e34753fc906817c763f1c8e7389448d1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76766 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-01src/drivers/vpd/vpd.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Iab55c57ee5cac60911c9fe4cee8d86a252bde372 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76839 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31drivers/i2c/generic: Add option to set ACPI subsystem IDMatt DeVillier
Change-Id: I7c9c938bd20d36be8fdfb0d95bb58a7259650693 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-31drivers/intel/fsp2_0/fsp_timestamp.c: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I03c21e180e9e399e5cb451bf3b9cfb6484cab68b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76778 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-30drivers/intel/gma/intel_bios.h: Use C99 flexible arraysElyes Haouas
Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I80b4b2df4a38dcbb28d928018446e91acae90ee6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-20drivers/mipi: Modify INX_P110ZZD_DF0 panel initialization codeCong Yang
There is a problem of screen shake on the old panel[1]. So increase the panel GOP component pull-down circuit size in hardware, and update the initialization code at the same time. The new initialization code is mainly adjusted for GOP timing. When Display sleep in, raise all GOP signals to VGHO and then drop to GND. In order to be consistent with the current panel model, let's rename this file. [1]: INX old panel product number is HJ110IZ-01A-B1, and the new panel product number is HJ110IZ-01A-B2. We have recalled the shipment old panel. BUG=b:270276344 BRANCH=trogdor TEST= test firmware display pass Change-Id: I2b2534afee1ed700c39d3c360aafd685b63ccbfb Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-17drivers/pc80/tpm: Add Infineon SLB9672 IDTim Crawford
Allows the new Infineon TPM chip used on Clevo laptops to be recognized. Change-Id: I2ee31b787d80c0b9c24c748b1b28906a22a1dee7 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-14drivers/uart/oxpcie: Fix broken console outputNicholas Chin
The OxPCIe952 serial cards currently fails after entering postcar, since the state of oxpcie_present is not maintained from previous stage. As a quick work-around test the expected UART register space to see if anyone decodes the address. Change-Id: I5601034be6e413616fb3433c894fb008a3e02138 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74597 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14drivers: mipi: Fine tune STA_ILI9882T panel HBP and HFPRuihai Zhou
coreboot logs the error below, since the value of hporch is too small. Increasing hbl from 80 to 174, and hso from 40 to 72 to revise the HBP(Horizontal Back Porch) and HFP(Horizontal Front Porch). After revising this, the actual measurement frame rate is 60.1Hz. [ERROR]HFP plus HBP is not greater than d_phy, the panel may not work properly. BUG=b:284812193 TEST=cbmem -c | grep "ERROR" and measure frame rate Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I7de5984ce8aec12d8ebe292974e05776835330d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76218 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12pc80/tpm: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I40b8482f41e8fece55fd60fec7ec3f63f83bd030 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76280 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12ast2050: Fix reserving VGA regionArthur Heymans
Reserving resources needs to have inclusive region ends. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I88a09d205ef9699de7f18e0a2f33c9ad3ce9fa36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76279 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-07drivers/intel/fsp2_0: Remove BUILD_TIME_STAMP_SIZE macroRonak Kanabar
Remove BUILD_TIME_STAMP_SIZE macro from coreboot because FSP 3223 version have BUILD_TIME_STAMP_SIZE macro defined as part of `FspProducerDataHeader.h`. Ref change: 9c28ab1d1a vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80 BUG=b:285110116 TEST=Able to build google/rex. Change-Id: I52707adf1aa6dadca8dcf82102f76916a0cfe346 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-06drivers/tpm: Move tis_plat_irq_status to cr50 driverGrzegorz Bernacki
tis_plat_irq_status() function is used only by Google TPM. It should be moved to drivers/tpm/cr50.c. The name of the function was changed to cr50_plat_irq_status(). BUG=b:277787305 TEST=Build all affected platforms Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-07-03drivers/spi_flash: Always exit 4-byte address mode when memory-mappedFred Reitberger
Always send the Exit 4-Byte Address Mode (E9h) command before the first access to the SPI flash in all stages when the SPI flash is memory-mapped. This is useful for x86 mainboards that do not access SPI flash in bootblock yet still need to exit 4-byte addressing mode in romstage or ramstage. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/76093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-23Makefile.inc: don't add fmap_config.h dependency twiceFelix Held
Commit d054bbd4f1ba ("Makefile.inc: fix multiple jobs build issue") added a dependency on $(obj)/fmap_config.h to all .c source files in all stages, so it's not needed any more to add it as a dependency to files that include fmap_config.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76002 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23{commonlib/drivers}: Have option to store MRC version inside CBMEMSubrata Banik
This patch introduces CBMEM ID to store the MRC version (similar to existing implementation that stores the FSP-M version inside CBMEM ID) inside cbmem so the version information is available across the different coreboot stages. For example: * romstage: Use the CBMEM ID version information to check if the MRC cache is valid and need to erase the MRC cache * ramstage: Use the CBMEM ID to store the MRC cache into the non-volatile space. BUG=b:261689642 TEST=Able to build and boot google/rex and dump the MRC version as below. cbmem --list CBMEM table of contents: NAME ID START LENGTH ... 21. MRC VERSION 5f43524d 75ffeb60 00000004 ... localhost ~ # cbmem -r 5f43524d | hexdump 00000000 01 12 07 00 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I91f735239b33c6f8ba41c076048903e4b213c6a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75921 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23driver/intel/fsp2_0: Add support to store MRC cache using MRC versionSubrata Banik
This patch uses the "generic" variable name as "version" while storing the MRC cache data instead referring to the FSP-M version or MRC version. Hence, updated all the instances of `fsp_version/fspm_version` with `version`. Also introduces the new option to the MRC cache version that allows SoC users to store the MRC cache version based on the supported EDK2 version. Intel FSP built with EDK2 version 202302 onwards has support to retrieve the MRC version by directly parsing the binary. Additionally, added the helper function `fsp_mrc_version()` and corresponding header file to read the MRC version from the FSP binary. BUG=b:261689642 TEST=Able to build and boot google/rex and google/omnigul. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia8af53aed674ad4a3b426264706264df91d9c6b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75920 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kapil Porwal <kapilporwal@google.com>