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2024-10-09drivers/usb/acpi: Move the CNMT Mutex to USBSean Rhodes
The Intel Bluetooth driver can be combined with either CNVi, or full PCI wireless cards such as the AX210. Move it to the USB code so it can be used by either or. Change-Id: Ib456b1870501182b2d8788e5d53bbf4d7981f91b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84627 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-09drivers/usb/acpi: Move Intel Bluetooth functions to separate fileSean Rhodes
The code for Intel Bluetooth is unrelated to all other devices, and needs to grow in size - move it to another file. Change-Id: I65ccb9f2fd95b07fa63866485920539adc474873 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84625 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07drivers/soundwire: Support Realtek ALC721 codecVarun Upadhyay
This change updates SoundWire driver to support ALC721 audio codec based on config flag. reference datasheet: Realtek ALC721-VA0-CG Rev. 0.34 BUG=b:368495490 TEST=This driver was tested on Intel RVP with Add-on ALC721 codec card by testing soundcard binding/devices are detected and check for audio playback. Change-Id: I1022ee91b16374d0d4d07e5198226595d61403a6 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Signed-off-by: Naveen M <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-07drivers/soundwire: Unify SoundWire ALC codec names under ALC 7 SeriesVarun Upadhyay
This change removes individual conditional blocks for specific ALC codec models and introduces a common name for the entire ALC 7 Series configuration. TEST=Build and test with DRIVERS_SOUNDWIRE_ALC_BASE_7XX. Change-Id: Ib7c33351207df472cd11243244063b007c24d9bf Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-02drivers/tpm: Remove unused 2nd argument in FUNC methodSean Rhodes
The method "FUNC" allows 1 argument, so remove the incorrectly referenced and unused second arguemnt. This fixes: ToInteger (Arg1, Local1) Error 6006 - ^ Method argument is not initialized (Arg1) Change-Id: If5e402579a2caff169e12253e5d9c2c493902ec7 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-02soc/intel: Deprecate SoC-specific global reset status configsSubrata Banik
This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X` Kconfigs, as they are no longer necessary for handling FSP global reset requests. Previously, these Kconfigs were used to select a specific 32-bit reset status code. However, with the introduction of FSP 2.4 and 64-bit interfaces, the global reset status code can now vary between architectures. To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET` config to a common default value (depending upon most commonly used global reset status code) based on the interface: - 0x40000003 for 32-bit FSP interfaces - 0x4000000000000003 for 64-bit FSP interfaces This default can be overridden if an FSP implementation uses a different status code (for example: Apollo Lake selects different FSP reset status code as 0x40000005). By removing the SoC-specific configurations, this change simplifies global reset handling and ensures compatibility across different FSP versions and platforms. Below table shows the relationship between Platform, FSP and FSP Global Reset Status: +-----------------+--------------+-------------------------+ | Platform | FSP | Global Reset Status | +-----------------+--------------+-------------------------+ | Alder Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Apollo Lake | 32-bit | 0x40000005 | +-----------------+--------------+-------------------------+ | Cannon Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Elkhart Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Jasper Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Meteor Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Sky Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Tiger Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Panther Lake | 64-bit | 0x4000000000000003 | +-----------------+--------------+-------------------------+ BUG=b:347669091 TEST=Verified FSP requested global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. w/ 32-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 40000003 FSPS, status=0x40000003 FSP: handling reset type, status=0x40000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` w/ 64-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 3 FSPS, status=0x4000000000000003 FSP: handling reset type, status=0x4000000000000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-01drivers/usb/acpi: Add a Power Resource for Intel BluetoothSean Rhodes
Add a Power Resource for Intel Bluetooth, that can reset the Bluetooth using the delay configured in the DSM. Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84146 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30drivers/i2c/at24rf08c: Disable DRIVER_LENOVO_SERIALS by defaultNicholas Sudsgaard
This should be the sane default, as having this option enabled when the AT24RF08C (Asset Identification EEPROM) is not present on the mainboard can cause SMBIOS table entries to become "*INVALID*". This can, for example, result in strange hostnames when an OS installer uses SMBIOS information to automatically generate one. On the other hand, the coreboot generated SMBIOS tables will at least always contain basic information. Therefore, this driver should be treated as an enhancement rather than a default. Currently, the following mainboards have this option disabled: - ThinkCentre M710s - ThinkCentre M700 / M900 Tiny - Haswell ThinkPads - ThinkPad T440p - ThinkPad W541 Therefore, we can remove this option entirely on these mainboards. Note that there may be other mainboards which do not have this chip present but still have the option enabled. However, this requires a more detailed investigation which would be out of scope of this change. TESTS=Timeless builds on lenovo mainboards produce the same binary. config INCLUDE_CONFIG_FILE default n Was temporarily added to `mb/lenovo/Kconfig` during these tests, as while the configuration does not change, the order of entries do. Therefore, technically producing a different binary when included. Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-30libgfxinit: Allow to configure screen rotationNico Huber
This allows to configure a default screen rotation in 90-degree steps. The framebuffer contents will then be displayed rotated, by the same amount in the other direction; i.e. if you turn the screen to the left, the picture has to be rotated to the right to accommodate. This is only supported by libgfxinit from Skylake / Apollo Lake on (earlier GPUs didn't support the 90-degree steps anyway) and it only works with the linear-framebuffer option. Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-27driver/intel/ish: Add config to indicate the presence of ISH MAIN firmwareJayvik Desai
This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware. The ISH MAIN firmware is located in rootfs, hence we no longer need to store the ISH BUP version in the CSE partition. When this config is enabled, fetching the ISH BUP version from the CSE firmware partition is skipped. BUG=b:360144613 TEST=Local build successful and tested on trulo by toggling the config. Enabling this config skips printing the ISH version in cbmem. Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-09-26drivers/aspeed/common: Add AST2600 supportPatrick Rudolph
Add support for AST2600 as found on Intel Archer City CRB by using the code found on Linux's ast drm driver. While on it do minor modifications found on the Linux drm driver that also affect the other ast chips. New log messages: [INFO ] ASpeed AST2050: initializing video device [INFO ] ast_detect_chip: VGA not enabled on entry, requesting chip POST [INFO ] ast_detect_config_mode: Using P2A bridge for configuration [INFO ] ast_detect_chip: AST 2600 detected [INFO ] ast_detect_chip: Analog VGA only [INFO ] ast_driver_load: dram MCLK=890316000 MHz type=3 bus_width=16 size=01000000 [ERROR] No header found [INFO ] ast_select_mode: Failed to decode EDID [DEBUG] Assuming VGA for KVM [DEBUG] AST: Display has 1024px x 768px [DEBUG] Using framebuffer 1024px x 768px pitch 4096 @ 32 BPP [INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32 [INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0x94000000 [INFO ] ASpeed high resolution framebuffer initialized TEST: Booted on Intel/ArcherCity CRB and used the UEFI firmware menu over KVM using native graphics init. Change-Id: I3d2d58d493706673c1b2ba4953967b1641bd6395 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-07drivers/intel/fsp2_0: Consolidate `BUILDING_WITH_DEBUG_FSP` optionSubrata Banik
Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly improves the option's prompt and help text. TEST=Built and booted google/rex successfully. Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-07drivers/intel/fsp2_0: Add Kconfig option to control MBP HOB creationSubrata Banik
This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. Disabling this option can improve boot time on platforms that do not utilize the MBP HOB, such as ChromeOS devices. The option is disabled by default on ChromeOS and enabled by default on other platforms. On ADL-P based platforms, this option is forced to be enabled as ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config from MTL and TGL config file. TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when it is disabled. Also verified that the system boots successfully in both cases. Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-09-06drivers/i2c/generic: Remove erroneous acpigen_pop_lenSean Rhodes
There are one too many acpigen_pop_len calls in the code to generate the ROTM; remove one to fix an EMERG warning: [EMERG] ASSERTION_ERROR: file `src/acpi/acpigen.c`, line 38 The extra acpigen_pop_len() call was added commit 45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package"). Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-09-02drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_infoArthur Heymans
GCC LTO found this. Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84056 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-02drivers/usb/acpi: Add DSM for Intel BluetoothSean Rhodes
Add support for creating a DSM Method for Intel Bluetooth that is outlined in Intel's connectivity integrated guide (which has no document number). It supports two GUIDs: Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Tile Activation Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Bluetooth reset timing Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-30drivers/efi/uefi_capsules.c: coalesce and store UEFI capsulesSergii Dmytruk
How it approximately works: (During a normal system run): 1. OS puts a capsule into RAM and calls UpdateCapsule() function of EFI runtime 2. If applying the update requires a reboot, EFI implementation creates a new CapsuleUpdateData* EFI variable pointing at the beginning of capsules description (not data, but description of the data) and does a warm reboot leaving capsule data and its description in RAM to be picked by firmware on the next boot process (After DEV_INIT:) 3. Capsules are discovered by checking for CapsuleUpdateData* variables 4. Capsule description in memory and capsule data is validated for sanity 5. Capsule data is coalesced into a continuous piece of memory (On BS_WRITE_TABLES via dasharo_add_capsules_to_bootmem() hook:) 6. Buffer with coalesced capsules is marked as reserved (On BS_WRITE_TABLES via lb_uefi_capsules() hook:) 7. coreboot table entry is added for each of the discovered capsules (In UEFI payload:) 8. CapsuleUpdateData* get removed 9. coreboot table is checked for any update capsules which are then applied Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-08-27drivers/intel/opregion.c: Also set vbt_size if size is 0Arthur Heymans
Make sure size vbt_size is initialized. GCC LTO warns about this. Change-Id: I4fcc6c02f898640e9b40d769e1165a4a0fb0fdf2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84041 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-08-23region: Turn region_end() into an inclusive region_last()Nico Huber
The current region_end() implementation is susceptible to overflow if the region is at the end of the addressable space. A common case with the memory-mapped flash of x86 directly below the 32-bit limit. Note: This patch also changes console output to inclusive limits. IMO, to the better. Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-08-20drivers/soundwire: Support Realtek ALC722 codecAnil Kumar
This patch adds SoundWire driver to support ALC722 audio codec. The existing ALC711 codec driver is refactored to include support for ALC722 device based on config flag. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc711 register "desc" = ""Headset Codec"" device generic 0.1 on end end reference datasheet: Realtek ALC722-CG ver. 0.56 TEST=This driver was tested on Intel RVP with on board ALC722 codec by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Test soundcard binding works and devices are detected and check for audio playback using speaker output. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-08-19drivers/efi: add optional ESRT-friendly coreboot table tagSergii Dmytruk
EFI System Resource Table (ESRT) is an informational structure that reports basic details about current system or device firmware. This is chiefly used to perform firmware updates. New CONFIG_DRIVERS_EFI_FW_INFO is off by default, enabling it adds DRIVERS_EFI_FW_{GUID,VERSION,LSV} to be used to specify firmware version/update information. Existing forms of versions wouldn't be sufficient because there is no universal way of converting string versions to 32-bit unsigned integers and there are no GUIDs or lowest supported versions. Change-Id: Ic1b768d7bed43edf7ca8e41552087734054de033 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83421 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: coreboot org <coreboot.org@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-15include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaroundFelix Held
Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since it was defined as unsigned long in AGESA.h, a workaround was needed in cpu/amd/mtrr.h to not have the build fail due to a non-identical redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround without reaming the defines isn't trivially possible, since the stoneyridge romstage.c still ends up including both definitions which can't be easily worked around. Now all non-vendorcode coreboot code uses TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and TOP_MEM2 to avoid this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2024-08-12drivers/intel/fsp2: Add config for FSP uGOP eSOLJayvik Desai
This patch introduces a new configuration option, FSP_UGOP_EARLY_SIGN_OF_LIFE, to the FSP driver. This enables uGOP support using FSP-M for the early sign-of-life feature in SOC. BUG=NA TEST=Able to build google/rex and checked the config in output. Change-Id: Ic0426ff7974a141ae9188b0098677b4cc97aee36 Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-08-11region: Introduce region_create() functionsNico Huber
We introduce two new functions to create region objects. They allow us to check for integer overflows (region_create_untrusted()) or assert their absence (region_create()). This fixes potential overflows in region_overlap() checks in SMI handlers, where we would wrongfully report MMIO as *not* overlapping SMRAM. Also, two cases of strtol() in parse_region() (cbfstool), where the results were implicitly converted to `size_t`, are replaced with the unsigned strtoul(). FIT payload support is left out, as it doesn't use the region API (only the struct). Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Ticket: https://ticket.coreboot.org/issues/522 Found-by: Vadim Zaliva <lord@digamma.ai> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-08-06drivers/{crb,pc80/tpm}: Drop conflicting tpm_config_t typedefMichał Żygowski
When both CRB and pc80 TPM drivers are compiled in, building fails because the tpm_config_t typedef has two incompatible definitions. Given that typedefs are discouraged by the project's coding style, simply get rid of the tpm_config_t typedef. TEST=Compile MSI PRO Z690-A target with CRB and PC80 TPM chips enabled in devicetree. Change-Id: Id41717e265362303a17745303a907c9c8f4f4e12 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82057 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-08-02i2c/drivers/generic: Return ROTM in a packageSean Rhodes
The ROTM method should return a package: ``` Name (RBUF, Package (0x03) { "0 1 0", "1 0 0", "0 0 1" }) Return (RBUF) ``` Adjust the acpigen to do this. Change-Id: Id493f6955c1d0dc3449402262a8575091a828226 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-07-29i2c/drivers/generic: Add support for including a CDMSean Rhodes
Chip Direct Mapping is exclusive to Windows; it allows specifying the position where a chip is mounted. There are 8 positions and a _CDM method should return 0xabcd0X, where X is the position. Tested by booting Windows 11 on the StarLite Mk V, rotating the device and checking the orientation is correct, where previously, it was inverted. Change-Id: If70c25288d835df7064b4051c43abeb2d6531f3b Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81409 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMDYu-Ping Wu
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A is bank selection. Since the MC146818 driver accesses VBNV via Bank 0, the value set in cmos_init() must not contain that bit. To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add an static assertion about the bank selection for AMD. Note that the kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157 BUG=b:346716300 TEST=none BRANCH=skyrim Change-Id: I6122201914c40604f86dcca6025b55c595ef609e Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for ISHSubrata Banik
This patch adds new ISH PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the ISH driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I280cfdb50e8d453e957cb4bccff3a7ee2fb3bd10 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83505 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-18drivers/pc80/rtc/mc146818rtc: Use macros for CMOS addressesYu-Ping Wu
Replace integer literals with macros for CMOS addresses for readability. Change-Id: I454662c90fabb41af864728febdefa57f5ff2cb2 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-07-15drivers/wifi: Support Radio Frequency Interference MitigationJeremy Compostella
The 'Radio Frequency Interference Mitigation' DSM function 11 provides the desired status of the RFI mitigation. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:352768410 TEST=ACPI DSM Function 11 reflects the value of the SAR binary Change-Id: I02808b0ce6a0a380845612e774e326c698ad1adc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-15drivers/wifi: Support Energy Detection ThresholdJeremy Compostella
The 'Energy Detection Threshold' DSM function 10 provides the desired status of the EDT optimizations. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:352788465 TEST=ACPI DSM Function 10 reflects the value of the SAR binary Change-Id: I2e2e9d4f5420020bd7540cb36fa8aebfedf62285 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-11drivers/qemu: Clarify config option name for QEMU display resolutionAlper Nebi Yasak
A previous commit splits out Cirrus display support from Bochs display support, with both using the pre-existing Bochs config options for the requested display resolution. Rename these config names to clarify they are not only specific to the Bochs display driver. Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11drivers/qemu: Split Cirrus display support from Bochs display supportAlper Nebi Yasak
QEMU's Cirrus display device is supported along with the Bochs driver since commit 7905f9254ebc ("qemu: cirrus native video init"). It is no longer the default since QEMU 2.2. The code supporting it can work independently of the Bochs display driver and depends more heavily on port I/O and VGA support code, so split it from that code to make it easier to support the Bochs driver in other architectures. Change-Id: Ic9492b501ed4fdcbda6886db60b1e5348715e667 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-07-11console/i2c_smbus: Allow to send data w/o register offsetNico Huber
Not every I2C target requires a register address. Not sending one for every console char saves us a lot of overhead. Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82762 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-04drivers/spi/acpi: Update generic property listKun Liu
Update generic property list for build test result fail https://qa.coreboot.org/job/coreboot-gerrit/259702/ BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iecd8573343706184dce5edfc12fe7a143390e0e9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83301 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-07-03drivers/wifi: Support 320Mhz Bandwidth Enablement per MCCPoornima Tom
Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support Bluetooth Regulator Domain SettingsJeremy Compostella
The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability to utilize increased device Transmit power capability for Bluetooth applications in coordination with Wi-Fi adhering to product SAR limit when Bluetooth and Wi-Fi run together. This commit introduces a `bluetooth_companion' field to the generic Wi-Fi drivers chip data. This field can be set in the board design device tree to supply the bluetooth device for which the BRDS function must be created. This feature is required for Meteor Lake rex karis variant. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/intel/ish: Skip ISH version call if CSE sync is done by payloadSubrata Banik
This patch skips the ISH firmware version print when CSE sync is done by payload. The payload is responsible to dump the ISH version as ISH version resides into the CSE boot partition table. BUG=b:305898363 TEST=Able to build google/rex. Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-01drivers/spi/acpi: Add generic property listKun Liu
The touchscreen vendor (Goodix) needs to use this value (hid-report-addr) in the touch driver, and this value needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table. BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-01drivers/mipi: Add support for LCE_LMFBX101117480 panelYang Wu
Add STA panel LCE_LMFBX101117480 serializable data to CBFS. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf About the init code, we communicated with the vendor through the datasheet to confirm the writing method of each register value. BUG=b:331870701 TEST=build and check the CBFS includes the panel BRANCH=None Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-06-27drivers/wifi: Support Wi-Fi 7 11be EnablementRavi Sarawadi
Add 802.11be (aka. Wi-Fi 7) enable/disable support based on document 559910 Intel Connectivity Platforms BIOS_Guidelines revision 8.3. There are countries where Wi-Fi 7 should be disabled by default. This adds capability for OEM to enable or disable by updating the board specific Specific Absorption Rate (SAR) binary. BUG=b:348345300 BRANCH=firmware-rex-15709.B TEST=SSDT dump shows that the _DSM method returns the value supplied by the SAR binary for function 12 Change-Id: Ifa1482d7511f48f5138d4c68566f07ce79f37a7a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-14tpm: Add Ti50 OpenTitan DID_VIDJett Rink
The OpenTitan HW implements the same firmware interface as the Ti50 H1D3C hardware variant; it just has a different DID_VID. Allow this new DID_VID to be recognized correctly. BUG=b:324940153 Change-Id: Iaacf6d88bc6067948756c465aac1cd8b24ecae1f Signed-off-by: Jett Rink <jettrink@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83033 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-13drivers/gfx/generic: Don't set DOD constraints when generating device addressMatt DeVillier
When dynamically generating the DOD (Display Output Device) device address (_ADR), don't set the DOD constraint flags; only set them when using the address value to generate the DOD package. This fixes ACPI brightness control functionality under Windows 11. Before: Name (_ADR, 0x80010400) After: Name (_ADR, 0x00000400) TEST=build/boot Win11 on google brya (banshee), ensure display brightness controls present and functional. Ref: ACPI Spec 6.5 Appendix B.6.1 - _ADR Change-Id: I1d710c6e55e6cb1d20d580bd784221ee1482b871 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83025 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-05Xeon-SP boards: Factor out OCP VPD `get_cxl_mode()` implAngel Pons
There's two copies of the `get_cxl_mode()` function to map the OCP VPD value to the values expected by platform code. As this is unnecessary, have a single copy of this function in the OCP VPD driver code. As the `get_cxl_mode()` function is Xeon-SP only, keep it in a separate file. This change simplifies things for boards using OCP VPD for CXL and has no impact for boards *not* using OCP VPD: - Boards not using OCP VPD can still define get_cxl_mode() in mainboard code as needed, just like they were able to do before. - Boards using OCP VPD but without CXL (`SOC_INTEL_HAS_CXL` is not enabled), this code won't get compiled in at all (see `Makefile.mk`). - Boards using OCP VPD and CXL will automatically make use of this `get_cxl_mode()` definition, which should be the same for all boards. It is possible that this may need to be expanded/adapted in the future, which is easy to handle in a follow-up commit when the need arises. TEST=Build and boot on intel/archercity CRB Change-Id: I935c4eb5b2392e2d0dc01b9f66d46c79b8141ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82224 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-05-31soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 buildsAppukuttan V K
EnableMultiPhaseSiliconInit upd is deprecated and has been removed starting with v2.4 of FSP specification. Multi-phase silicon initialization is mandatory for all FSP implementations compliant to v2.4. The following modifications are made: - In fsp_params.c and silicon_init.c EnableMultiPhaseSiliconInit update is guarded so that it will get included only if FSP2.4 is not selected. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <stddef.h>Elyes Haouas
Change-Id: I7d7ad562eeff7247b7377b6570d489faee0aeda0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82669 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-17cr50: Replace "cr50" to "GSC" in debug messagesTyler Wang
The cr50.c file currently prints "cr50" in debug messages no matter the system is using Cr50 or Ti50. This can be confusing for developers. This patch replaces "cr50" with "GSC" in debug messages. Using "GSC" makes the messages more clear and easier to search via `grep`. BUG=none TEST=Build and test on karis Change-Id: I21f66cf8b608ca4e4dc82d7a55a851ec996c8bb3 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82420 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2024-05-14soc/intel/common: Add Panther Lake DIDsSaurabh Mishra
Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I941d6e1c8a697234b8e64a2523e60587897d7f7a Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81848 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-11driver/intel/fsp2_0: Update soc_binding.h for coreboot compatibilitySubrata Banik
Included <efi/efi_datatype.h> to address coreboot style header definitions rather using EDK2 header <Base.h>. TEST=Able to build google/rex0. Change-Id: I66559872c8d137d1baef5860fb98cad2a5214368 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82265 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-10drivers/mipi: Update init code for IVO_T109NW41 panelZhongtian Wu
1. VCOM OTP burning, initial code Settings can be deleted, B6h 2. Fine-tune VGH, VGL, VGHO, VGLO voltage, B1h PA6 3. Boot CLK performance change: add E9h, C7h, E9h 4. Extend TFT life: D5h PA25~PA32,D3h PA1~PA5; 5. Gamma optimization: E0h 6. Improve picture quality, add EQ: D2h to CLK 7. Press mura to improve and modify B1h PA4 and PA5 BUG=b:320892589 TEST=boot ciri with IVO_T109NW41 panel and see firmware screen Change-Id: I13421660faba9ef8e33a51c5ab28aeb1388aff40 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82240 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2024-05-06drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to muxWon Chung
Copy ACPI _PLD values from USB ports to corresponding USB muxes so that the kernel can create symlinks between Type C connectors and corresponding USB muxes. This symlink will be used to let userspace be able to modify the USB role without knowing ACPI topology for the device. BUG=b:121287022 b:329657774 TEST=emerge-${BOARD} coreboot then check ACPI table on DUT Change-Id: If27042cc995ef188f8a3e31444e994318ff98803 Signed-off-by: Won Chung <wonchung@google.com> Tested-by: Emilie Roberts <hadrosaur@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81089 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Emilie Roberts <hadrosaur@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-06drivers/intel/mipi_camera: Add CSI2 Data Stream Interface GUIDCoolStar
Required in SSDB for Windows drivers. Tested on google/brya (kano) and verified Intel Webcam shows up to Windows as a camera source Change-Id: Id6089f6bd841333882e28de9307fe5e48e368d02 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82068 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-03drivers/wifi/generic: Fix a typo on symbolElyes Haouas
WIFI_MTCL_CBFS_FILEPATH is now used. Change-Id: Icdd0332ae9c56a54596a775c0a9aa7b9f8d6738c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-05-03drivers/intel/fsp2_0: Release bmp_logo during OS_PAYLOAD_LOAD stageKarthikeyan Ramasubramanian
bmp_load_logo() loads the custom logo.bmp file into CBMEM. This cbmem buffer is released after FSP-S init is complete. In certain platforms, the logo file is displayed during PCI enumeration. This means the logo buffer is used after it is released. Fix this issue by releasing the logo buffer when the coreboot has finished loading payload. During S3 scenario CBMEM is locked, bmp logo is not loaded and hence the release is a no-op. BUG=b:337144954 TEST=Build Skyrim BIOS Image and boot to OS. Ensure that the chromeOS boot logo is seen without any corruption. Change-Id: Id27cf02de04055075e7c1cb0ae531dee8524f828 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82121 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-05-02soc/intel/xeon_sp: Add get_cxl_modeShuo Liu
Configuration variable implementation (VPD, et al) is regarded to be mainboard specific and should not be bounded to SoC codes. Add get_cxl_mode so that SoC codes do not need to get this configuration from VPD any more. TEST=Build and boot on intel/archercity CRB with no significant log differences Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-30drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4Jeremy Compostella
Sets`PLATFORM_USES_FSP2_X86_32' to `n' by default if FSP 2.4 is enabled as 64-bits FSP should be norm moving forward. BUG=b:329034258 TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80323 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-30drivers/intel/fsp2_0: Add dedicated caller function for ap procedure callsAppukuttan V K
Add FSP 2 Multi Processor Platform Initialization module a function indirection to ensure that efi_ap_procedure functions are called with the appropriate C calling convention. BUG=b:329034258 TEST=Verified both x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: I64e65b2941207375d5e27c84aa26061e7e72a7f6 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81663 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-30drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_headerAppukuttan V K
Same fsp_header struture is being used for x64 and x32 modes and hence dropping the x64 assertion. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81662 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-30drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes alignedAppukuttan V K
- Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned in x86_64 mode.This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP heap buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. This alignment is consistent for both x86_64 and x86_32 modes to simplify the implementation. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81661 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-04-26drivers/pc80/tpm: Disable device if TPM not presentMichał Żygowski
If the TPM is not detected in the system it may mean it is inactive due to enabled ME with active PTT. In such case, the chipset will route the TPM traffic to PTT CRB TPM on Intel systems. If TPM is not probed, disable the PC80 TPM device driver, so that coreboot will not generate improper SSDT ACPI table. Change-Id: I05972ad74a36abaafa2f17a16f09710550a3a3f3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-04-26drivers/crb: Disable device if CRB TPM not presentMichał Żygowski
If CRB TPM is not detected in the system it may mean it is inactive due to disabled or neutered ME. In such case, the chipset will route the TPM traffic to LPC/SPI on Intel systems. If CRB TPM is not probed, disable the CRB TPM device driver, so that coreboot will not generate improper SMBIOS/SSDT ACPI tables. Change-Id: Ie0928536d9042b1f680d585e1ca9ad2cadf0c8ef Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-04-25drivers/crb: Check for PTT before attempting to initialize CRB TPMMichał Żygowski
We can assume that platforms, which select HAVE_INTEL_PTT, will not have any other CRB TPM than PTT. Check whether PTT is available before forcefully initializing the TPM and selecting the CRB interface in the TPM configuration registers. Change-Id: If0ec6217b0e321b7d7a9410b70defde3c3195fc3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80453 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-04-25drivers/mipi: Add support for STA_ER88576 panelYang Wu
Add STA panel STA_ER88577 serializable data to CBFS. Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf About the init code, we communicated with the vendor through the datasheet to confirm the writing method of each register value. BUG=b:331870701 TEST=build and check the CBFS includes the panel BRANCH=None Change-Id: I210b23b67fbc102c9926171f1c78f6824820e4b7 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82054 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-24drivers/i2c/rt5645: Add RT5645 amp driverJianeng Ceng
RT5663 is very old and it was used the hard code like RT53 or 10EC5663, which is the different series from RT5645/5650, it may caused some ambiguity. Because I2C generic driver dose not support dsd gpio setting, we declared the new rt5645 series driver for expansion. Add RT5645 AMP support. The kernel driver of 5650 is written in rt5645.c. Add acpi name cbj-sleeve-gpios for power gate GPIO. ALC5650 DataSheet Rev 0.93 Realtek upstream link: https://lore.kernel.org/all/20240404035747.118064-1-derek.fang@realtek.com/ Hide the device because of Microsoft Windows. BUG=None TEST=verified in anraggar and probe device rt5650 succeed ``` \_SB.PCI0.I2C3.RT58: Realtek RT5650 ``` Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81773 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-23drivers/intel/fsp2_0: Support FSP 2.4 64-bitsJeremy Compostella
FSP 2.4 brings FSP 64-bits support which requires some adjustments in coreboot: FSP/UEFI uses the Microsoft x64 calling convention. Appropriate attribute has to be set to all functions calling or called by the FSP. BUG=b:329034258 TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-04-22drivers/intel/fsp2_0: Introduce fsp print helper macrosAppukuttan V K
This patch introduces fsp print helper macros to print `efi_return_status_t' with the appropriate format. These macros are now used for fsp debug prints with return status efi_return_status_t is defined as UINT64 or UNIT32 based on the selected architecture BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: If6342c4d40c76b702351070e424797c21138a4a9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-19acpi: Make acpi_device_write_dsd_gpio() publicJianeng Ceng
Make sure it can be used for other driver. At present, i2c_generic_write_gpio() is not suitable for being called by other drivers, so delete it, add acpi_device_write_dsd_gpio() to replace it, and make it public. BUG=None TEST= Build BIOS FW pass and it can be use for other driver. Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-16security/tpm: support compiling in multiple TPM driversSergii Dmytruk
Starting from here CONFIG_TPM1 and CONFIG_TPM2 are no longer mutually exclusive. Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69162 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15drivers/crb: use crb_tpm_ prefix instead of tpm2_Sergii Dmytruk
This prevents name clashes with drivers/spi/tpm and allows both to be potentially compiled in at the same time. Change-Id: I0aa2686103546e0696ab8dcf77e2b99bf9734915 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-14drivers/uart/pl011: Enhance struct documentationMaximilian Brune
Source: PrimeCell UART (PL011) Technical Reference Manual Revision: r1p5 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I58409b23e3790a052d3bc0ecf6a6bede15b4d76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80180 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <stdarg.h> and <stdio.h>Elyes Haouas
<string.h> is supposed to provide <stdarg.h> and <stdio.h> Change-Id: I021ba535ba5ec683021c4dfc41ac18d9cebbcfd2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81853 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-11tree: Drop unused <edid.h>Elyes Haouas
Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81821 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Drop unused <stdlib.h>Elyes Haouas
Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81819 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11tree: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-11drivers/acpi/thermal_zone: Correct Kelvin constant used for conversionNicholas Sudsgaard
As 0C is 273.15K you could argue that 2731 and 2732 are both correct. However, 2732 is deemed as correct both throughout the codebase and in the ACPI specification[1]. [1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/11_Thermal_Management/thermal-control.html#temperature-change-notifications Change-Id: I845bc750681c7ae6f2d1342b32983b990ce6d296 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81197 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2024-04-11tree: Drop unused <string.h>Elyes Haouas
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09tree: Drop unused <delay.h>Elyes Haouas
Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81812 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-09tree: Drop unused <console/console.h>Elyes Haouas
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09drivers/gfx: Remove unnecessary line continuationsElyes Haouas
Change-Id: Ic71516ae73d61c9f13876a5acc071645bbe8e866 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81594 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-09drivers/mipi: Fine tune clock for BOE_NV110WUM_L60Ruihai Zhou
Fine tune the panel clock to prevent mipi noise from affecting wifi band. After tuning, the panel refresh rate keeps at 60Hz and wifi test passed. Just keep consistent with the Linux kernel panel driver panel-boe-tv101wum-nl6 [1] configuration. [1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/5029075/59 BUG=b:330807136 TEST=fw screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Ic44c86f062d4e836f403ee97f2fc6370fff02797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-06drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_tSubrata Banik
Replace fixed-width integers for pointers and sizes with uintptr_t and size_t, promoting portability across 32-bit and 64-bit architectures. For FSP-API specific UPD assignments, rely on `efi_uintn_t` rather fixed size datatype uint32_t/uint64_t. BUG=b:242829490 TEST=Firmware splash screen visible on google/rex0 w/ both 32-bit and 64-bit compilation. Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81615 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-06lib: Refactor bmp_load_logo() implementationSubrata Banik
This refactoring ensures bmp_load_logo() takes logo_size as an argument, returning a valid logo_ptr only if logo_size is non-zero. This prevents potential errors from mismatched size assumption. BUG=b:242829490 TEST=google/rex0 builds successfully. Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81618 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-05smmstorev2: Load the communication buffer at SMM setupArthur Heymans
This removes the runtime SMI call to set up the communication buffer for SMMSTORE in favor of setting this buffer up during the installation of the smihandler. The reason is that it's less code in the handler and a time costly SMI is also avoided in ramstage. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-04drivers/intel/fsp2_0: Support FSP-T in long modeArthur Heymans
Call into FSP-T using the protected mode wrapper and enter long mode in FSP-T support assembly code. TEST: Booted on ibm/sbp1 in long mode. Change-Id: Id6b9780b06b4bfbb952e32091ffbf3d0014f2090 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-04-04drivers/intel: Align FSP debug handler with EFI calling conventionSubrata Banik
Ensures the FSP debug handler adheres to the EFI calling convention, enabling seamless integration with coreboot infrastructure. This is critical for 64-bit coreboot and FSP communications. BUG=b:242829490 TEST=FSP debug logs successfully captured via coreboot event handler. Change-Id: I9085a6c7d50e58fb56cbbc61da3a0af094d0dc05 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-04-03drivers/mipi: Fine tune clock for IVO_T109NW41Ruihai Zhou
Fine tune the panel clock to prevent mipi noise from affecting wifi band. After tuning, the panel refresh rate keeps at 60Hz and wifi test passed. Just keep consistent with the Linux kernel panel driver panel-boe-tv101wum-nl6 configuration. BUG=b:330807136 TEST=fw screen display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I128b33fbcda9759330a363ebb6cf66415405c488 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81625 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-04-03drivers/intel/fsp2_0: Use coreboot uint8_t type for consistencySubrata Banik
This patch replaces UINT8 with uint8_t to align with coreboot's standard data type conventions. This promotes consistency within the codebase. BUG=b:242829490 TEST=Verified firmware splash screen functionality on google/rex0. Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81571 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-04-02drivers/mipi: Add support for KD_KD101NE3_40TI panelYang Wu
Add K&D panel KD_KD101NE3_40TI serializable data to CBFS. Datasheet: KD101NE3-40TI-A003 _Pre SPEC_20231218.pdf BUG=b:331870701 TEST=build and check the CBFS include the panel BRANCH=None Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81583 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-30drivers/tpm: Make it compile againPatrick Rudolph
Fix regression introduced in 47e9e8cde1810ee9f249027b14ee9f82a7a52d84 "security/tpm: replace CONFIG(TPMx) checks with runtime check": Replace BIOS_WARN with BIOS_WARNING. Change-Id: Id23cda2f5403effd2a4bda3852f0f300d0e62cdf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81590 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28security/tpm: replace CONFIG(TPMx) checks with runtime checkSergii Dmytruk
This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2 during compilation, in which case actual TPM family in use can be determined at runtime. In some places both compile-time and runtime checks are necessary. Yet in places like probe functions runtime state checks don't make sense as runtime state is defined by results of probing. Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69161 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-28security/tpm: resolve conflicts in TSS implementationsSergii Dmytruk
No functional changes. Refactor code such that there won't be any compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled in. One might want to support both TPM families for example if TPM is pluggable, while currently one has to reflash firmware along with switching TPM device. Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-28security/tpm: make tis_probe() return tpm_familySergii Dmytruk
Via an out parameter. This is needed to be able to dynamically pick TSS implementation based on the information discovered on probing. Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69159 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-26drivers/intel/fsp2_0: Avoid unnecessary extra CBFS accessJeremy Compostella
fsp_mrc_version() function does not need to perform a CBFS access to to get an address to the FSP-M blob as the caller, do_fsp_memory_init(), already has it loaded. In addition to make the code simpler, it avoids an unnecessary decompression of the FSP blob if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set. TEST=Verified on Meteor Lake rex Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81256 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2024-03-23drivers/i2c/tas5825m: Allow using I2C busTim Crawford
The latest Clevo boards connect the TAS5825M to one of the I2C connections instead of the SMBus connection. The I2C ops are compatible with SMBus, so always use them. Tested on system76/oryp6 (uses SMBus) and in-development system76/oryp12 (uses I2C3). TAS5825M init is successful and speaker output works. Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-23drivers/intel/ish: Include stdbool.h to identify bool typeKarthikeyan Ramasubramanian
When the concerned chip.h file is included in a source file, it causes compilation error saying unknown type name bool. Fix it by including the stdbool.h file in the chip.h file. BUG=None TEST=Build Brox by including the chip.h file in one of the source files. Change-Id: I4159e2c281c3e89dc45555ce38ad8637a3bf8587 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 12:55:34 +0000