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2019-07-02drivers/pc80/rtc/mc146818rtc_boot: Use size_t for lengthElyes HAOUAS
Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-27drivers/pc80/tpm: add support for TPM emulator SwTPM 2.0 moduleTsung Ho Wu
Add software TPM 2.0 emulator to tpm device probe list. SwTPM: https://github.com/stefanberger/swtpm Tested on qemu q35 with MAINBOARD_HAS_LPC_TPM and MAINBOARD_HAS_TPM2 set in qemu-q35 Kconfig. Qemu: see qemu flags at https://s3hh.wordpress.com/2018/06/03/tpm-2-0-in-qemu/ How to see it work. Ubuntu 18.04: 1. Install SwTPM from https://github.com/stefanberger/swtpm 2. Add MAINBOARD_HAS_LPC_TPM and MAINBOARD_HAS_TPM2 to src/mainboard/emulation/qemu-q35/Kconfig and rebuild coreboot.rom 3. mkdir -p swtpm0 4. swtpm socket --tpmstate dir=swtpm0 --tpm2 --ctrl \ type=unixio,path=swtpm0/swtpm-sock --log level=20 & 5. qemu-system-x86_64 -machine q35 -m 2G \ -chardev socket,id=chrtpm,path=swtpm0/swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm -device \ tpm-tis,tpmdev=tpm0 -pflash build/coreboot.rom \ -serial $(tty) -display none 6. Check boot log and search 'Found TPM'. Change-Id: I5f58d2c117afbd057bb91697912db826db1d67a1 Signed-off-by: Tsung Ho Wu <tsungho.wu@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33302 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-24Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADERSubrata Banik
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set to ENV_RAMSTAGE. This approach will help to add future optimization (rampayload) in coreboot flow if required. Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-22drivers: Add missing #include <commonlib/helpers.h>Elyes HAOUAS
ALIGN and ALIGN_UP needs 'helpers.h Change-Id: Ia18f69b58bae6d841d800dc38745ff27f51cec46 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21drivers/ipmi: Add chip opsPatrick Rudolph
* Add chips ops for IPMI KCS. * Get IPMI version over KCS. * Generates ACPI SPMI table for IPMI KCS. * Generates SMBIOS type 38 for IPMI KCS. * Generates ACPI SPMI device for IPMI KCS on LPC device. * Add documentation To use this driver on BMC that support KCS on I/O: 1. Add an entry to the devicetree.cb: chip drivers/ipmi device pnp ca2.0 on end # IPMI KCS end 2. Select IPMI_KCS in Kconfig. 3. (Optional) enable LPC I/O decode for the given address. Tested on Wedge100s. Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21drivers/intel/fsp: use ALIGN_UP instead of ALIGN for better readabilityFelix Held
Change-Id: I41fd50dc1e30332261f80e99419dad2635b5a54a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-06-21src/driver/vpd: Update vpd_decode from upstreamHung-Te Lin
The upstream vpd_decode.c has been revised to prevent overrun of decoded contents. BUG=chromium:967209 TEST=select VPD config on kukui; make; boots on at least kukui boards. Change-Id: I1a50670a66b7b174d2a432c29d90152b86c32982 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21drivers/intel/fsp1_0/fastboot_cache: Remove unneeded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: I109f5aaa87afde61a36fff884305b43c1de2c680 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vlado Cibic Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21drivers/amd/agesa: Assert that StdHeader is non-nullJacob Garber
Coverity believes there is a path where StdHeader is possibly null. This *should* be incorrect, since the header is actually initialized through the module dispatch framework, though Coverity can't see it due to the extensive type-punning. However, the control flow is so dizzingly complicated that I'm not even completely sure, so adding an extra assert to be careful won't hurt anyway. Change-Id: If3d7c5d5c5bba846e7453b3dbc824e2208d749fb Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1379932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-18drivers/i2c/sx9310: Print I2C SAR device infoEric Lai
Print I2C SAR device info so that it is available in cbmem logs. BUG=none BRANCH=none TEST=Boot up and check cbmem -c can find the SAR I2C info Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia143932bb660ed2c2cea76310f11ede2b727adf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33432 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-18drivers/ipmi: Fix multiple issuesPatrick Rudolph
* Set abort command define * Set debug level to SPEW * Support zero length data packet in ipmi_kcs_send_message That's required for commands like GET_DEVICE_ID, which have no additional data to send. * Read reply even if given no receive buffer * Prevent buffer overflow in read reply processing Tested on Wedge100s. Change-Id: Iefddd88a744c3b96751d3fe8c2951ca2115548ce Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33488 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-16drivers/ipmi: Fix coding stylePatrick Rudolph
Fix 'do not use assignment in if condition'. Change-Id: I6e1b81a1b87de4315391618968c59cc3d3a66a77 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-14drivers/fsp1_0: select CACHE_MRC_SETTINGS if MRC_CACHE_FMAPMatt DeVillier
Rather than force the user to create the RW_MRC_CACHE FMAP region, simply select CACHE_MRC_SETTINGS so it's done automatically for them. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Iaa1da6015c1bfafe8ea81ca34ef8851f0c689487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-12{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK supportFrans Hendriks
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-10spi_flash: Add Dual SPI supportJulius Werner
This patch adds support to read SPI flash in Dual SPI mode, where both MISO and MOSI lines are used for output mode (specifically Fast Read Dual Output (0x3b) where the command is still sent normally, not Fast Read Dual I/O (0xbb) whose additional benefit should be extremely marginal for our use cases but which would be more complicated to implement). This feature needs to be supported by both the flash chip and the controller, so we add a new dual_spi flag (and a new flags field to hold it) to the spi_flash structure and a new optional xfer_dual() function pointer to the spi_ctrlr structure. When both are provided, Dual SPI mode is used automatically, otherwise things work as before. This patch only adds the dual_spi flag exemplary to all Winbond and Gigadevice chips, other vendors need to be added as needed. Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10spi_flash: Make .read() callback optionalJulius Werner
All SPI flash chip drivers currently in coreboot use the generic read functions (spi_flash_cmd_read_fast()/_slow()) as their read callback. The only use case for specialized read callbacks we have left is with specialized flash controllers like Intel fast_spi (which sort of impersonate the flash chip driver by implementing their own probe function). This patch unifies the behavior for all normal flash drivers by making the read callback optional and letting them all fall back to a default read implementation that handles normal fast/slow reading. Most of the drivers used to install the respective callback after checking CONFIG_SPI_FLASH_NO_FAST_READ, but some hardcoded either slow or fast writes. I have found no indications for why this is and spot-checked datasheets for affected vendors to make sure they all support both commands, so I assume this is just some old inaccuracy rather than important differences that need preserving. (Please yell if you disagree.) Also take the opportunity to refactor some of the common spi_flash.c code a bit because I felt there are too many nested functions that don't really do enough on their own, and centralizing stuff a bit should make it easier to follow the code flow. (Some of this is in preparation for the next patch.) Change-Id: I2096a3ce619767b41b1b0c0c2b8e95b2bd90a419 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-06-10spi_flash: gigadevice: Adopt Winbond chip info structureJulius Werner
This patch changes the Gigadevice SPI flash driver to adopt the same structure packing improvements for the hardcoded parameters of individual chips that was implemented for Winbond last year. This cuts the size of the hardcoded info nearly in half and should save us a few hundred bytes in every stage. Change-Id: I9910dcb9b649f51b317f3f8fcba49e5e893f67d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-10cbfs_spi: Enable speed logging by default for BIOS_DEBUGJulius Werner
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get in the way (just adding one line per stage, essentially) and should have no notable overhead. Let's enable it by default for the BIOS_DEBUG log level rather than having to recompile to get it. Also fix an issue with building this code on MIPS due to lack of 64-bit division primitives. (This means MIPS and arm32 board may display incorrect results when reading more than 4MB in a single transfer, which sounds very unlikely.) Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-08mb/lenovo/t430: Fix Dual GraphicsPatrick Rudolph
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix disabling iGPU in 'Dual Graphics' on Lenovo T430. * Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select DRIVERS_LENOVO_HYBRID_GRAPHICS. Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-05src/drivers/intel: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects pointer fih as FORWARD_NULL. Add sanity check for fih to prevent NULL pointer dereference. BUG=CID 1401717 TEST=Built and boot up to kernel. Change-Id: Ia6853e5302c87d9ffe52b942f067be56f6e77406 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-06-04drivers/fsp20: Fix spelling in help textFelix Singer
Change-Id: Iab8d20a385bde31b29fa7766a87753fcc2d759b8 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-04soc/intel/braswell: Use common cpu/intel/car codeArthur Heymans
The code in cpu/intel/car/romstage.c Does most of the things like setting up timestamps, stack guards, entering postcar. A functional difference is that the FSP header is searched for twice instead of passed from the CAR entry to the C code. When using C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special linker symbol kept across multiple stages is needed, which is likely not worth the speedup). Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-03drivers/aspeed/ast2050: Remove variable set but not usedElyes HAOUAS
Change-Id: Iedda92edf8c4eb7be037dcc0faa6fe8aa0c0754c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-03src/driver/vpd: Update lib_vpd from upstreamHung-Te Lin
Update lib_vpd.c (only containing vpd_decode.c) to latest version from https://chromium.googlesource.com/chromiumos/platform/vpd The called module (vpd.c) has been also corrected for new lib_vpd types and constants. BUG=chromium:967209 TEST=select VPD config on kukui; make; boots on at least kukui boards. Change-Id: I3928e9c43cb87caf93fb44ee10434ce80f0a188a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-06-03drivers/intel/fsp1_1: Exit cleanly if FSP not foundJacob Garber
Instead of dereferencing a null pointer, print a nice message and exit cleanly if the FSP isn't found in the CBFS. Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1401467, 1401717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33049 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/{device,drivers}: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I3395715f9e2b03175089186ab2e57d9e508fc87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-29soc/intel/skylake: Use common cpu/intel/car romstage codeArthur Heymans
Setting up the console and entering postcar can be done in a common place. Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29drivers/intel/fsp1.1: Simplify bootflow and clean upArthur Heymans
This gets rid of the boilerplate back and forward calls between the SOC/FSP-driver code and mainboard code. Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/drivers/xgi: Move coreboot related includes to xgi_coreboot.hElyes HAOUAS
Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29drivers/generic/max98357a: Add extra error handlingJacob Garber
It is possible that acpi_device_scope() and acpi_device_name() can return NULL to indicate an error, so add error handling to check their return values. Change-Id: I4c7ab0c592845d9d5f142e078fc2b505a99ecd12 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1362592 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29drivers/intel/fsp2_0: Dont' use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Ic50b16916261abb8c63b8fe571819af5c830ff8d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29drivers/emulation/qemu_debugcon: Don't use CAR_GLOBALArthur Heymans
This platform uses NO_CAR_GLOBAL_MIGRATION. Change-Id: Idc9434e5a1a8bc5ed76a9f80c9a7cfba2fd474c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29Clean up unused arch/early_variables.h headerArthur Heymans
Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29drivers/intel/fsp2_0: Fix typo mistakeSubrata Banik
Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-05-27src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0Arthur Heymans
drivers/intel/fsp1_0/Kconfig is a better location than cpu/x86/Kconfig. Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-27drivers/intel/fsp1.1: Remove unused functionArthur Heymans
This function is unused since POSTCAR_STAGE is used. (be291e8 soc/intel/fsp1.1: Implement postcar stage) Change-Id: Ia9ff5236295a0e1c4f7634d27cf0ae1d87029678 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-27drivers/intel/fsp1.1: Remove stale comment on bootflowArthur Heymans
This list is incorrect and not up to date. The FSP1.1 romstage bootflow is unnecessarily clumsy and instead of trying to update this comment effort is better spend making the bootflow more streamlined. Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-25AGESA binaryPI: Add AGESA entry timestampsKyösti Mälkki
The call to timestamp_rescale_table() had to be moved before TS_AGESA_INIT_{POST/RESUME}_DONE to have that timestamp appear without rescaling. Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-25AGESA binaryPI: Redo entrypoints namelistKyösti Mälkki
Stop assuming the list is complete with no gaps, and use a lookup-table to match AGESA_STRUCT_NAME types of the entrypoints we use with names. Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-25AGESA: Move debug helper to eventlog fileKyösti Mälkki
Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31513 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25AGESA: Move heap_status_name() implementationKyösti Mälkki
Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23AGESA binaryPI: Sync STRUCT_NAME definitionsKyösti Mälkki
While not implemented, copying the definitions from later AGESA/AMD.h to older helps us avoid lots of preprocessor directives. Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31510 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-22post_code: add post code for video initialization failureKeith Short
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon initialization returns an error when graphics was also initialized. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22post_code: add post code for memory errorKeith Short
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails to initialize RAM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22post_code: add post code for invalid vendor binaryKeith Short
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails to locate or validate a vendor supplied binary. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-21soc/intel/fsp1.1: Implement postcar stageArthur Heymans
This moves FSP1.1 to use postcar stage to tear down CAR. On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found during the postcar stage so there is no need to push to save it in CAR global variables. On FSP1.1 platforms with an open source CAR implementation (Skylake, even though it still runs the FSP-T), the soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR. This also uses common functions to set up the MTRR to use after CAR is torn down. Test: build/boot on google/celes (BSW) and google/chell (SKL) Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-21src/drivers/intel/fsp2_0: Fix logical 'and' of equal expressionsElyes HAOUAS
Probably a copy/paste issue. Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-16{arch,cpu}/x86, drivers/intel: Restore cpu_index error handlingJacob Garber
Previously cpu_index() always succeeded, but since commit 095c931 (src/arch/x86: Use core apic id to get cpu_index()) it is now possible for it to indicate an error by returning -1. This commit adds error handling for all calls to cpu_index(), and restores several checks that were removed in commit 7c712bb (Fix code that would trip -Wtype-limits) but are now needed. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I5436eed4cb5675f916924eb9670db04592a8b927 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-05-16drivers/elog: Rename ramstage_elog_add_boot_count() to elog_add_boot_count()Subrata Banik
This patch removes ramstage_ prefix from ramstage_elog_add_boot_count() function. Change-Id: Ia75b2dc959ace7dc26dc974c5f4b5cb6c5a25617 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-05-16Remove remaining unnecessary ENV_RAMSTAGE guardSubrata Banik
TEST=Able to build coreboot for CML. Change-Id: I8a6a97d59277ebfc498c83bb039436ed7c89d2cd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-05-14Remove unnecessary ENV_RAMSTAGE guardSubrata Banik
TEST=Able to build coreboot for CML. Change-Id: Ic0f473e04ffc1de50dee871af52eacf0b328b376 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32764 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-123rdparty/libgfxinit: Update for runtime CPU detectionNico Huber
Beside one tiny fix for framebuffer scaling, this contains a major refactoring of libgfxinit's configuration infrastructure. With this, we are finally able to detect CPUs at runtime and only have to confi- gure a CPU/GPU generation. Change-Id: Iccf4557453878536f527e4a1902439a1961ab701 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-12boot_device: Constify argumentPatrick Rudolph
Add const qualifier to first argument. Change-Id: I6655e04401b6a7aa5cafb717ff6f46b80b96646e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07intel/fsp1_1: Drop remnants of `pei_data`Nico Huber
`pei_data` was a struct with blob parameters from pre-FSP times. Somehow, it sneaked into upstream FSP1.1 support (probably because early board ports were written for a different blob). When added upstream, its usage was already perverted. It was declared at SoC level but mostly used to pass mainboard data from mainboard code to itself and FSP data from FSP code to itself. Now that no board/ SoC code uses it anymore, we can finally drop it. Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-07intel/fsp1_1: Move MRC cache pointers into `romstage_params`Nico Huber
These are part of a common concept and not SoC specific. Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-07intel/fsp1_1: Drop `boot_mode` from `pei_data`Nico Huber
It was only used locally. Change-Id: Iaaad760e8ceca62655f5448c30846cf11959e8e1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-05-07intel/fsp1_1: Drop unused, weak raminit()Nico Huber
Change-Id: I5d155df1d589fc8d7462f46e87275bd6efae0a7f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-05-06drivers/intel/fsp2_0: Fix fsp post-init validationMatthew Garrett
Part of this checks whether tolum_base and cbmem_top are the same - however, cbmem_top hasn't been initialised at the point where this call occurs. Change the ordering to fix that. Signed-off-by: Matthew Garrett <mjg59@google.com> Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-05-06Fix code that would trip -Wtype-limitsJulius Werner
This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06drivers/intel/fsp1_1/cache_as_ram.inc: Reduce max line length to 80Frans Hendriks
Cosmetic change to reduce line length to 80 max. BUG=NA TEST=Build Portwell PQ7-M107 Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-03drivers/fsp 1.1: clean up Kconfig optionsMatt DeVillier
Now that support has been added for using the public FSP repo for Braswell platform, clean up Kconfig options and set sane defaults when using it. The following changes have been made: - add option to use the 3rdparty/fsp repo for Braswell platform - reorder FSP 1.1 Kconfig entries for improved flow/readability - set the default path for the FSP binary based on use of FSP repo and platform - set the CBFS location for the FSP binary based on platform Change-Id: Ie2f732bf0ac4d4551908caa56360b8bb2869b4c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-25drivers/spi/sst: Remove unused variablesElyes HAOUAS
Change-Id: Ic6eb9c7dbfc5fde97f0f45f09431c617cb850c38 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-24mb/google/sarien: Disable touch by strap pin GPP_B4Eric Lai
We want to disable touch for non-touch sku. We can use strap pin GPP_B4 to identify it is connected with touch or not. touch sku: GPP_B4 is low non-touch sku: GPP_B4 is high BUG=b:131132419 TEST=boot up and check no touch device exist Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If6681262c25e4b01e061a8520e38905d40345509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32438 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23src: include <assert.h> when appropriateElyes HAOUAS
Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-21drivers/intel/fsp2_0: Set basename for FSP binariesFelix Singer
Since there is no standardized naming scheme for the FSP binaries, the option USE_FSP_REPO can't be used on some platforms, because some of the filenames differ and the build process awaits "Fsp_*.fd" as filename. As a workaround, add the option -n to SplitFspBin.py, which defines the basename. Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30930 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-12drivers/i2c/sx9310: Add support for GPIO IRQFurquan Shaikh
This change adds support for mainboards to use GPIO IRQ instead of IOAPIC to accomodate for cases where IOAPIC routing might not be available for certain pads. BUG=b:129794308 Change-Id: I3e2bb4280303cea177cc0c803d29140731e2b44a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11drivers/spi: Move M25Pxx commands to spi_winbond.hFrans Hendriks
Move Winbond M25PXX command values to spi_winbond.h file. The command values will be used for programming SPI contoller of Intel Braswell, using this include file. Update winbond.c file with coreboot header. BUG=N/A TEST=Facebook FBG-1701 with flashrom Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11drivers/intel/fsp1_1: Configure UART after memory initFrans Hendriks
FSP code will default enable the onboard serial port. When external serial port is used, this onboard port needs to be disabled. Add function mainboard_after_memory_init() function to perform required actions to re-enabled output to external serial port. BUG=N/A TEST=LPC Post card on Intel Cherry Hill Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-06src: Use #include <timer.h> when appropriateElyes HAOUAS
Also, extra-lines added or removed and local includes moved down. Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-05drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failureFrans Hendriks
RTC time contains invalid values on system without RTC battery. Handle 'invalid' the same way as 'cmos_invalid'. This will reset CMOS date when calling function enables 'invalid'. BUG=N/A TEST=Portwell PQ-M107 booting Linux Embedded Change-Id: I5eae57d00f328400a8b03c28b7ecdbbc71522206 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29329 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-02drivers/intel/fsp2_0: Use same stack with corebootSubrata Banik
This patch ensures to have same stack base for FSP and coreboot. Feature added in FSP2.1 - Remove stack swapping from FSP. - Stack will be shared between coreboot and FSP. TEST=Build and boot FSP2.1 enable platform like dragonegg, iclrvp. No car global variable corruption seen after enabling this feature. Change-Id: I673b4216d991d8ccad725c3931006a694184106c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32079 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-28drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 moduleSubrata Banik
Add HrP 9560 module device ID (0x06F0) into device/pci_ids.h file. TEST=HrP module is getting detected during PCI enumeration on CMLRVP Change-Id: I8f6d89b1c6d03e2497f6b345a520323f45247d7e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32096 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27drivers/intel/gma: Move gfxinit into sub packageNico Huber
Move the actual graphics init provided by libgfxinit into a sub package `GMA.GFX_Init`. This way it can be compiled in individually. Change-Id: Ib413a0d70c8dc305f4476c1d5aee6b81ff880bec Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31456 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-27drivers/intel/gma: Make libgfxinit available w/o gfxinitNico Huber
We might want to make use of libgfxinit functions without using it for actual graphics init. Change-Id: I29c3b19989acb678d0d447e83d38bad9d584caa9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31455 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-25Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)Julius Werner
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-23console/qemu_debugcon: Support additional stagesPatrick Rudolph
Add support for bootblock and postcar, which were introduced on qemu in the last few month. Fixes non-working debugcon in those stages. Change-Id: I553f12c2105237d81ae3f492ec85b17434d8334c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31833 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19drivers/intel/fsp2_0: Add support for FSP minor version updateSubrata Banik
This patch adds support for FSP2.1 Kconfig which is backward compatible with FSP2.0 specification and added below coreboot impacted features as below: 1. Remove FSP stack switch and use the same stack with boot firmware 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30310 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19drivers/intel/fsp2_0: Implement EFI_MP_SERVICES_PPI structure APIsSubrata Banik
This patch ensures to have below listed features: 1. All required APIs to create MP service structure. 2. Function to get MP service PPI status MP specification here: http://github.com/tianocore/edk2/blob/master/MdePkg/Include/Ppi/MpServices.h coreboot design document here: ../Documentation/soc/intel/icelake/MultiProcessorInit.md Supported platform will call fill mp_services structure so that FSP can install the required PPI based on coreboot published structure. BRANCH=none BUG=b:74436746 TEST=Able to publish MP service PPI in coreboot. Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25634 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-16drivers/intel/fsp1_0: Deduplicate codePatrick Rudolph
Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0. Allows to have a common entry after FSP-M. Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-03-15drivers/intel/fsp2_0: fix TPM setup and MRC cache hash logicJoel Kitching
When VBOOT_STARTS_IN_BOOTBLOCK is selected, the tpm_setup call in memory_init.c is not used. When VBOOT_STARTS_IN_ROMSTAGE is selected, the tpm_setup call in memory_init.c is triggered. However, when verstage runs, tpm_setup is called yet again, and an error is triggered from the multiple initialization calls. Since there are currently no boards using VBOOT_STARTS_IN_ROMSTAGE + FSP2_0_USES_TPM_MRC_HASH, disable this combination via Kconfig, and remove the tpm_setup call from Intel FSP memory initializion code. * VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=y vboot is enabled, and TPM is setup prior to Intel FSP memory initialization. Allow FSP2_0_USES_TPM_MRC_HASH option. * VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=n vboot is enabled, but TPM is setup in romstage, after Intel FSP memory initialization. Disallow FSP2_0_USES_TPM_MRC_HASH option. * VBOOT=n vboot is disabled. Disallow FSP2_0_USES_TPM_MRC_HASH option. See bug for more information: https://bugs.chromium.org/p/chromium/issues/detail?id=940377 BUG=chromium:940377 TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: I4ba91c275c33245be61041cb592e52f861dbafe6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31837 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14drivers/i2c/lm96000: Add new hardware-monitoring ICNico Huber
LM96000 is the successor of the famous LM85. Change-Id: Ie7df3107bffb7f8e45e71c4c1fbe4eb0a9e3cd03 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/21194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-14drivers/i2c/nct7802y: Add new hardware-monitoring ICNico Huber
Just another hardware-monitoring chip. Only limited fan control and PECI configuration is implemented. Change-Id: I35ea79e12941804e398c6304a08170a776f4ca76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-12drivers/intel/fsp2_0: Add provision to include PPI directorySubrata Banik
This patch adds a generic provision into FSP2.0 driver to implement dedicated PEIM to PEIM interface as per Intel FSP requirement. Change-Id: I988d55890f8dd95ccf80c1f1ec2eba8196ddf9a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07src: Drop unused include <timestamp.h>Elyes HAOUAS
Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-03-06driver/intel/ish: add ish chip driver supportJett Rink
We want to be able to specify the firmware variant suffix in the devicetree.cb configuration for particular firmware builds. This driver allows us to specify the firmware_variant property in the device tree and have it populate a _DST table in the SSDT ACPI table for the ISH device, thus making the suffix available to the kernel (See crrev.com/c/1433482 for kernel change that uses the value) BUG=b:122722008 TEST=decompile DDST table and verify that new firmware-variant value is present. Also verfied that kernel can access this new field using the shim loader kernel CLs Change-Id: Id8be986185282521aee574027503eaf8968e1508 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01drivers/intel/fsp2_0: Add more EFI return status into FSP2.0 driverSubrata Banik
This patch adds few more required EFI return status into FSP2.0 drivers so that coreboot code can make use of those. Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-23drivers/intel/fsp2_0: Update dependency of USE_FSP_REPOMaulik V Vaghela
USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was getting selected for cometlake soc also. Since FSP is not yet upstreamed for cometlake, compilation was failing due to FSP was not found. So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only and excluding for cometlake. Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-22Revert "src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260"Duncan Laurie
This reverts commit 3afb84a24583f5dee9fb407f11b32253d59392bf. Reason for revert: This is causing issues with the PCIe link and the system is unable to enter S0ix. Until it can be fixed in coreboot revert the change here that is not working properly. BUG=b:124264120 Change-Id: Ia20da9ab560ca35950b4a916667f51e0f541b382 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31559 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 02:01:22 +0000