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2017-07-26drivers/pc80/rtc: Build for bootblock and postcar stages tooNico Huber
Fixes builds with BOOTBLOCK_CONSOLE && USE_OPTION_TABLE. Change-Id: I1c7e9baa60f33c2c3651e2def0335454f7e20451 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25drivers/intel/fsp2_0: Add NULL check while locating hob list ptrSubrata Banik
Assert incase unable to locate hob list pointer due to cbmem is not available. Change-Id: I17f54b07ab149ae06d09226ed9063189d829efe2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth
This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611. This was merged too early. I'll repost it. Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17intel/fsp: Add and use new post codes for FSP phase indicationSubrata Banik
New post codes are POST_FSP_MEMORY_EXIT POST_FSP_SILICON_EXIT This patch will make it more consistent to debug FSP hang and reset issues. Bug=none Branch=none TEST=Build and Boot on eve Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-17intel/fsp1_1: Don't consume FSP_SMBIOS_MEMORY_INFO_HOB in S3 resume pathSubrata Banik
FSP doesn't publish smbios_memory_info_guid during S3 resume path. Hence it's recommended to skip consuming this HOB in S3 resume. Bug=none Branch=none TEST=Build and boot Lars system with this patch. Change-Id: I321751523b1ea3326ffc23f4d4c53d5362482674 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17drivers/intel/fsp1_1: Handle errors in find_fsp()Werner Zeh
The function find_fsp() parses the FSP header and returns either a valid pointer to the FSP_INFO_HEADER or an error code. The caller of find_fsp() only takes care about a NULL-pointer but not about a possible error code. This leads to memory access violations in case of error when FspTempRamInit is called. To avoid this and to let the user know that there was an error while parsing the FSP header show an error message and the error code. Change-Id: I67fef0a53fb04c8ba5d18b5d4ef2fdc1aeba869e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-16drivers: Drop level of indirection for MMIO HW accessStefan Reinauer
We don't need another level of indirection for these hardware accesses. Change-Id: Ic567d8272e5dd943ce19babbd7ad57ba5d86c354 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-15siemens/nc_fpga: Fix wrong type castWerner Zeh
As "var" is not a pointer but a variable there is no need to cast it to a pointer before using the value. Change-Id: I7f8e3ceadaa4301c50c5f5480cccab2be904aa9a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-15drv/intel/gma/i915: Get rid of unused function prototypePatrick Rudolph
The function prototype isn't used any more, remove it. Change-Id: Ie5bd4e4ec8f28bc0768d5427cf734ef77855a15e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-14drivers/fsp1_1: remove VBT function defs from util.hMatt DeVillier
Including <fsp/gop.h> in util.h causes issues with redeclarations when using SOC_INTEL_COMMON_GFX_OPREGION along with FSP 1.1. Separating it out and including directly in vbt.c has no negative side effects. Change-Id: I2d82c2da40b067272d876929fc73b97f490146a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13src/drivers: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: Ib3a1cf04482a8f19b159c31cfb16a7b492748d91 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12drv/intel/gma/opregion: Add method to restore ASLSPatrick Rudolph
Add a new method to restore ASLS on S3 resume. Use new interface introduced in last commit. Change-Id: I254683081cbaf3a5938794dcba140ac9ee07f48a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12drv/intel/gma/opregion: Add interface for GNVS ASLB handlingPatrick Rudolph
Add and use new interface to set and get GNVS' ASLB register. To be used by Intel's gma driver to set ASLB at ACPI table creation and to get ASLB on S3 resume. Change-Id: If30c6b2270069783b0892774802f47406404da5f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12drv/intel/gma/opregion: Add function to set ASLS registerPatrick Rudolph
Add a new method to set ASLS register that holds the ACPI OpRegion base address. Change-Id: I4850500ac6d58f80b0eddc81514053c87774405c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-11siemens/nc_fpga: Modify macro FPGA_SET_PARAM to avoid hwilib errorsWerner Zeh
The macro FPGA_SET_PARAM was introduced to make the setting of different FPGA registers with the appropriate values from hwinfo more transparent. The hwilib takes care about the size of the provided buffer where the requested value should be stored in. The fields in hwinfo have not always the same size as the matching registers in the FPGA. So to avoid errors resulting in a too small buffer when calling hwilib_get_field() the buffer is now fixed to 32 bit and will be casted to the destination type when the value is written into the FPGA register. Changing the field size in hwilib would be the wrong way as the defined lengths are specified this way to be expandable in the future. In addition the number of maximum supported temperature sensors is increased to 8 as the FPGA now supports more. Change-Id: I0c697106783158420708a973c3cff2be90fa4fce Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-10drivers/intel/gma: Fix undefined behaviorRyan Salsamendi
Fix undefined behavior found by clang's -Wshift-sign-overflow, find, and source inspection. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I5240a19647c8ad59f64925f3e1c199446a886d2d Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-07-03northbridge/intel/haswell: Fix undefined behaviorRyan Salsamendi
Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-02drivers/spi: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: If80e0c4e1c9911b44853561b03aef1c741255229 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-02siemens/nc_fpga: Rename freeze_mode to freeze_disableWerner Zeh
The flag FF_FreezeDis marks if this feature is disabled. For a better readability rename freeze_mode to freeze_disable and invert the meaning of this information. Change-Id: I648b2392d2c8046965479511fde485a9cb934378 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-30rx6110sa: Add a software reset sequence in case of power lossWerner Zeh
According to the datasheet the RTC needs a power rising slope of no more than 100µs/V to ensure a correct power-on reset. If the mainboard that hosts the RTC cannot guarantee this, a software reset sequence is needed in the case where the battery was drained completely. As the rising slope of the power supply depends on so many parameters and is highly mainboard specific, refactor the initialization code to perform a software reset every time a power loss event is recognized by the RTC. Change-Id: If64d672e51667523058041bd00e1e50ac047143d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27drivers/spi: Don't disable non-existent warnings on clangStefan Reinauer
The warning -Wstack-usage= doesn't seem to exist on clang, so trying to disable it makes the compiler unhappy about non-existent pragmas. Catching this on gcc is good enough, so let's disable it for the clang case Change-Id: Ia3716a83ba41743ac1dbe73e70abd170de30d7ab Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-22drv/intel/gma/acpi: Fix copyright headerPatrick Rudolph
Use full text GPLv2 header. Change-Id: I937aed725ebf0d2e12c52ac4d94794830fbd764d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-20drivers/net/r8168: Get mac address from VPDShelley Chen
If RT8168_GET_MAC_FROM_VPD selected, use r8168 driver with some slight mods to check the VPD for a mac address. Otherwise, check for mac address in cbfs. Use default mac address if cannot find one. BUG=b:62090148, b:35775024 BRANCH=None TEST=Boot to kernel. Insert mac address into VPD vpd -s ethernet_mac=<address> reboot the system. Ensure we have ip address and corresponding mac address with ifconfig. Ensure ethernet controller shows up with lspci. Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-15drivers/xgi: Fix usage of NGI Kconfig optionsNico Huber
This driver reinvented MAINBOARD_DO_NATIVE_VGA_INIT in a very special way: If it wasn't set, perform native gfx init in textmode, if it was set, perform native gfx init in linear framebuffer mode. Test for LINEAR_FRAMEBUFFER instead and make the native gfx init optional. Also, make Kconfig reflect the actual behaviour. Change-Id: If20fd1f5b0f4127b426e8ff94acc61fcd4eb49af Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/20131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-14drivers/fsp1_1: decouple VBT from execution of GOP driverMatt DeVillier
Commit 2e7f6cc introduced the 'no graphics init' option for FSP 1.1 SoCs using a GOP driver to init the display, but selecting that option while including a VBT breaks compilation for Braswell and Skylake devices because the VBT and GOP driver are intertwined. This patch decouples the VBT from the GOP driver execution, allowing the 'no graphics init' option to compile (and work) properly when CONFIG_ADD_VBT_DATA_FILE=y. Change-Id: Ifbcf32805177c290c4781b32bbcca679bcb0c297 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20210 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-06-13siemens/nc_fpga: Expand FPGA functionalityMario Scheithauer
The siemens/mc_apl1 mainboard needs more functionality provided by Siemens NC FPGA. The additional functionality contains backlight brightness/PWM control and Dsave time for board reset. Change-Id: I6b65b01f0d67afe598b7c005868f71b00dec56fd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-12src/drivers: Add license headersMartin Roth
Change-Id: I1c4b30ab47e12ec35cb681ec5c6635ecd20aa2e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19121 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-09rx6110sa: Add more chip configuration options to chipWerner Zeh
The RTC RX6110SA has several configuration options which might be interesting to set. To make this setup independent of the driver itself but let it still be configurable on mainboard level, add more configuration options to the chip driver. Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08drvs/intel/wifi/wifi: Fix regressionPatrick Rudolph
Fix regression introduced by commit 5c026445 (drivers/intel/wifi: Add support for generating SSDT table) In case the regular PCI path is taken, there're no chip_ops and the code will segfault. The bug was covered by other bugs that caused this code to never execute. Add NULL pointer checks and only fill in device name if one is provided. Tested on Lenovo T430 and wifi card 8086:0085. Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-06-07Kconfig: Indent help textMartin Roth
These Kconfig files had help text that was not indented further than the 'help' keyword. Change-Id: Ia9fdb22c0f5f0cec0c9d08aa6603b4ce8d60d9a3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07Use more secure HTTPS URLs for coreboot sitesPaul Menzel
The coreboot sites support HTTPS, and requests over HTTP with SSL are also redirected. So use the more secure URLs, which also saves a request most of the times, as nothing needs to be redirected. Run the command below to replace all occurences. ``` $ git grep -l -E 'http://(www.|review.|)coreboot.org' | xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g' ``` Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/20034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-06fsp1_1: Verify FSP_IMAGE_ID/_REV against headersNico Huber
FSP_IMAGE_ID and FSP_IMAGE_REV are defined in `FspUpdVpd.h`. Check against these to avoid mismatching definitions in coreboot and the FSP blob. Change-Id: Ic86229e7f0c2d0525b8a79add292c6c81a349aa6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-05intel/gma: Fix typo GMBUS0 -> GMBUS1 in edid.cSebastian "Swift Geek" Grzywna
This typo existed in code before rewriting for using defines and it's clearly visible after rewrite. Previously it was writing to reserved area of GMBUS0 register, while values are matching those of GMBUS1. This line probably is a no-op since it's just sending the STOP again (without an address set this time). Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/16341 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-04Kconfig: Add choice of framebuffer modeNico Huber
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for `HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model that with additional symbols. Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-04console/flashsconsole: Add spi flash console for debuggingYouness Alaoui
If CONSOLE_SPI_FLASH config is enabled, we write the cbmem messages to the 'CONSOLE' area in FMAP which allows us to grab the log when we read the flash. This is useful when you don't have usb debugging, and UART lines are hard to find. Since a failure to boot would require a hardware flasher anyways, we can get the log at the same time. This feature should only be used when no alternative is found and only when we can't boot the system, because excessive writes to the flash is not recommended. This has been tested on purism/librem13 v2 and librem 15 v3 which run Intel Skylake hardware. It has not been tested on other archs or with a driver other than the fast_spi. Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers that support a linear framebuffer. Some related settings moved to the drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are hardcoded. Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-02Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER. * Let drivers select it if they are in charge. * Don't select it on the mainboard level if a driver handles it. Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-31rx6110sa: Add possibility to use both I2C and SMBus for the RTCWerner Zeh
The driver for the RTC RX6110SA is designed to be used with I2C bus. This patch adds the possibility to use SMBus operations to access the RTC. For this purpose the Kconfig switch RX6110SA_USE_SMBUS is added. It is not enabled per default so that I2C will be used. One can set this switch on board level to use SMBus instead. Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19978 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-30lib/edid: Split out fill_lb_framebuffer()Nico Huber
Place it into new edid_fill_fb.c, and invert the logic of the Kconfig guard (NATIVE_VGA_INIT_USE_EDID is now !NO_EDID_FILL_FB). It has to be selected by all drivers that use MAINBOARD_DO_NATIVE_VGA_INIT but pro- vide their own fill_lb_framebuffer() implementation. Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-29gma/acpi: Fix argument count to _DSSMatt DeVillier
As the comment above the change indicates, and per ACPI spec, _DSS has one argument. Change-Id: Ic05832d412cd0c89ed3a275c4db694a9118dac28 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-24drivers/spi/spi-generic: Make spi_setup_slave strong symbolFurquan Shaikh
Now that all platforms are updated to provide spi bus map, there is no need to keep the spi_setup_slave as a weak symbol. BUG=b:38430839 Change-Id: I59b9bbb5303dad7ce062958a0ab8dee49a4ec1e0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-22Kconfig: Move and clean up CONFIG_VGANico Huber
Change-Id: I6e710b95cade0ea68f787f33c0070613d64b6da6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-05-22drivers/intel/gma: Drop unused INTEL_DPNico Huber
Change-Id: I786848cd48c6fcfecf9b72c60623cadcfcbb7db7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/19803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-05-19drivers/spi/spi_flash: Move flash ops to spi_flash_ops structureFurquan Shaikh
Define a new spi_flash_ops structure, move all spi flash operations to this structure and add a pointer to this structure in struct spi_flash. BUG=b:38330715 Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19drivers/spi/spi_flash: Clean up SPI flash probeFurquan Shaikh
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it so that drivers can use it outside spi_flash.c. 2. Make southbridge intel spi driver use spi_flash_generic_probe if spi_is_multichip returns 0. 3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to provide specialized probe functions. With this change, the specialized spi flash probe functions are now associated with a particular spi ctrlr structure and no longer disconnected from the spi controller. BUG=b:38330715 Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-19drivers/spi/spi_flash: Pass in spi_slave structure as const to probe functionsFurquan Shaikh
Pointer to spi_slave structure can be passed in as const to spi flash probe functions since the probe functions do not need to modify the slave properties. BUG=b:38330715 Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19707 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19drivers/spi/spi_flash_internal: Remove unused spi_fram_probe_ramtronFurquan Shaikh
Remove unused function declaration spi_fram_probe_ramtron. BUG=b:38330715 Change-Id: I05e6c5c2b97d6c8a726c0e443ad855f9bcb703f9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19706 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19drivers/spi/spi_flash: Pass in flash structure to fill in probeFurquan Shaikh
Instead of making all SPI drivers allocate space for a spi_flash structure and fill it in, udpate the API to allow callers to pass in a spi_flash structure that can be filled by the flash drivers as required. This also cleans up the interface so that the callers can maintain and free the space for spi_flash structure as required. BUG=b:38330715 Change-Id: If6f1b403731466525c4690777d9b32ce778eb563 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19drivers/spi/spi_flash: Add page_size to struct spi_flashFurquan Shaikh
Add a new member page_size to spi_flash structure so that the various spi flash drivers can store this info in spi_flash along with the other sizes (sector size and total size) during flash probe. This removes the need to have {driver}_spi_flash structure in every spi flash driver. This is part of patch series to clean up the SPI flash and SPI driver interface. BUG=b:38330715 Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19drivers/spi/spi_flash: Use boot_device_spi_flash to obtain spi_flash structureFurquan Shaikh
Instead of storing spi flash device structure in spi flash driver, use boot_device_spi_flash callback to obtain pointer to boot device spi flash structure. BUG=b:38330715 Change-Id: Idd50b7644d1a4be8b62d38cc9239feae2215103c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-19drivers/spi/cbfs_spi: Provide implementation of boot_device_spi_flashFurquan Shaikh
This allows callers to retrieve handle to the boot device spi_flash structure. BUG=b:38330715 Change-Id: I1c07327115e0449cbd84d163218da76a6fa2cea0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-18vbe: remove the necessity for a global vbe_mode_info_valid()Aaron Durbin
There's no users of vbe_mode_info_valid() aside from the local compilation units. Remove the declaration and make the function static to the current global implementers. Change-Id: I4872ac6ad15ba6a86bba69d51a8348b9921c152d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-18coreboot_tables: specify clear interface for lb_framebuffer()Aaron Durbin
For some reason the "interface" for adding framebuffer information is sitting in src/include/vbe.h while also guarding the call to fill_lb_framebuffer() with vbe_mode_info_valid() along with some macro if CONFIG_* for good measure. Move the fill_lb_framebuffer() declaration to coreboot_tables.h and provide a comment about how it should be used. Also, now that there's no need for the notion of a global vbe_mode_info_valid() remove it from the conditional call path of fill_lb_framebuffer(). Change-Id: Ib3ade6314624091ae70424664527a02b279d0c9b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-18uart: Fix bug in {uart8250, uart8250_mem, ns16550}_rx_byte functionsWerner Zeh
We have several different UART implementations of which three support a timeout when receiving characters. In all of these three implementations there is a bug where when the timeout is hit the last received character will be returned instead of the needed 0. The problem is that the timeout variable i is decremented after it has been checked in the while-loop. That leads to the fact that when the while-loop is aborted due to a timeout i will contain 0xffffffff and not 0. Thus in turn will fool the following if-statement leading to wrong return value to the caller in this case. Therefore the caller will see a received character event if there is none. Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-13drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.cNico Huber
And don't link it. It's for ROMCC. To make code happy that uses the ROMCC interface read_option(), read_option_lowlevel() is ported to mc146818rtc.c along with a message to use get_option() instead. Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-12commonlib: Move drivers/storage into commonlib/storageLee Leahy
Move drivers/storage into commonlib/storage to enable access by libpayload and indirectly by payloads. * Remove SD/MMC specific include files from include/device * Remove files from drivers/storage * Add SD/MMC specific include files to commonlib/include * Add files to commonlib/storage * Fix header file references * Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver * Add Kconfig source for commonlib/storage * Rename *DEVICE* to *COMMONLIB* * Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE* TEST=Build and run on Galileo Gen2 Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-12drivers/storage: Delay after SD SWITCH operationsLee Leahy
Delay for a while after the switch operations to let the card recover. TEST=Build and run on Galileo Gen2 Change-Id: I938e227a142e43ed6afda80d56af90df0bae1b05 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-05-11drivers/i2c: Add new driver for RTC type RX6110 SAMario Scheithauer
This driver enables the usage of the external RTC chip RX6110 SA (http://www5.epsondevice.com/en/products/i2c/rx6110sab.html) which is connected to the I2C bus. The I2C address of this device is fixed. One can change parameters in the device tree so that the used setup can be adapted to match the configuration of the device on the mainboard. Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/19625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-05-10drivers/storage: Fix array referencesLee Leahy
Fix bug detected by coverity to handle the zero capacity case. Specific changes: * Reduce loop count by one to handle zero capacity case * Use structure instead of dual arrays * Move structures into display_capacity routine Coverity Issues: * 1374931 * 1374932 * 1374933 * 1374934 TEST=Build and run on Galileo Gen2 Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-10drivers/storage: Remove set_control_regLee Leahy
Remove unused field in generic SD/MMC controller data structure. TEST=Build and run on Galileo Gen2 Change-Id: I7169dca07509a6f2513d62b593742daf764010b2 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/19629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-08drivers/intel/wifi: provide weak get_wifi_sar_limits()Aaron Durbin
Provide a failing get_wifi_sar_limits() to allow SAR Kconfig options to be selected without relying on CHROMEOS which currently has the only code to provide SAR data. Change-Id: I1288871769014f4c4168da00952a1c563015de33 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19580 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-05drivers/spi: Re-factor spi_crop_chunkFurquan Shaikh
spi_crop_chunk is a property of the SPI controller since it depends upon the maximum transfer size that is supported by the controller. Also, it is possible to implement this within spi-generic layer by obtaining following parameters from the controller: 1. max_xfer_size: Maximum transfer size supported by the controller (Size of 0 indicates invalid size, and unlimited transfer size is indicated by UINT32_MAX.) 2. deduct_cmd_len: Whether cmd_len needs to be deducted from the max_xfer_size to determine max data size that can be transferred. (This is used by the amd boards.) Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: coreboot org <coreboot.org@gmail.com>
2017-05-05drivers/pc80/tpm: Fix missing tis_close() functionPhilipp Deppenwiese
tis_close() must be called after tis_open() otherwise the locked locality isn't released and the sessions hangs. Tested=PC Engines APU2 Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/19535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-05-03drivers/{aspeed,xgi_z9s}/Kconfig: Don't override NATIVE_VGA_USE_EDIDArthur Heymans
device is run before drivers to generate .config and the first default takes precedence so this override achieves nothing. Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-03lib/edid.c: Differentiate between absent and non-conformant EDIDArthur Heymans
Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-28drivers/intel/fsp2_0: add option to incorporate platform memory versionAaron Durbin
On Chrome OS systems a memory setting change is needed to be deployed without updating the FSP blob proper. Under such conditions one needs to trigger retrain of the memory. For ease of use provide an option, FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC and mainboard memory setting version number into the FSP version passed to the platform. The lower 8 bits of the FSP version are the build number which in practice is normally 0. Use those 8 bits to include the SoC and mainboard memory settings version. When FSP, SoC, or mainboard memory setting number is bumped a retrain will be triggered. BUG=b:37687843 Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19452 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-25lib: provide clearer devicetree semanticsAaron Durbin
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25drivers/storage: Add SD/MMC/eMMC driver based upon depthchargeLee Leahy
The SD/MMC support is broken into several pieces. There are three main data structures: * sdhci_ctrlr - This is SDHCI controller specific and defined in include/device/sdhci.h * sd_mmc_ctrlr - This contains generic controller management data and defined in include/device/sd_mmc_ctrlr.h * storage_media - This contains the flash storage device management data and is defined in include/device/storage.h The SD/MMC driver consists of several components: * SDHCI controller code * bouncebuf.c * bouncebuf.h * pci_sdhci.c * sdhci.c * sdhci.h * sdhci_adma.c * sdhci_display.c * Flash storage device support * mmc.c * mmc.h * sd.c * sd_mmc.c * sd_mmc.h * storage.c * storage.h * storage_erase.c * storage_write.c Kconfig values enable various portions of the controller and storage drivers to be built to reduce the overall size of what is included in the final image. Full read/write/erase operations are provided for those platforms which want to take advantage. It is also possible to build the driver to perform initialization only. By default, this driver is not included in any platform, platforms must specifically select DRIVERS_STORAGE to add the SD/MMC support. After this patch is reviewed and merged, there are some additional patches: * Common CAR storage area - Use a predefined region of CAR to pass data structures between bootblock through to romstage. This allows early stages to preform the SD/MMC device initialization and later stages to use the SD/MMC device without further initialization. The example code initializes the SD/MMC device in bootblock and uses the SD/MMC device in romstage without further initialization. * CBMEM ID - Add a CBMEM ID value for the data structures so that they may be passed from romstage to ramstage and eventually the payload. The example uses the SD/MMC device in ramstage without further initialization. * Move the SD/MMC driver into commonlib * Have libpayload build the SD/MMC driver from commonlib. The intent is to pass the controller state to libpayload so that the SD/MMC device can be used without further initialization. * On some platforms, have depthcharge use the commonlib SD/MMC driver History: Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot and make the following changes: * Removed #include "config.h" from mmc.c, allow the lint tests to pass. * Move include files from drivers/storage into include/device. * Rename mmc.h to storage.h. * Add the Kconfig and Makefile and make edits to get the code to build. * Add support to initialize a PCI controller. * Fix formatting issues detected by checkpatch. * Fix data flow issues detected by checkpatch. * Add the missing voltage (MMC_VDD_35_36) into the voltage mask. * Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*. * Replace printf with sd_mmc_error. * Add sdhc_debug, sdhc_trace and sd_error macros. * Add Kconfig values to enable storage device debugging and tracing. * Add tracing and debug support to the SDHCI driver. * Allow SOC to override more controller features. * Split out ADMA support. * Move 1V8 support into SOC routine. * Move HS400 support into SOC routine. * Rework clock handling. * Change all controller references to use ctrlr. * Update the voltage handling. * Update modes of operation. * Move DMA fields into MmcCtrlr. * Update bus width support. * Change MMC_TIMING_* to BUS_TIMING_*. * Rename MMC_MODE_ to DRVR_CAP. * Move quirks into ctrlr->caps. * Associate removeable with the controller. * Statically allocate MmcMedia. * Replace the SdhciHost structure with the MmcCtrlr structure. * Split the code to support other SD/MMC controllers. * Split out erase and write support. * Update the code to be more consistent with the coreboot coding style. * Only expose calling APIs. * Divide up mmc.c into 4 modules: MMC, SD, storage card, common code. * Update debug and error messages. * Add partition support. * Display clock frequencies once in MHz. * Remove mmc_send_cmd, use ctrlr->send_cmd instead. * Handle error from sd_send_op_cond. * Allow mainboard to control delays around CMD 0. * Support command logging. * Mainboard may set delay after SD/MMC command. * Display serial number with sd_mmc_trace. * Remove cmd set parameter from mmc_switch. * Display errors for timeout and comm errors. * Add LED support. * Move 64bit DMA flag into ctrlr->caps. * Rework PIO transfer routine. * Add HS200 bus tuning. * Add support for HS400. * Use same format for HS400, HS200 and HS52. * Reduce storage_media structure size * Add routine to update code pointers * Add display of storage setup * Display controller setup TEST=Build and run on Reef and Galileo Gen2 Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/19208 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-24drivers/i2c/tpm: Remove vendor.irqDaniel Kurtz
The vendor.irq field was originally intended for use as the TPM 1.2 "command complete" interrupt. However, all actual coreboot tpm drivers and hardware use the vendor.status method of checking command completion instead, and this irq field is not used. Let's just remove this unused functionality to simplify the code. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). TEST=Boot eve w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). Change-Id: I994c5bfbd18124af9cb81d9684117af766ab0124 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19396 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24drivers/i2c/tpm/cr50: Use tis_plat_irq_status for Cr50 IRQ statusDaniel Kurtz
The Cr50 TPM uses an IRQ to provide a "status" signal used for hand-shaking the reception of commands. Real IRQs are not supported in firmware, however firmware can still poll interrupt status registers for the same effect. Commit 94cc485338a3 ("drivers/i2c/tpm/cr50: Support interrupts for status") added support for the Cr50 driver on X86 platforms to use a KConfig file to supply an IRQ which it would poll using acpi_get_gpe. If the IRQ is not supplied, the Cr50 driver inserts a 20 ms wait. Unfortunately this doesn't work so well when using the i2c connected Cr50 on ARM platforms. Luckily, a more generic implementation to allow a mainboard to supply a Cr50 IRQ status polling function was solved for SPI connected Cr50s by commit 19e3d335bddb ("drivers/spi/tpm: using tpm irq to sync tpm transaction"). Let's refactor the i2c c50 driver to use this same approach, and change eve and reef boards to make use of DRIVER_TPM_TIS_ACPI_INTERRUPT for specifying the TPM flow control interrupt. This essentially reverts these two commits: 48f708d199 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe 94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status And ports this commit to i2c/tpm/cr50: 19e3d335bd drivers/spi/tpm: using tpm irq to sync tpm transaction As a side effect the tpm_vendor_specific IRQ field goes back to its original usage as the "TPM 1.2 command complete" interrupt, instead of being repurposed to hold the flow control IRQ. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). TEST=Boot eve w/ serial enabled firmware, verify verstage sees "cr50 TPM" and does not complain about lack of tis_plat_irq_status(). Change-Id: I004329eae1d8aabda51c46b8504bf210484782b4 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19363 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24drivers/spi/tpm: Do not let MAINBOARD_HAS_SPI_TPM_CR50 depend on SPI_TPMDaniel Kurtz
MAINBOARD_HAS_SPI_TPM_CR50 describes a capability of the board and SPI_TPM is only on if we actually want to compile in the TPM code. For example, in src/drivers/i2c/tpm/Kconfig MAINBOARD_HAS_I2C_TPM_CR50 also doesn't depend on SPI_TPM. This problem manifests itself as the following build issue when building with MAINBOARD_HAS_I2C_TPM_CR50 but without an explict "select TPM2": src/Kconfig:296:error: recursive dependency detected! src/Kconfig:296: symbol MAINBOARD_HAS_TPM2 is selected by MAINBOARD_HAS_TPM_CR50 src/Kconfig:408: symbol MAINBOARD_HAS_TPM_CR50 depends on MAINBOARD_HAS_SPI_TPM_CR50 src/drivers/spi/tpm/Kconfig:15: symbol MAINBOARD_HAS_SPI_TPM_CR50 depends on SPI_TPM src/drivers/spi/tpm/Kconfig:1: symbol SPI_TPM depends on TPM2 src/Kconfig:396: symbol TPM2 is selected by MAINBOARD_HAS_TPM2 MAINBOARD_HAS_SPI_TPM_CR50 shouldn't depend on SPI_TPM. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: I0cb3f6d3aa4159bad563a6a4b006d7f4825e04b4 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Suggested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19411 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-24drivers/spi/spiconsole: Fix broken spiconsole driverFurquan Shaikh
Use spi_setup_slave to fill up the spi_slave structure with pointer to spi_ctrlr structure which can then be used to perform all spi operations. Change-Id: I2804ed1e85402426a654352e1ceaf0993546cd8b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19385 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-24drivers/i2c/tpm: Hide ACPI on unsupported platformsPatrick Rudolph
Depend on I2C_TPM to prevent showing the menu entry on systems that do not have an I2C TPM installed. Change-Id: I7cd647c9c7e9721eab96ab64b844a882f156ee68 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19374 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-04-24*.asl: Remove obsolete reference to TPM ASL filePatrick Rudolph
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static and empty ASL file. Delete src/drivers/pc80/tpm/acpi/tpm.asl. Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19drivers/intel/mipi_camera: Add MIPI CSI camera SSDT generatorV Sowmya
Add SSDT generator for MIPI CSI camera to create ACPI objects used by the Intel kernel drivers. * SSDB: Sensor specific database for camera sensor. * PWDB: Power database for all the camera devices. * CAMD: ACPI object to specify the camera device type. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated SSDT table has the required entries. Change-Id: Ief9e56d12b64081897613bf1c7abcdf915470b99 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18967 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-04-19elog: Print timestamp when logging eventJulius Werner
We're already reading the RTC whenever we file an event, we might as well print out the value at that time. Having a few RTC timestamps in the firmware log makes it easier to correlate that part of the log to a particular boot once we start having multiple boots in the log. Change-Id: I750dd18aa2c43c95b8c1fbb8f404c1e3a77bec73 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19305 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13drivers/spi/tpm: Clean up SPI TPM driverFurquan Shaikh
1. Move common TIS macros to include/tpm.h. 2. Use common TIS macros while referring to status and access registers. 3. Add a new function claim_locality to properly check for required access bits and claim locality 0. BUG=b:36873582 Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19213 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-09drivers/spi: Get rid of spi_get_configFurquan Shaikh
There is only one user for spi_get_config i.e. SPI ACPI. Also, the values provided by spi_get_config are constant for now. Thus, get rid of the spi_get_config call and fill in these constant values in SPI ACPI code itself. If there is a need in the future to change these, appropriate device-tree configs can be added. BUG=b:36873582 Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-083rdparty/libgfxinit: Update submodule pointerNico Huber
Some renamings force us to update our code: * Scan_Ports() moved into a new package Display_Probing. * Ports Digital[123] are called HDMI[123] now (finally!). * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`. Other noteworthy changes in libgfxinit: * libgfxinit now knows about ports that share pins (e.g. HDMI1 and DP1) and refuses to enable any of them if both are connected (which is physically possible on certain ThinkPad docks). * Major refactoring of the high-level GMA code. Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-05drivers/spi/tpm: Allow TPM_SPI to be used with PC80_SYSTEM.Furquan Shaikh
In order to be able to use SPI TPM on x86, allow TPM_SPI to be used with PC80_SYSTEM. BUG=b:35583330 Change-Id: Ibe626a192d45cf2624368db42d369202a4003123 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19093 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05drivers/spi/tpm: Make SPI TPM driver CAR-safeFurquan Shaikh
1. Use proper CAR semantics for global/static variables. 2. Use spi_* functions directly instead of using a global structure to store pointers to those functions. BUG=b:36873582 Change-Id: I1fc52ab797ef0cbd3793a387d68198efc5dde58c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05drivers/spi/tpm: using tpm irq to sync tpm transactionJeffy Chen
BUG=b:35647967 TEST=boot from bob Change-Id: Ib64107b17fb6e93dbe626ce92f3bc9da8b84784e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/452284 Commit-Ready: Caesar Wang <wxt@rock-chips.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19113 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05drivers/spi/tpm: try to wake cr50 if it is asleepJeffy Chen
BUG=b:35775002 TEST=boot from bob Change-Id: I6324f3c02da55a8527f085ba463cbb1f4fb5dc2e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/452283 Commit-Ready: Caesar Wang <wxt@rock-chips.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19112 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-05drivers/spi/tpm: Add tis.c and tpm.c to ramstage and romstageFurquan Shaikh
These files are required to support recovery MRC cache hash save/restore in romtage/ramstage. BUG=b:35583330 Change-Id: Idd0a4ee1c5f8f861caf40d841053b83a9d7aaef8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19092 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-03drivers/i2c/tpm: remove 1260 byte buffer from stackAaron Durbin
The tis.c module is needlessly copying data to/from a 1260 byte buffer on the stack. Each device's transport implementation (cr50.c or tpm.c) maintains its own buffer, if needed, for framing purposes. Therefore, remove the duplicated buffer. BUG=b:36598499 Change-Id: I478fb57cb65509b5d74bdd871f1a231f8080bc2f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19061 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/i2c/tpm: remove unused variable in tpm_transmit()Aaron Durbin
The 'ordinal' variable is not used. Remove it. BUG=b:36598499 Change-Id: I015a6633c0951980658b3c879e48bc84d604d62e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19060 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-03drivers/i2c/tpm: remove unused types from tpm.hAaron Durbin
There are unused structures/types in the tpm.h header file. Remove them. BUG=b:36598499 Change-Id: Iddc147640dcec70e80791846eb46298de1070672 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19059 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/spi/tpm: honor tis_sendrecv() APIAaron Durbin
The spi tis_sendrecv() implementation was always returning success for all transactions. Correct this by returning -1 on error when tpm2_process_command() returns 0 since that's its current failure return code. BUG=b:36598499 Change-Id: I8bfb5a09198ae4c293330e770271773a185d5061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19058 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/spi/tpm: make tpm_info object local to compilation unitAaron Durbin
The tpm_info object is a global, but its symbol does not need to be exposed to the world as its only used within tpm.c. BUG=b:36598499 Change-Id: Idded3dad8d0d1c3535bddfb359009210d3439703 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19057 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-03drivers/spi/tpm: de-assert chip select on transaction errorAaron Durbin
In the case of start_transaction() failing the chip select is never deasserted. Correct that by deasserting the chip select when start_transaction() fails. BUG=b:36598499 Change-Id: I2c5200085eb357259edab39c1a0fa7b1d81ba7b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19056 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-03nb/intel: Deduplicate vbt headerPatrick Rudolph
Move header and delete duplicates. Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18903 Tested-by: build bot (Jenkins) Tested-by: coreboot org <coreboot.org@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-31drivers/intel/gma: Guard GFX_GMA_* configsNico Huber
It's confusing to have these Kconfig symbols for non-Intel boards. Change-Id: I4903c816258e5d2b8ed8704295b777aee175e8bc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18795 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-03-28Remove libverstage as separate library and source file classJulius Werner
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are linked directly into the bootblock or the romstage. However, they're still compiled with a separate "libverstage" source file class, linked into an intermediate library and then linked into the final destination stage. There is no obvious benefit to doing it this way and it's unclear why it was chosen in the first place... there are, however, obvious disadvantages: it can result in code that is used by both libverstage and the host stage to occur twice in the output binary. It also means that libverstage files have their separate compiler flags that are not necessarily aligned with the host stage, which can lead to weird effects like <rules.h> macros not being set the way you would expect. In fact, VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86 because their libverstage code that gets compiled into the romstage sets ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to run pre-migration. This patch resolves these problems by removing the separate library. There is no more difference between the 'verstage' and 'libverstage' classes, and the source files added to them are just treated the same way a bootblock or romstage source files in configurations where the verstage is linked into either of these respective stages (allowing for the normal object code deduplication and causing those files to be compiled with the same flags as the host stage's files). Tested this whole series by booting a Kevin, an Elm (both with and without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode. Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18302 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28soc/intel/common/block: Add cache as ram init and teardown codeSubrata Banik
Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18381 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-18nb/i945/gma.c: Refactor panel setupArthur Heymans
This reuses some of gm45 code to set up the panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. A default of 180Hz is selected for the PWM frequency if it is not defined in the devicetree, this might be annoying for displays that are LED backlit, but is a safe value for CCFL backlit displays. Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-17drivers/intel/fsp1_1: Fix issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" WARNING: line over 80 characters WARNING: else is not generally useful after a break or return WARNING: braces {} are not necessary for single statement blocks WARNING: suspect code indent for conditional statements (16, 32) WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18886 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 21:16:01 +0000