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2016-09-12driver/fsp2_0: Include stdint header file in api.hNaresh G Solanki
'bool' type is reported undefined due to missing stdint.h inclusion, Fix it by including the same. Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-08intel/gma: Use defines for registers and values in edid.cSebastian "Swift Geek" Grzywna
This replaces magic values with defines without changing any value. Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com> Reviewed-on: https://review.coreboot.org/16339 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08drivers/i2c/tpm: Fix early TPM probeDuncan Laurie
The early TPM probe was done directly in tis.c ignoring the lower layer that provides appropriate access to the chip. Move this into a tpm_vendor_probe() function so it can use iic_tpm_read() with all of the built-in delays and semantics instead of calling i2c_readb() directly from the wrong layer. This fixes early init failures that were seen with the cr50 i2c tpm on the reef mainboard. Change-Id: I9bb3b820d10f6e2ea24c57b90cf0edc813cdc7e0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16527 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-06drivers/i2c/tpm: Fix error handling for tis structure not initializedDuncan Laurie
If the TPM completely fails to respond then the vendor structure may not have assigned handlers yet, so catch that case and return error so the boot can continue to recovery mode instead of asserting over and over. Change-Id: If3a11567df89bc73b4d4878bf89d877974044f34 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-06drivers/i2c/tpm: Add support for generating ACPI tableDuncan Laurie
Add code to generate an ACPI descriptor for an I2C TPM based on the device as described in devicetree.cb. This currently requires the devicetree to provide the HID, since we don't currently talk to the TPM in ramstage and I didn't want to add yet another init path for it here. This was tested on a reef board to ensure that the device is described properly in the SSDT. Change-Id: I43d7f6192f48e99a4074baa4e52f0a9ee554a250 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16397 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06drivers/i2c/tpm: Add support for cr50 TPMDuncan Laurie
Add support for the cr50 TPM used in apollolake chromebooks. This requires custom handling due to chip limitations, which may be revisited but are needed to get things working today. - timeouts need to be longer - must use the older style write+wait+read read protocol - all 4 bytes of status register must be read at once - same limitation applies when reading burst count from status reg - burst count max is 63 bytes, and burst count behaves slightly differently than other I2C TPMs - TPM expects the host to drain the full burst count (63 bytes) from the FIFO on a read Luckily the existing driver provides most abstraction needed to make this work seamlessly. To maximize code re-use the support for cr50 is added directly instead of as a separate driver and the style is kept similar to the rest of the driver code. This was tested with the cr50 TPM on a reef board with vboot use of TPM for secdata storage and factory initialization. Change-Id: I9b0bc282e41e779da8bf9184be0a11649735a101 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16396 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-06drivers/i2c/tpm: Allow sleep durations to be set by the chipDuncan Laurie
Allow the sleep durations used by the driver to be set by the specific chip so they can be tuned appropriately. Since we need to read the chip id to know the values use very conservative defaults for the first command and then set it to the current values by default. Change-Id: Ic64159328b18a1471eb06fa8b52b589eec1e1ca2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16395 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-06drivers/i2c/tpm: Make driver safe for use in x86 pre-ramDuncan Laurie
Use CAR accessors where needed for accessing static data. In some cases this required some minor restructuring to pass in a variable instead of use a global one. For the tpm_vendor_init the structure no longer has useful defaults, which nobody was depending on anyway. This now requires the caller to provide a non-zero address. Tested by enabling I2C TPM on reef and compiling successfully. Change-Id: I8e02fbcebf5fe10c4122632eda1c48b247478289 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16394 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-02apollolake: relocate fsp header files to vendorcodeBrandon Breitenstein
FSP header files should be located in vendorcode, not soc directory. This patch includes changes any references to the old location to the new location. Change-Id: I44270392617418ec1b9dec15ee187863f2503341 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31src/drivers: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16321 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31parade/ps8640: disable mipi mcsJitao Shi
Disable ps8640 mipi mcs function to avoid recognizing the normal mipi dsi signal as msc cmd. BUG=chrome-os-partner:56346 BRANCH=none TEST=build pass elm and show ui Change-Id: I91c690fb1ff3bd9b5c1f227205829c914347cd30 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4fd441b46300fea9f238b27c9c1cda4e9e53c80d Original-Change-Id: I85b9f1e6677e4bf8ab1e30c2e69445079fff2d18 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/373219 Original-Commit-Ready: Daniel Kurtz <djkurtz@chromium.org> Original-Tested-by: jitao shi <jitao.shi@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/16365 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31parade/ps8640: add delay to every loop when polling ps8640 readyJitao Shi
Add delay before and in polling ps8640 ready to reduce the frequency of polling. BUG=chrome-os-partner:54897 BRANCH=none TEST=build pass elm and show ui Change-Id: I43c833af910490e53496a343330a6a6af35623a9 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bc8c3d6f7cf0b2da693a465cf3845e8bbc53825a Original-Change-Id: I5c725eed8110ff9f545c1142ca28bcff336b6860 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/371718 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Tested-by: jitao shi <jitao.shi@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/16364 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31driver/intel/fsp2.0: Add External stage cache region helperRizwan Qureshi
If ramstage caching outside CBMEM is enabled i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a helper function to determine the caching region in SMM should be implemented. Add the same to FSP2.0 driver. FSP1.1 driver had the same implementation hence copied stage_cache.c. The SoC code should implement the smm_subregion to provide the base and size of the caching region within SMM. The fsp/memmap.h provides the prototype and we will reuse the same from FPS 1.1. Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16312 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-25vboot: consolidate google_chromeec_early_init() callsAaron Durbin
On x86 platforms, google_chromeec_early_init() is used to put the EC into RO mode when there's a recovery request. This is to avoid training memory multiple times when the recovery request is through an EC host event while the EC is running RW code. Under that condition the EC will be reset (along with the rest of the system) when the kernel verification happens. This leads to an execessively long recovery path because of the double reboot performing full memory training each time. By putting this logic into the verstage program this reduces the bootblock size on the skylake boards. Additionally, this provides the the correct logic for all future boards since it's not tied to FSP nor the mainboard itself. Lastly, this double memory training protection works only for platforms which verify starting from bootblock. The platforms which don't start verifying until after romstage need to have their own calls (such as haswell and baytrail). Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16318 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-24drivers/spi: remove unconditional RW boot device initializationAaron Durbin
The SPI drivers for the various chipsets are not consistent in their handling of when they are accessible. Coupled with the unknown ordering of boot_device_init() being called this can lead to unexpected behavior (probing failures or hangs). Instead move the act of initializing the SPI flash boot device to when the various infrastructure requires its usage when it calls boot_device_rw(). Those platforms utilizing the RW boot device would need to ensure their SPI drivers are functional and ready when the call happens. This further removes any other systems failing to boot as reported in https://ticket.coreboot.org/issues/67. BUG=chrome-os-partner:56151 Change-Id: Ib3bddf5e26bf5322f3dd20345eeef6bee40f0f66 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16300 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-08-23drivers/spi: be sure to call spi_init() before spi_flash_probe()Aaron Durbin
It's necessary to call spi_init() prior to calling spi_flash_probe() such that the SPI drivers can do any work required prior to performing SPI transactions. It could be argued that the drivers should handle such situations, however the SPI API implementations seem to assume the callers ensured spi_init() was called before any SPI transactions. This fixes systems that failed to boot introduced by [1]. Issue tracked in https://ticket.coreboot.org/issues/67. [1] I2aa75f88409309e3f9b9bd79b52d27c0061139c8 https://review.coreboot.org/16200 BUG=chrome-os-partner:56151 Change-Id: I2d8d5ac685833521f1efe212b07a4b61ba0d9bc3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16297 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-08-20drivers/intel/fsp2_0: Add SMBIOS memory HOB supportRavi Sarawadi
Add SMBIOS memory GUID and functions to retrieve HOB. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ie7e2239bb691c748d9fd852c3dc8cdc05243b164 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-19drivers/elog: use region_device for NV storageAaron Durbin
Instead of assuming SPI backing use a region_device to abstract away the underlying storage mechanism. BUG=chrome-os-partner:55932 Change-Id: I6b0f5a7e9bea8833fb1bca87e02abefab63acec3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16204 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19drivers/spi: provide optional implementation of boot_device_rw()Aaron Durbin
On many x86 platforms the boot device is SPI which is memory mapped. However, in order to write to the boot device one needs to use the SPI api. Therefore, provide a common implementation of boot_device_rw() which has no mmap() functionality. It only reads, writes, and erases. This will be used in the existing infrastructure but in a SPI agnostic way. Two options are added: 1. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP 2. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY The former is auto-selected when COMMON_CBFS_SPI_WRAPPER is not selected. The latter can be used to include the implementation in the early stages such as bootblock, verstage, and romstage. BUG=chrome-os-partner:56151 Change-Id: I2aa75f88409309e3f9b9bd79b52d27c0061139c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16200 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19drivers/spi: include SPI flash modules for all stagesAaron Durbin
It shouldn't matter if COMMON_CBFS_SPI_WRAPPER is selected to include the SPI flash support in all stages. Therefore, include the SPI flash support files in all the stages. While there include the same set of files for all stages. They were out of sync for some reason. BUG=chrome-os-partner:56151 Change-Id: I933335104203315cbbcf965185a7c176974e6356 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16198 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19drivers/spi: ensure SPI flash is boot device for coreboot tablesAaron Durbin
The spi_flash_probe() routine was setting a global varible unconditonally regardless if the probe was for the boot device or even if the boot devcie was flash. Moreover, there's no need to report the SPI information if the boot device isn't even SPI. Lastly, it's possible that the boot device is a SPI flash, but the platform may never probe (selecting SPI_FLASH) for the actual device connected. In that situation don't fill anything in as no correct information is known. BUG=chrome-os-partner:56151 Change-Id: Ib0eba601df4d77bede313c358c92b0536355bbd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16197 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19lib/cbfs_spi: provide boot_device_rw() supportAaron Durbin
Provide the RW boot device operations for the common cbfs SPI wrapper. The RW region_device is the same as the read-only one. As noted in the boot_device_rw() introduction patch the mmap() support should not be used in conjuction with writing as that results in incoherent operations. That's fine as the current mmap() support is only used in the cbfs layer which does not support writing, i.e. no cbfs regions would be written to with any previous or outstanding mmap() calls. BUG=chrome-os-partner:56151 Change-Id: I7cc7309a68ad23b30208ac961b1999a79626b307 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16199 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19Kconfig: introduce writable boot device notionAaron Durbin
Indicate to the build system that a platform provides support for a writable boot device. The following will provide the necessary support: COMMON_CBFS_SPI_WRAPPER users soc/intel/apollolake soc/intel/baytrail soc/intel/braswell soc/intel/broadwell soc/intel/skylake The SPI_FLASH option is auto-selected if the platform provides write supoprt for the boot device and SPI flash is the boot device. Other platforms may provide similar support, but they do that in a device specific manner such as selecting SPI_FLASH explicitly. This provides clearance against build failures where chipsets don't provide SPI API implementations even though the platform may use a SPI flash to boot. BUG=chrome-os-partner:56151 Change-Id: If78160f231c8312a313f9b9753607d044345d274 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19drivers/spi: move cbfs_spi.c locationAaron Durbin
The common boot device spi implementation is very much specific to SPI flash. As such it should be moved into that subdirectory. It's still a high-level option but it correctly depends on BOOT_DEVICE_SPI_FLASH. Additionally that allows the auto-selection of SPI_FLASH by a platform selecting COMMON_CBFS_SPI_WRAPPER which allows for culling of SPI_FLASH selections everywhere. BUG=chrome-os-partner:56151 Change-Id: Ia2ccfdc9e1a4348cd91b381f9712d8853b7d2a79 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16212 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19Kconfig: separate memory mapped boot device from SPIAaron Durbin
Make the indication of the boot device being memory mapped separate from SPI. However, retain the same defaults that previously existed. BUG=chrome-os-partner:56151 Change-Id: I06f138078c47a1e4b4b3edbdbf662f171e11c9d4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16228 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19tpm2: Fixed typoRobert Foss
Fixed "intierface" typo. Change-Id: I65f0156ee059a8bed96c900ca3da3a06f45901e8 Signed-off-by: Robert Foss <robert.foss@collabora.com> Reviewed-on: https://review.coreboot.org/16252 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-18Kconfig: lay groundwork for not assuming SPI flash boot deviceAaron Durbin
Almost all boards and chipsets within the codebase assume or use SPI flash as the boot device. Therefore, provide an option for the boards/chipsets which don't currently support SPI flash as the boot device. The default is to assume SPI flash is the boot device unless otherwise instructed. This falls in line with the current assumptions, but it also allows one to differentiate a platform desiring SPI flash support while it not being the actual boot device. One thing to note is that while google/daisy does boot with SPI flash part no SPI API interfaces were ever implemented. Therefore, mark that board as not having a SPI boot device. BUG=chrome-os-partner:56151 Change-Id: Id4e0b4ec5e440e41421fbb6d0ca2be4185b62a6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16191 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-15Revert "Kconfig: separate memory mapped boot device from SPI"Aaron Durbin
This reverts commit a83bbf58541cf41ea7a97dedbc8c02dffa59e86d. This was submitted out of order. Change-Id: Ic5a28faf94c1f1901a72e46343722eb4224c5086 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16226 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-15drivers/spi: provide option to not include all flash driversAaron Durbin
All flash drivers are automatically included in the build unless COMMON_CBFS_SPI_WRAPPER was selected. However, there are cases where these drivers are unnecessary such as certain intel platforms where spi controller uses hardware sequencing without any ability to manually probe the device. Therefore, provide an option that the SoC can set the default value for. The COMMON_CBFS_SPI_WRAPPER option is still honored by not including all drivers when that is selected. BUG=chrome-os-partner:56151 Change-Id: Ie9aa447da450f7c8717545f05cff800139a9e2dd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16187 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-15Kconfig: separate memory mapped boot device from SPIAaron Durbin
Make the indication of the boot device being memory mapped separate from SPI. However, retain the same defaults that previously existed. BUG=chrome-os-partner:56151 Change-Id: Ibdd7c8754f9bf560a878136b1f55238e2c2549d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16193 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-14drivers/elog: provide more debug infoAaron Durbin
Provide more informative messages when CONFIG_ELOG_DEBUG is enabled as well as more informative error messages in the case of elog_scan_flash() failing. In the sync path the in-memory buffer is dumped in before the contents are read back from the non-volatile backing store and dumped again if the subsequent parsing fails. BUG=chrome-os-partner:55932 Change-Id: I716adfb246ef6fbefc0de89cd94b3c1310468896 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-12drivers/intel/fsp2_0: Fix FSP reset pathLee Leahy
Don't verify HOB list pointer or HOBs when FSP returns a reset request. BRANCH=none BUG=chrome-os-partner:56159 TEST=Build and run on Galileo Gen2. Change-Id: I6382f5ff92092623955806ebff340608c4ee156a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/16162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11intel/fsp1_1: Use new per-region position overridePatrick Georgi
It cooperates better with the file sorting heuristic. Change-Id: I1c071243720352970dd2c4c2afed12451f91dcaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16141 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10drivers/intel/fsp2_0: Add fsp_write_line functionLee Leahy
Add fsp_write_line function which may be called by FSP to output debug serial data to the console. TEST=Build and run on Galileo Gen2 Change-Id: If7bfcea1af82209dcdc5a9f9f2d9334842c1595e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-10drivers/intel/fsp1_1: Add fsp_write_line functionLee Leahy
Add fsp_write_line function which may be called by FSP to output debug serial data to the console. TEST=Build and run on Galileo Gen2 Change-Id: Ib01aef448798e47ac613b38eb20bf25537b9221f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16128 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10elog: Ensure eventlog will always get initialized when configured inJulius Werner
Commit 0d9cd92e (chromeos: Clean up elog handling) removed the individual elog_init() calls from mainboards that did them and automated adding certain events through the boot state machine. Unfortunately, the new code would sometimes not log any specific event at all, and thereby also never call elog_init() (through elog_add_event()) which adds the "System boot" event. We can assume that any board that configures the eventlog at all actually wants to use it, so let's just add another call to elog_init() to the boot state machine so we can ensure it gets called at least once. BRANCH=None BUG=chrome-os-partner:56001 TEST=Booted Kevin, confirmed that eventlog code runs again. Change-Id: Ibe7bfc94b3e3d11ba881399a39f9915991c89d8c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16118 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-09drivers/elog: provide return status for all operationsAaron Durbin
Instead of relying on global state to determine if an error occurred provide the ability to know if an add or shrink operation is successful. Now the call chains report the error back up the stack and out to the callers. BUG=chrome-os-partner:55932 Change-Id: Id4ed4d93e331f1bf16e038df69ef067446d00102 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16104 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-09drivers/elog: clean up SMBIOS related codeAaron Durbin
Don't conditionally compile parts of the code. The unused pieces get culled by the linker, and the #if's just clutter things up. BUG=chrome-os-partner:55932 Change-Id: Ic18b2deb0cfef7167c05f0a641eae2f4cdc848ee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16102 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-09drivers/elog: consolidate checks in elog_find_flash()Aaron Durbin
There were checks against global variables trying to determine failing cases of elog_find_flash(). Instead move the checks into elog_find_flash() and return value indicating failure. A minimum 4KiB check was added to ensure the eventlog is at least that size which makes the heuristic checks cleaner. BUG=chrome-os-partner:55932 Change-Id: I4d9d13148555e05d4f217a10f995831a0e437fc3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16101 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-09drivers/elog: remove unnecessary global stateAaron Durbin
There were 3 variables indicating the state of the event log region. However, there's no need to keep track of those individually. The only thing required is to know is if elog_scan_flash() failed. There's no other tracking required beyond that. BUG=chrome-os-partner:55932 Change-Id: I88ad32091d3c37966a2ac6272f8ad95bcc8c4270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16100 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-09drivers/elog: sync events to non-volatile storage lastAaron Durbin
There were multiple paths where writes and erases of the flash were being done. Instead provide a single place for synchronizing the non-volatile storage from the mirrored event log. This synchronization point resides as the very last thing done when adding an event to the log. The shrinking check happens before committing the event to non-volatile storage so there's no need to attempt a shrink in elog_init() because any previous events committed already honored the full threshold. BUG=chrome-os-partner:55932 Change-Id: Iaec9480eb3116fdc2f823c25d028a4cfb65a6eaf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16099 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-08drivers/elog: treat offsets relative to start of mirrorAaron Durbin
Instead of treating offsets relative to after the header make the offsets relative to the in-memory mirror buffer. This simplifies the logic in that all offsets are treated the same. It also allows one to remove a global variable. BUG=chrome-os-partner:55932 Change-Id: I42491e05755d414562b02b6f9ae47f5c357d2f8a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16098 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-08drivers/elog: use region_device for mirroring into ramAaron Durbin
A region_device can be used to represent the in-memory mirror of the event log. The region_device infrastructure has builtin bounds checking so there's no need to duplicate that. In addition, it allows for removing much of the math juggling for the buffer size, etc. BUG=chrome-os-partner:55932 Change-Id: Ic7fe9466019640b449257c5905ed919ac522bb58 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16097 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: use offsets for checking cleared buffersAaron Durbin
There's only 2 users of checking if the event buffer is cleared to the EOL value. Each were passing pointers of the in-memory mirror while also doing calculations for the size to check. Since the in-memory mirror is one big buffer the only thing required to know is the offset to start checking from. The check is always done through the end of the buffer. BUG=chrome-os-partner:55932 Change-Id: Icd4a7edc74407d6578fc93e9eb533abd3aa17277 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16096 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: perform writes in terms of offsetsAaron Durbin
Instead of taking pointers and back-calculating the proper offset perform writes in terms of the offsets within the elog region in flash. BUG=chrome-os-partner:55932 Change-Id: I5fd65423f5a6e03825c788bc36417f509b58f64d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16095 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-08-08drivers/elog: remove parameters from elog_flash_erase()Aaron Durbin
The elog_flash_erase() was only called to erase the entire elog region in flash. Therefore, drop the parameters and perform the full erase. BUG=chrome-os-partner:55932 Change-Id: I6590347ae60d407bc0df141e9196eb70532f8585 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16094 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: remove unnecessary check in elog_shrink()Aaron Durbin
There was a check against the next event offset against the shrink size in elog_shrink(). However, all calls to elog_shrink() were conditionalized on the next event offset exceeding the full threshold. The shrink size is set to the minimum of the full threshold and a percentage of the elog region size. Therefore, it's impossible for the next event offset to be less than the shrink size because full threshold is always greater than or equal to the shrink size. BUG=chrome-os-partner:55932 Change-Id: Ie6ff106f1c53c15aa36a82223a235a7ac97fd8c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16093 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: use event region size when adding a clear eventAaron Durbin
For the elog shrink case we log the number of bytes shrunk from the event log. However, when clearing the log the size recorded was the entire region size including the header as well as the event region space. To be more consistent mark the clearing event with the number of bytes actually cleared out (excluding the header size). BUG=chrome-os-partner:55932 Change-Id: I7c33da97bd29a90bfe975b1c6f148f181016f13f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16092 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08drivers/elog: remove unused functionAaron Durbin
get_rom_size() is no longer used. Remove it. BUG=chrome-os-partner:55932 Change-Id: Id9fa8f67b67ee355243a5c763cfafa0ce76e9b2b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16088 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-06drivers/intel/fsp1_1: only set a base address for FSP in COREBOOT CBFSAaron Durbin
The -b FSP_LOC argument to cbfstool is only valid for the COREBOOT CBFS. Don't pass that value for all other CBFS regions. Change-Id: Ib5321e7a7dbee8d26eb558933c8ce3fea50b11fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-05drivers/intel/fsp2_0: Ensure EC is in right mode before memory initFurquan Shaikh
If EC_GOOGLE_CHROMEEC is enabled, ensure that the EC is in correct mode before running memory init. This saves additional memory training required in recovery path because of reboot later in ramstage. BUG=chrome-os-partner:54245 Change-Id: Ic71c054afdcd0001cea95563fe513783b56f3e60 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16034 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05drivers/spi: Add support for Micron N25Q128AWerner Zeh
Although we have already support for the flash chip N25Q128 there is a similar type available which has the same geometry and opcodes but unfortunately a slightly different device type ID. While the already supported N25Q128 has the ID 0xbb18 this one has the ID 0xba18. To make both types available in the flash support table, use N25Q128A as the flash name. This name can be found in the datasheet which can be found here: https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf TEST=Booted and verified that MRC cache could be written Change-Id: I02a47692efb23a9a06a289c367488abd256b8e0c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16061 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-05drivers/intel/fsp2_0: Add checklist supportLee Leahy
Add the Kconfig value to point to the checklist data files. TEST=Build and run on Galileo Gen2 Change-Id: I3737b46162214fad139382193de944ec5d175645 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16039 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03spi/tpm: read TPM version in larger chunksVadim Bendebury
The TPM version string has become much longer recently, and the TPM_FW_VER register available on VID 1ae0 devices supports reading in arbitrary size quantities. Let's read 50 bytes at a time to reduce the SPI register read wrapper overhead, and increase the length limit to 300 bytes to accommodate longer version strings. TEST=verified on the Kevin device: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/16000 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Update the debug levelsLee Leahy
Choose appropriate debug levels for the various messages in the FSP driver. Change: * BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows builder to disable FSP driver output by selecting CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 * BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the payload from successfully booting TEST=Build and run on Galileo Gen2 Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Remove fsp_print_upd_info declarationLee Leahy
Remove unused function declaration. TEST=Build and run on Galileo Gen2 Change-Id: Id971829c19c2535c975a68c44fb3697f60d0b4ad Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Disable display of FSP headerLee Leahy
Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16002 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Handle FspNotify callsLee Leahy
Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. Display the MTRRs before the first call to fsp_notify. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15855 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: FSP driver handles all FSP errorsLee Leahy
Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInitLee Leahy
Verify that FSP is properly returning: * HOB list pointer * FSP_BOOTLOADER_TOLUM_HOB * FSP_RESERVED_MEMORY_RESOURCE_HOB TEST=Build and run on Galileo Gen2 Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15850 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Add display HOB supportLee Leahy
Add support to display the HOBs returned by FSP: * Add Kconfig value to enable HOB display * Move hob_header, hob_resource and uuid_name structures into util.h * Move hob_type enum into util.h * Remove static from the debug utility functions * Add fsp_ prefix to the debug utility functions * Declare the debug utility functions in debug.h * Add HOB type name table * Add more GUID values * Add new GUID name table for additional GUIDs * Add routine to convert EDK-II GUID into a name * Add SOC specific routine to handle unknown GUID types * Add routine to convert HOB type into a name * Add SOC specific routine to handle unknown HOB types * Add routine to display the hobs TEST=Build and run on Galileo Gen2 Change-Id: I10606d752859fff0f4f08a5ac03ab129b2c96d1f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Add UPD display supportLee Leahy
Add UPD display support: * Add a Kconfig value to enable UPD value display * Add a routine to display a UPD value * Add a call before MemoryInit to display the UPD parameters * Add a routine to display the architectural parameters for MemoryInit * Add a weak routine to display the other UPD parameters for MemoryInit * Add a call before SiliconInit to display the UPD parameters * Add a weak routine to display the UPD parameters for SiliconInit TEST=Build and run on Galileo Gen2. Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15847 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Monitor FSP setting of MTRRsLee Leahy
Display the MTRR values in the following locations: * Before the call to FspMemoryInit to document coreboot settings * After the call to FspMemoryInit * Before the call to FspSiliconInit * After the call to FspSiliconInit * After the call to FspNotify * Before the call to FspNotify added in patch 15855 TEST=Build and run on Galileo Gen2 Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15849 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02drivers/fsp2_0: Increment boot count for non-S3 bootFurquan Shaikh
If ELOG_BOOT_COUNT is enabled and the boot is not s3 resume, then increment boot count. BUG=chrome-os-partner:55473 Change-Id: Ib3e77180bd640ec0424978e73034d7c99cdcba95 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15948 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-02drivers/intel/fsp2_0: Display FSP calls and statusLee Leahy
Disable the chatty FSP behavior for normal builds. Use a Kconfig value to enable the display of the FSP call entry points, the call parameters and the returned status for MemoryInit, SiliconInit and FspNotify. The debug code is placed into drivers/intel/fsp2_0/debug.c. TEST=Build and run on Galileo Gen2 Change-Id: Iacae66f72bc5b4ba1469f53fcce4669726234441 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15989 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02i2c/w83795: Fix chip type messagePatrick Georgi
(val & 4) == 1 is always false. Since val & 4 is either zero or non-zero, just drop the second test (for "== 1"). Validated against the data sheet that this is really the right register, bit and value. Change-Id: I627df9a9b4fddfff486689e405f52a3b54135eef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1241864 Reviewed-on: https://review.coreboot.org/16009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31src/drivers: Capitalize CPU, RAM and ACPIElyes HAOUAS
Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15983 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31intel/wifi: Include conditionally in the buildKyösti Mälkki
Keep this enabled by default as most x86 platforms could have PCI-e slots equipped with one of these Intel WiFi adapters. The Kconfig entries under google boards had no function previously, the variable was never referenced. Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15931 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28drivers/intel/fsp2_0: Update the copyrightsLee Leahy
Update the copyright dates in the FSP 2.0 files. Add a copyright to Kconfig. TEST=Build and run on Galileo Gen2 Change-Id: I0ad0c5650bde0e31d01a04bcc7d22a19273fe29b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28intel/fsp1_1: Add C entry support to locate FSP Temp RAM InitSubrata Banik
FSP temp ram init was getting called earlier from ROMCC bootblock. Now with C entry boot block, it is needed to locate FSP header and call FspTempRamInit. Hence add fsp 1_1 driver code to locate FSP Temp ram and execute. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built kunimitsu and ensure FSP Temp Ram Init return success Change-Id: If40b267777a8dc5c473d1115b19b98609ff3fd74 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15787 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28i2c/ww_ring: Add ww_ring files to ramstageFurquan Shaikh
These files are required by storm and gale boards for enabling elog support in ramstage. BUG=chrome-os-partner:55639 Change-Id: I2bbfee2acf2bfe2f896a8619b1276dcea1b87f16 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27drivers/intel/fsp2_0: Update MRC cache with dead version in recoveryFurquan Shaikh
If the system is in recovery, store the newly generated MRC data using a dummy version which is not legit. This ensures that on next normal boot, new MRC data will be generated and stored. BUG=chrome-os-partner:55699 Change-Id: Ib13e8c978dc1b4fc8817fab16d0e606f210f2586 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15828 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27cpu/x86: Support CPUs without rdmsr/wrmsr instructionsLee Leahy
Quark does not support the rdmsr and wrmsr instructions. In this case use a SOC specific routine to support the setting of the MTRRs. Migrate the code from FSP 1.1 to be x86 CPU common. Since all rdmsr/wrmsr accesses are being converted, fix the build failure for quark in lib/reg_script.c. Move the soc_msr_x routines and their depencies from romstage/mtrr.c to reg_access.c. TEST=Build and run on Galileo Gen2 Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15839 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26drivers/intel/fsp2_0/header_util: Convert UPD headersLee Leahy
Convert the FSP 2.0 UPD headers from typedef to struct: * FSP_UPD_HEADER * FSPM_ARCH_UPD TEST=Build and run on Galileo Gen2 Change-Id: Iab241ea07c955e95ff988a4a30103d2a112179b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15856 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-26drivers/elog: put back 4KiB limitAaron Durbin
The removal of ELOG_FLASH_BASE and ELOG_FLASH_SIZE resulted in the FMAP region for the eventlog to be honored. However, certain systems seem to have a large eventlog region that wasn't being used in practice. Because of the malloc() in the eventlog init sequence a large allocation was now being requested that can exhaust the heap. Put back the 4KiB capacity until the resource usage is fixed. BUG=chrome-os-partner:55593 Change-Id: Ib54b396b48e5be80f737fc3feb0d58348c0d2844 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15835 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-26drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-MLee Leahy
Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM. Quark executes romstage directly from the SPI flash part (in-place), but loads FSP-M into ESRAM. This split occurs because ESRAM is too small to hold everything while debugging. Platforms executing FSP-M directly from the SPI flash need to select FSP_M_XIP. TEST=Build and run on Galileo Gen2. Change-Id: Ib5313ae96dcec101510e82438b1889d315569696 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15848 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25drivers/uart: Enable debug serial output during postcarLee Leahy
Build the UART drivers for the postcar stage. TEST=Build and run on Galileo Gen2 Change-Id: I8bf51135ab7e62fa4bc3e8d45583f2feac56942f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15843 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-24drivers/elog: remove elog Kconfig variablesAaron Durbin
Now that FMAP is a first class citizen in coreboot there's no reason to have alternate locations for ELOG. If one wants eventlog support they need to specify the ELOG entry in the FMAP. The one side effect is that the code was previously limiting the size to 4KiB because the default ELOG_AREA_SIZE was 4KiB. However, that's no longer the case as the FMAP region size is honored. Change-Id: I4ce5f15032387155d2f56f0de61f2d85271ba606 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15814 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-19drivers/intel/fsp2_0: Split reset handling logicAndrey Petrov
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The rest 6 codes are platform-specific and may vary. Modify helper function so that only basic resets are handled and let SoC deal with the rest. Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPSAaron Durbin
The FSPS component can request resets. Handle those generically. BUG=chrome-os-partner:52679 Change-Id: I41c2da543420102d864e3c5e039fed13632225b4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15748 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: handle reset requests from FSPMAaron Durbin
The FSPM component can request resets. Properly handle those. BUG=chrome-os-partner:52679 Change-Id: If21245443761cb993e86c0e383c8bca87f460a85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15747 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: range check stack provided to FSPMAaron Durbin
Ensure that the stack provided to FSPM doesn't overlap the current program which is loading the FSPM component. If there is a conflict that's an error since it could cause the current program to crash. BUG=chrome-os-partner:52679 Change-Id: Ifff465266e5bb3cb3cf9b616d322a46199f802c7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15746 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: don't use saved memory data in recovery modeAaron Durbin
If the system is in recovery mode force a full retrain. BUG=chrome-os-partner:52679 Change-Id: I4e87685600880d815fe3198b820a10aa269baf37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15745 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: honor FSP revision for memory training dataAaron Durbin
Utilizing the FSP revision while saving the memory training data is important because it means when the FSP is updated the memory training is redone. The previous implementation was just using '0' as a revision. Because of that behavior a retrain would not have been done on an FSP upgrade. BUG=chrome-os-partner:52679 Change-Id: I1430bd78c770a840d2deff2476f47150c02cf27d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15744 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-19drivers/intel/fsp2_0: remove unused fsp_load_binary()Aaron Durbin
Remove the now unused fsp_load_binary() function. BUG=chrome-os-partner:52679 Change-Id: I5667eb71689a69a9e05f7be05cb0c7e7795a55d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15743 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: load and relocate FSPS in cbmemAaron Durbin
The FSPS component loading was just loading to any memory address listed in the header. That could be anywhere in the address space including ramstage itself -- let alone corrupting the OS memory on S3 resume. Remedy this by loading and relocating FSPS into cbmem. The UEFI 2.4 header files include path are selected to provide the types necessary for FSP relocation. BUG=chrome-os-partner:52679 Change-Id: Iaba103190731fc229566a3b0231cf967522040db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15742 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: John Zhao <john.zhao@intel.com>
2016-07-19drivers/intel/fsp2_0: handle XIP and non-XIP for FSPM componentAaron Durbin
The previously implementation for loading the FSPM component didn't handle platforms which expects FSPM to be XIP. For the non-XIP case, romstage's address space wasn't fully being checked for overlaps. Lastly, fixup the API as the range_entry isn't needed any longer. This API change requires a apollolake to be updated as well. BUG=chrome-os-partner:52679 Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15741 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: separate component validation from loadingAaron Durbin
The current FSP component loading mechanism doesn't handle all the requirements actually needed. Two things need to be added: 1. XIP support for MemoryInit component 2. Relocating SiliconInit component to not corrupt OS memory. In order to accommodate those requirements the validation and header initialization needs to be a separate function. Therefore, provide fsp_validate_component() to help achieve those requirements. BUG=chrome-os-partner:52679 Change-Id: I53525498b250033f3187c05db248e07b00cc934d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15740 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: implement common memory_init() tasksAaron Durbin
Instead of performing the same tasks in the chipset code move the common sequences into the FSP 2.0 driver. This handles the S3 paths as well as saving and restoring the memory data. The chipset code can always override the settings if needed. BUG=chrome-os-partner:52679 Change-Id: I098bf95139a0360f028a50aa50d16d264bede386 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15739 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: set BootLoaderTolumSize genericallyAaron Durbin
The amount of reserved memory just below the DRAM limit in 32-bit space is defined in the FSP 2.0 specification within the FSPM_ARCH_UPD structure. There's no need to make the chipset code set the same value as needed for coreboot. The chipset code can always change the value if it needs after the common setting being applied. Remove the call in soc/intel/apollolake as it's no longer needed. BUG=chrome-os-partner:52679 Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: fix hand-off-block types and sizeAaron Durbin
The gcc compiler treats sizeof(void) == 1. Therefore requesting a 1 byte reservation in cbmem and writing a pointer into the buffer returned is wrong. Fix the size of the request to be 32-bits because FSP 2.0 is in 32-bit space by definition. Also, since the access to the field happens across stage boundaries it's important to ensure fixed widths are used in case a later stage has a different pointer bit width. BUG=chrome-os-partner:52679 Change-Id: Ib4efc7d5369d44a995318aac6c4a7cfdc73e4a8c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15737 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-18elog: Use rdev_mmap to find offset of ELOGFurquan Shaikh
In case of elog not being stored in CBMEM, calculate flash offset by using rdev_mmap instead of assuming that the entire flash is mapped just below 4GiB. This allows custom mappings of flash to correctly convert the flash offset to mmap address. BUG=chrome-os-partner:54186 TEST=Verified behavior on reef. mosys able to read out the elog correctly. Change-Id: I3eacd2c9266ecc3da1bd45c86ff9d0e8153ca3f2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15722 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15drivers/intel/fsp1_1: align on using ACPI_Sx definitionsAaron Durbin
The SLEEP_STATE_x definitions in the chipsets utilizing FSP 1.1. driver have the exact same values as the ACPI_Sx definitions. The chipsets will be moved over subsequently, but updating this first allows the per-chipset patches to be isolated. BUG=chrome-os-partner:54977 Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15665 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-07-14drivers/i2c: Add new driver for RTC type PCF8523Werner Zeh
This driver enables the usage of an external RTC chip PCF8523 which is connected to the I2C bus. The I2C address of this device is fixed. One can change parameters in device tree so that the used setup can be adapted in device tree to match the configuration of the device on the mainboard. Change-Id: I2d7e161c9e12b720ec4925f1acfd1dd8ee6ee5f5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15641 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>