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2014-08-25UART 8250: Unconditionally provide register constants and use UART8250 prefix.Gabe Black
The register indexes and bitfield masks were guarded by the UART8250 config options, but it might be (is) necessary to use them in a driver that is UART8250 like without actually using the 8250 driver itself. To avoid any name collision with other drivers, also change the constant prefix from UART_ to UART8250_. Change-Id: Ie606d9e0329132961c3004688176204a829569dc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171336 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a93900be8d8a8260db49e30737608f9161fbf249) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6715 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-13Falco/Slippy: Patch to refactor haswell/gma.c and ↵Furquan Shaikh
mainboard/google/slippy/i915io.c A large portion of documented registers have been initialized using macros. Only a few undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant calls. However, some more work is required to correctly identify which calls are not required. All the io_writes are replaced by gtt_writes. Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66204 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6600 Tested-by: build bot (Jenkins)
2014-08-10drivers: Add I2C TPM driver to corebootStefan Reinauer
On ARM platforms the TPM is not attached through LPC but through I2C. This patch adds an I2C TPM driver that supports the following chips: * Infineon SLB9635 * Infineon SLB9645 In order to select the correct TPM implementation cleanly, CONFIG_TPM is moved to src/Kconfig and does the correct choice. Old-Change-Id: I2def0e0f86a869d6fcf56fc4ccab0bc935de2bf1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/167543 Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit b4049a0e96f6335a93877e1e884f9a440487c421) i2c tpm: Remove mostly useless delay code/tables. I assume from the code in the TPM driver that the TPM spec defines different types of delays and timeouts which each have a particular duration, and that the TPM can tell you how long each type is if you ask it. There was a large table, some members of a data structure, and a function or two which managed the timeouts and figured their value for different operations. The timeout values for the various "ordinals" were never set in the vendor specific data structure, however, and always defaulted to 2 minutes. Similarly the timeouts a, b, c, and d were never overridden from their defaults. This change gets rid of all the timeout management code and makes the "ordinal" timeout 2 minutes and the a, b, c, and d timeouts 2 seconds, the larger of the two default values. This is a port from depthcharge to coreboot, original change: https://chromium-review.googlesource.com/#/c/168363/ Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Old-Change-Id: I79696d6329184ca07f6a1be4f6ca85e1655a7aaf Reviewed-on: https://chromium-review.googlesource.com/168583 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> (cherry picked from commit b22395a73f361c38626911808332a3706b2334fe) TPM: Stop requesting/releasing the TPM locality. The locality is requested when the TPM is initialized and released when it's cleaned up. There's no reason to set it to the same thing again and restore it back to the same value before and after every transaction. forward ported from https://chromium-review.googlesource.com/#/c/168400 Old-Change-Id: I291d1f86f220ef0eff6809c6cb00459bf95aa5e0 Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168584 Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cc866c20c6f936f349d2f1773dd492dca9bbf0c1) Squashed three commits for the i2c tpm driver. Change-Id: Ie7a50c50fda8ee986c02de7fe27551666998229d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6519 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-07-29x230: Deploy VBTVladimir Serbinenko
Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5396 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-07-21src/drivers: Remove a trailing whitespaceElyes HAOUAS
Change-Id: If357da5d84a255e0bdf8784d559ee0941045bbd6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6309 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-19lenovo/x60: Support digitizer on X60t and X201t.Vladimir Serbinenko
Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-07-17drivers/spi: Sanitize headers from preprocessor abuseEdward O'Callaghan
Continuing on from the rational given in: a173a62 Remove guarding #includes by CONFIG_FOO combinations Change-Id: I35c636ee7c0b106323b3e4b90629f7262750f8bd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17drivers,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I2d1f6a571166924c929452fd0f70192670904220 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6285 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-15drivers/intel/fsp/fsp_util: 'long unsigned int' is 'unsigned long'Edward O'Callaghan
This is a bit of strange way to write 'unsigned long', fix that. Change-Id: I17caf971dac840e0f35f883dacfbd5c94d8c03d6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-14SPI: Split writes using spi_crop_chunk()Kyösti Mälkki
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14SPI flash: Fix alignment checks in Page Program commandsKyösti Mälkki
There are two separate restrictions to take into account: Page Program command must not cross address boundaries defined by the flash part's page size. Total number of bytes for any command sent to flash part is restricted by the SPI controller capabilities. Consider CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4. This write would be split at offset 64 for no reason. Consider CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4. This write would not be split at page boundary as required. We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT is a misnomer for the maximum payload length supported by the SPI controller and is removed in a followup. Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6162 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-08drivers: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ie80c87c614a536cc6b0bdbf196c280b64547d3b7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6203 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi flash: Organise options listKyösti Mälkki
Change-Id: I21e4e2384d9b8bbd34f652e99af11dee993fb41c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6173 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()Dave Frodin
At the end of some SPI operations the SPI device needs to be polled to determine if it is done with the operation. For SPI data writes the predicted time of that operation could be less than 10us. The current per loop delay of 500us is adding too much delay. This change replaces the delay(x) in the do-while loop with a timer so that the actual timeout value won't be lengthened by the delay of reading the SPI device. Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5973 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-01stdlib: Drop duplicates of min() and max()Kyösti Mälkki
Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6161 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-29drivers/pc80/mc146818rtc_early.c: Silence unused func complaintsEdward O'Callaghan
Clang complains these functions are unused since they find their way into the bootblock of ROMCC boards by #including the .c file. These static inlines should probably be moved into a header in reality. Change-Id: I9d82a6befb0ac99afab6265f9d3649e419f2887d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6122 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-25drivers/intel/gma: Uninitialized var before if conditionEdward O'Callaghan
The variable 'wait' is used uninitialized whenever 'if' condition is false if (val & DDI_BUF_CTL_ENABLE) { ^~~~~~~~~~~~~~~~~~~~~~~~ Leading to an uninitialized use occurs here: if (wait) ^~~~ Change-Id: I7d96bf1e33b9c4312d4a0ba8276e83d17d6cd070 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6052 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-25drivers/elog: Unmangle header include out of pre-proc condEdward O'Callaghan
Change-Id: Ic4905d8a6908a30602382f5846f1dc2c0dbe2431 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6068 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21PC80 RTC: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Idc4c47f3802019c2853ec71f8e9c057c3ab8d3ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6074 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21PS2 keyboard: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6073 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21Misc: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6072 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-20drivers/intel/gma: Equality comparison with extraneous parenthesesEdward O'Callaghan
Spotted by Clang. Change-Id: I3e612c0fa050a09fa7e5b1cb643935b84eb2b957 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6053 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-11PIC i8259: Move #defines and functions to i8259.hMike Loptien
The PIC i8259.c file has a lot of #defines and function definitions in it. I am moving these to the i8259.h file and also adding a few functions to update the PIC IRQ mask register. The PIC default configuration has all of its interrupts masked off except for IRQ2. IRQ2 is where the Slave PIC is cascaded from the Master PIC. Change-Id: I78d505358c29fadbc184137a09120863ea1d5c13 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/5950 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-01i915_reg: Declare LVDS register values.Vladimir Serbinenko
Change-Id: If8b3578c4fa31bf9f09c0053a5cac7ebc993b634 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5319 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-29drivers/intel/fsp: update enable_mrc_cache with fast bootMartin Roth
When going from a configuration with fast boot disabled to one with it enabled, ENABLE_MRC_CACHE was not being enabled properly. This forces it on with ENABLE_FSP_FAST_BOOT. Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5794 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-29add rtc_init() to romstageMartin Roth
The FSP clears the bit that tells us whether or not the RTC has lost power when it sets up memory. Because of this, we need to initialize the RTC in romstage instead of ramstage. Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5735 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-25lenovo: Add lenovo_mainboard_partnumber.Vladimir Serbinenko
Change-Id: Ie10dcb742fe0884dd94ff5960e2e4b116f633243 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5246 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-23drivers/pc80/Kconfig: Revert PS/2 initialization defaultsPatrick Georgi
Remove the inconsistent behaviour based on unrelated configuration: PS/2 init is now always enabled. This can change once we find a better approach. Change-Id: Ia8d55032f0e5eca0bf82d77df7dab95bcb2b353a Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5634 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2014-05-20drivers: Drop GbE stub driversEdward O'Callaghan
These NIC stub drivers were to initialize the Gigabit Ethernet adapters just enough to keep coreboot from trying to execute an option ROM. However this is no longer required as non-VGA option roms are not ran; See: b32816e Remove PCI_ROM_RUN option Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5777 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-18drivers/spi/sst.c: Remove unused func to_sst_spi_flash()Edward O'Callaghan
Trips up clang builds with a warn treated as error. Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
There are a couple of places where CPPFLAGS are pasted into CFLAGS, eliminate them. Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5765 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
Rename INCLUDES to CPPFLAGS since the latter is more commonly used for preprocessor options. Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5764 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-15drivers/pc80/Kconfig: simplify PS/2 selection rulesPatrick Georgi
There's no need to state the dependency twice. Change-Id: Ia241d441211c6f476d0a6ed7589b038f7a220265 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5633 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-05-13src/drivers/pc80: Remove empty struct keyboardEdward O'Callaghan
This is a empty struct that has propagated through the superio's & ec's but really does nothing. Time to get rid of it before it adds yet more cruft. However, since this touches many superio's at once we do this in stages by first changing the function type to be a pure procedure. Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5617 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-09Intel FSP: add a shared set of functions for the FSPMartin Roth
- Move the non chipset-specific fsp pieces out of the chipset into a shared area. This is used by northbridge / southbrige / SOC code. It pulls in pieces from Kconfig, Makefile and FSP specific code. - Enabled in the CPU code with a Kconfig "select PLATFORM_USES_FSP" Change-Id: I7ffa934c1df09b71d48a876a56e3b888685870b8 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5635 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-02drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payloadPaul Menzel
If the user selects GRUB 2 as the payload in Kconfig, coreboot does not need to initialize the PS/2 keyboard as GRUB 2 is going to do it. Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is chosen as payloadPaul Menzel
As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is able to initialize the PS/2 keyboard itself, so it is not necessary to let coreboot do it. SeaBIOS is also able to do it faster as discussed in a thread on the coreboot mailing list from October 2010 [1]. In that thread it was also proposed to not let coreboot initialize the PS/2 coreboot when SeaBIOS is used as a payload. [1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310 subject: [coreboot] coreboot+seabios timings Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02drivers/pc80/Kconfig: Mention that GRUB 2 is able to init PS/2 keyboardPaul Menzel
Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-30console: Drop EARLY_CONSOLE optionKyösti Mälkki
We have means to easily disable a specific console in romstage if necessary, so this global option makes little sense. The option was initially introduced as a work-around for build issues around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs. Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5607 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30uart: Support multiple portsKyösti Mälkki
The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5342 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-29SPI: Use common dependency in KconfigKyösti Mälkki
Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5605 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-26uart8250io: Fix build with DEBUG_SMIKyösti Mälkki
Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5574 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-26Get rid of HAVE_INIT_TIMER config optionFurquan Shaikh
There is redundancy in terms of use of init_timer. We have a Kconfig option to decide whether a board has init_timer as well as we use a stub for init_timer in places where we do not have any init_timer defined. Thus, remove the Kconfig option. Henceforth, all boards that do not have init_timer functionality can include a stub_timer if required. Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-22usbdebug: Add BeagleBone BlackKyösti Mälkki
Avoid some confusion as the selection of "BeagleBone" is not compatible with the product "BeagleBone Black". Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-22Drop drivers/generic/debugKyösti Mälkki
Not very popular nor useful nowadays. Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4554 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-18console: Drop driver list in ramstageKyösti Mälkki
This framework was only available in ramstage. So we had to define console output functions separately for bootblock, romstage and SMM. Follow-up patches will re-enable all the consoles removed here, in a more flexible fashion, and with less lines-of-code and copy-paste. Also the driver list is not in a well-defined order and some of the loops could exit without visiting all drivers. NOTE: This build has no console in ramstage. Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5337 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09OxPCIe uart: Move under drivers/uartKyösti Mälkki
This driver is only a thin shell for uart8250mem and we could extend it with further compatible PCI IDs from other vendors/brands. Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09OxPCIe uart: Split PCI bridge controlKyösti Mälkki
None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09uart: Redefine Kconfig optionsKyösti Mälkki
Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09console uart: Fill coreboot table entriesKyösti Mälkki
Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5310 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09uart: Prepare to support multiple base addressesKyösti Mälkki
Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5309 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-12drivers/spi: Add support for adesto SPI flash partsChris Douglass
Adds support for the following Adesto Technologies SPI Flash parts. AT25DF081 AT25DF321 AT25DF641 It has been tested on an Orion VPX7654 board populated with an AT25DF321A part. The "08" and "64" densities have not been tested. These parts are the successors of the Atmel AT26DF line that was spun out or purchased by Adesto. In this patch, adesto.c is identical to winbond.c with part entries for the Adesto parts. The datasheet for the AT25DF parts includes a "100MHz" programming command in addition to the "85MHz" command that is currently used but this patch does not add support for that enhanced programming mode. Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5225 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-09intel/gma: Remove MCH register declarations.Vladimir Serbinenko
i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror. It's not currently used and we don't want any MCH registers in GFX. Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5318 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04console: Use single driver entry for UARTsKyösti Mälkki
UARTs now have unified prototypes and can use a single entry in the list of drivers for ramstage. Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5308 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04usbdebug: Move Kconfig under drivers/usbKyösti Mälkki
This menu may become a bit more complicated with addition of new USB hardware so move it out of console/. Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5307 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04SMM: Only have console with DEBUG_SMIKyösti Mälkki
Existing code compiled serial communication and printk() for SMM even when DEBUG_SMI was not selected. Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5142 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-04uart8250: Move under drivers/uartKyösti Mälkki
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5236 Tested-by: build bot (Jenkins)
2014-03-04uart8250mem: Unify calls with generic UARTKyösti Mälkki
NOTE: UART base for SMM continues to be broken, as it does not use the address resource allocator has assigned. Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04console: Fix includesKyösti Mälkki
Do not pull in console hw-specific prototypes everywhere with console.h as those are not needed for higher levels. Move prototypes for UARTs next to other consoles. Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5232 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04pl011 UART: Move under drivers/uartKyösti Mälkki
Currently this is only a minimal stub to get console on qemu-armv7. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5162 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04option: Add arch-agnostic get_option()Kyösti Mälkki
We should not have pc80/ includes in console/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5157 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04uart8250: Fix and unify baudrate divisor calculationKyösti Mälkki
Divisor is a function of requested baudrate, platform-specific reference clock and amount of oversampling done on the UART reference. Calculate this parameter with divisor rounded to nearest integer. When building without option_table or when there is no entry for baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate. For OxPCIe use of 4 MHz for reference was arbitrary giving correct divisor for 115200 but somewhat inaccurate for lower baudrates. Actual hardware is 62500000 with 16 times oversampling. FIXME: Field for baudrate in lb_tables is still incorrect. Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5229 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04nehalem: Replace video init.Vladimir Serbinenko
Old video init just replayed the sequence. This one actually computes the values. Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5270 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04drivers/intel/gma: Add EDID retrieving functions.Vladimir Serbinenko
Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5278 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-03-03qemu: Support textmode gfx init.Vladimir Serbinenko
Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5283 Tested-by: build bot (Jenkins) Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-28drivers/spi: Sort SPI flash filesChris Douglass
Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967 Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com> Reviewed-on: http://review.coreboot.org/5260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-20usbdebug: Unify console APIKyösti Mälkki
Struct dbgp_pipe would not be suitable for use with xHCI. Just use an index, it is easy to setup in Kconfig if our future debug setup has separate pipes for console output and debugging/traceings. Change-Id: Icbbd28f03113b208016f80217ab801d598d443a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5227 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-17console: Add drivers/uartKyösti Mälkki
Also move UART related Kconfig options from top-level file. Change-Id: I4e407977cff6f6506f991600c98d6d264676d3f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5230 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-17src/drivers/spi: introduce AMIC supportIdwer Vollering
Add support for the AMIC A25L032 flash chip. Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/5252 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-16usbdebug: Remove EHCI_DEBUG_OFFSETKyösti Mälkki
Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-12usbdebug: Split to USB host/deviceKyösti Mälkki
Top-level interface to console over USB mut not require low-level details of ECHI debug port internals. Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5197 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10usbdebug: Split PCI EHCI partKyösti Mälkki
There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10usbdebug: Fix data toggle on receiveKyösti Mälkki
USB device end toggles data PID when we ACK'd the zero-length data packet. As USB host we need to toggle data PID too or the next data received would get discarded. Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4775 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10usbdebug: Improve receive speedKyösti Mälkki
Read from USB endpoint_in 8 bytes at a time, the maximum what EHCI debug port capability has to offer. Change-Id: I3d012d758a24b24f894e587b301f620933331407 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06QEMU debugcon: Move under drivers/emulation/qemuKyösti Mälkki
Also prepare this console for use in romstage. Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5136 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2014-02-06ne2k: Move under drivers/netKyösti Mälkki
Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-06spkmodem: Move under drivers/pc80Kyösti Mälkki
Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5134 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-06usbdebug: Move under drivers/usbKyösti Mälkki
Also relocate and split header files, there is some interest for EHCI debug support without PCI. Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-02drivers/i2c/at24rf08c/lenovo_serials.c: Remove trailing whitespacePaul Menzel
The trailing whitespace breaks the Git commit hook `util/lint/lint-stable-003-wihitespace`. So remove it. Change-Id: I70e4ac71529884a9a4fabf2aa9a4ea6e0323b9d4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5092 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-01lenovo: Handle EEPROM/RFID chip.Vladimir Serbinenko
EEPROM/RFID chip present in thinkpad should be locked in a way to avoid any potential RFID access. Read serial number, UUID and P/N from EEPROM. This info is stored on AT24RF08 chip acessible through SMBUS. Change-Id: Ia3e766d90a094f63c8c854cd37e165221ccd8acd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4774 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-01-28spi: Add support for Winbod W25Q64DWAaron Durbin
The W25Q64DW spi part is programatically equivalent to the other W25Q64 parts except it operates at 1.8V. Just add a new entry with the appropriate ID. BUG=chrome-os-partner:22292 BRANCH=None TEST=SPI controller can program the part. Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170011 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-26pc80/keyboard: Ignore interface test failure.Vladimir Serbinenko
On Asus A8N-E this test fails but if failure is ignored keyboard works. Change-Id: Ifeeff2f41537b35bc90a679f956fea830b94292c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4816 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-23SPI: Add API for programmer-specific flashing.Vladimir Serbinenko
Change-Id: I7a2f5b9ae74458b5ed6271b1c27842c61546dcd2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4712 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23keyboard.c: fix coding style with indentAndrew Wu
Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3986 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13xpowers/axp209: Add helper to set voltages from devicetree configAlexandru Gagniuc
Change-Id: I3ffe225b78f88c3c2d3a15292c43009e69413afb Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4638 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13xpowers/axp209: Allow voltages to be sepecified in devicetree.cbAlexandru Gagniuc
This allows system voltages to be specified uniformly, rather than hardcoding them for each board. This will be used by cubieboard in an upcoming patch. Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4637 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13drivers: Add support for X-Powers AXP209 PMUAlexandru Gagniuc
Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4591 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12drivers/spi/eon: Add EN25Q64Vladimir Serbinenko
chip found in X230 if not using hardware sequencing. Change-Id: I6ded10d35bfdbbe3d54c4170dd7846c7833f5ff7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4616 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_contentVladimir Serbinenko
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4659 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-21max77802: update headerDavid Hendricks
This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6 Reviewed-on: https://gerrit.chromium.org/gerrit/64303 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4426 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Refactor code containing aux callsFurquan Shaikh
Moved a lot of code from i915io.c to intel_dp.c with specific function calls Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc Reviewed-on: https://gerrit.chromium.org/gerrit/63950 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4429 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flagsFurquan Shaikh
Depending upon the values decoded from edid, the function decides the appropriate bits to be set in flags parameter (Important for fastboot to work correctly in kernel) Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856 Reviewed-on: https://gerrit.chromium.org/gerrit/64265 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4423 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add cpu transcoder attribute to intel dpFurquan Shaikh
Also, used this attribute in the calculation of htotal and other registers Added intel_dp_* functions for m,n registers and dimension register calculations Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a Reviewed-on: https://gerrit.chromium.org/gerrit/64001 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4422 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Calculate transcoder flags based on pipe configFurquan Shaikh
Works fine with all three panels with the change of 6 bits per color. Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e Reviewed-on: https://gerrit.chromium.org/gerrit/63762 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21tpm: provide explicit tpm register accessAaron Durbin
An issue was observed using a specific vendor's TPM in that it chokes on access to registers that are not explicitly defined in the PC client specification. The previous driver used generic access functions for reading and writing registers. However, issues come to play when reading from the status register. It read it as a 32-bit value, but that read address 0x1b which is not defined in the spec. Instead of using generic access functions for the tpm registers provide explicit ones. To that end provide more high level wrapper functions to perform the semantic access required. Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4388 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21rtd2132: implement full configurationAaron Durbin
It has been disseminated that the RTD2132 chip needs to be fully programmed for settings to take affect. Most of the settings are note documented very well and present themselves as magic values. Also, the wait time for starting the sequence needs to be bumped from 2ms to 60ms. Lastly, expose all the known settings through devicetree. Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65857 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Remove PS/2 keyboard initialization on resume from S3Martin Roth
When we go through the resume path, there shouldn't ever be a need to initialize the PS/2 keyboard. The OS is going to reinitialize it anyway, and it just slows the resume. Verified Code flow in normal boot/S3 resume with print statements. Verified Keyboard was correctly disabled and flushed by booting to recovery mode screen while pressing keys on the integrated keyboard. Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63648 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4396 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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