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Add DPTS (device prepare to sleep) method that is to be called in
mainboard's \_SB.MPTS, which is called in _PTS.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie308f74940a33711a398bc11d0550cb06b55cdcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Fix always-true conditions to properly test whether a bit is set.
Change-Id: I54b5dbfdbb99a47ef0dfdb9497179f516d6e1f23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
PXSX._RST is invoked on driver removal.
build dependency:
soc/intel/common/block/pcie/rtd3
This driver will use the rtd3 methods for the same parent in the device
tree. The rtd3 chip needs to be added on the same root port in the
devicetree separately.
Test:
Add chip entry to the corresponding root port and check PXSX Device
is generated in ssdt.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61354
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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