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On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
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Not sure what this is about.
Required for BeagleBone (not Black) with HUB in the middle, also
old FX2 senses extra reset if we do this.
Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3868
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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According to EHCI specification, host controller software stops
the USB Reset condition by writing PORT_RESET=0. Software then
poll-waits this bit until controller hardware has completed USB
Reset sequence and read returns with PORT_RESET==0.
Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3863
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Organized such that it is easy to support devices that do not
export special Debug Descriptor. Some of these can still work
in a fixed configuration and/or require additional initialisation
for UART clocks etc.
Change-Id: Id07fd6b69007332d67d9e9a456f58fdbca1999cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7209
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Add new file for device-specific initialisation transactions.
Change-Id: I339df400a41675f178c7af613f03b2b44c826189
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7208
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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We only reference with ehci_caps and ehci_regs during initialisation,
no need to carry those around.
When EHCI BAR is relocated during PCI allocation, record the changed
address even if usbdebug is not enabled. Use the DBGP_EP_VALID flags
to determine if endpoints have been configured or not.
Change-Id: Idfd52edf7c2fc25b1b225985462ac488264e4c6d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7207
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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On entry to ramstage CBMEM is looked for a copy of an already initialized
EHCI debug dongle state. If a copy is found, it contained the state before
CAR migration and the USB protocol data toggle can be out of sync. It's an
even/odd kind of a parity check, so roughly every other build would
show the problem as invalid first line: 'ug found in CBMEM.'
After CAR migration, re-direct the state changes to correct CBMEM table.
Change-Id: I7c54e76ce29af5c8ee5e9ce6fd3dc6bdf700dcf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7206
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
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Change-Id: Ie80c87c614a536cc6b0bdbf196c280b64547d3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6203
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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We have means to easily disable a specific console in romstage if
necessary, so this global option makes little sense.
The option was initially introduced as a work-around for build issues
around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs.
Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5607
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Avoid some confusion as the selection of "BeagleBone" is not compatible
with the product "BeagleBone Black".
Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4289
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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This menu may become a bit more complicated with addition of
new USB hardware so move it out of console/.
Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5307
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Struct dbgp_pipe would not be suitable for use with xHCI.
Just use an index, it is easy to setup in Kconfig if our
future debug setup has separate pipes for console
output and debugging/traceings.
Change-Id: Icbbd28f03113b208016f80217ab801d598d443a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Read this variable from PCI configuration capabilities list instead.
Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Top-level interface to console over USB mut not require low-level
details of ECHI debug port internals.
Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5197
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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There are EHCI compatible host controllers on ARM without PCI bus
architecture. Currently we have not come across one with the debug
capability though.
Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5175
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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USB device end toggles data PID when we ACK'd the zero-length data
packet. As USB host we need to toggle data PID too or the next data
received would get discarded.
Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4775
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Read from USB endpoint_in 8 bytes at a time, the maximum what
EHCI debug port capability has to offer.
Change-Id: I3d012d758a24b24f894e587b301f620933331407
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Also relocate and split header files, there is some interest
for EHCI debug support without PCI.
Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5129
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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