coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-10-13	drivers: snsn65dsi86: Fix link rate parsing	Julius Werner
	DP link rates are reported in an array of LE16 values. The current code tries to parse them as 8-bit which doesn't get very far, causing us to always drop into the fallback path. This patch should fix the issue (+minor whitespace cleanup). BUG=b:170630766 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2020-10-09	sc7180: Remove the delay to force hpd detection and always disable HPD	Vinod Polimera
	HPD on this bridge chip is a bit useless. This is an eDP bridge so the HPD is an internal signal that's only there to signal that the panel is done powering up. But the bridge chip debounces this signal by between 100 ms and 400 ms (depending on process, voltage, and temperate). One particular panel asserted HPD 84 ms after it was powered on meaning that we saw HPD 284 ms after power on. Assume that the panel driver will have the hardcoded delay in its prepare and always disable HPD. Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-01	drivers: sn65dsi86: Retry link training up to 10 times	Julius Werner
	The kernel guys have found that automatic link training from this bridge can occasionally fail and needs to be retried. They have added up to 10 retries just to be sure, so let's do the same in coreboot. BUG=b:169535092 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45882 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10	sc7180: Add support for sn65dsi86 bridge	Vinod Polimera
	Add sn65dsi86 bridge driver to enable the eDP bridge. Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf Changes in V1: - fix the dp lanes using mask - separate out the refclk and hpd config to init function Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>