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path: root/src/drivers/spi/winbond.c
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2016-05-09spi: Add support for Winbond W25Q256Varadarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ifde289ec004f5d54d5df32011c87e49470e2bb5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 613b5ae45f7b8325863d8be492a451e6d076e293 Original-Change-Id: I93386e058a60b5c9b61d89607cf8c6e0de6a21ca Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/334522 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17spi: Add function to read flash status registerDuncan Laurie
Add a function that allows reading of the status register from the SPI chip. This can be used to determine whether write protection is enabled on the chip. BUG=chrome-os-partner:35209 BRANCH=haswell TEST=build and boot on peppy Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240702 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c58f17689162b291a7cdb57649a237de21b73545) Change-Id: Ib7fead2cc4ea4339ece322dd18403362c9c79c7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbdf0d72892eef4a742a418a347ecf650c01ea5 Original-Change-Id: I2541b22c51e43f7b7542ee0f48618cf411976a98 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241128 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17drivers/spi: Pass flash parameters from coreboot to payloadDan Ehrenberg
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-20spi: do not use malloc in Winbond driverVadim Bendebury
When the driver is included in bootblock, malloc() is not available. Come to think of it, it is perfectly fine to use a statically allocated structure for the SPI device descriptor - coreboot is unlikely to require concurrent support of multiple SPI devices of the same kind. BRANCH=none BUG=chrome-os-partner:31438 TEST=bootblock on the FPGA board recognizes the installed Winbond device: coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting... SF: Detected W25Q16 with page size 1000, total 200000 Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228959 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8771 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-17spi_flash: Move (de-)assertion of /CS to single locationDavid Hendricks
This consolidates all calls to spi_claim_bus() and spi_release_bus() to a single location where spi_xfer() is called. This avoids confusing (and potentially redundant) calls that were being done throughout the generic spi_flash.c functions and chip-specific functions. I don't think the current approach could even work since many chip drivers assert /CS once and then issue multiple commands such as page program followed by reading the status register. I suspect the reason we didn't notice it on x86 is because the ICH/PCH handled each individual command correctly (spi_claim_bus() and spi_release_bus() are noops) in spite of the broken code. BUG=none BRANCH=none TEST=tested on nyan and link Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I3257e2f6a2820834f4c9018069f90fcf2bab05f6 Original-Reviewed-on: https://chromium-review.googlesource.com/194510 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit d3394d34fb49e9e252f67371674d5b3aa220bc9e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ieb62309b18090d8f974f91a6e448af3d65dd3d1d Reviewed-on: http://review.coreboot.org/7829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-16spi: Add support for Winbond W25Q32DWDavid Hendricks
Similar to the W25Q64DW, the W25Q32DW has basically the same attributes as the earlier W25Q32 parts but with a different value in the MSB of the ID. BUG=none BRANCH=none TEST=tested on nyan, now SPI flash commands actually work. Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I697768a443c98515d893f9cf8f8b4258ae0f159d Original-Reviewed-on: https://chromium-review.googlesource.com/191205 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 35f03f4f4f21c470d172ce7cce257517b959346d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I73606737835e4f8ea00d2c331ca37957e4abd953 Reviewed-on: http://review.coreboot.org/7755 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-09-29spi: Add support for Winbond W25Q128FWMohan D'Costa
The W25Q128FW spi part is programatically equivalent to the other W25Q128 parts except it operates at 1.8V. Just add a new entry with the appropriate ID. Tested on a modified MinnowMax Board. Change-Id: Id6a426418a7f785a9d959b02a9e3d2ffc421804f Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6971 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-07-17drivers/spi: Sanitize headers from preprocessor abuseEdward O'Callaghan
Continuing on from the rational given in: a173a62 Remove guarding #includes by CONFIG_FOO combinations Change-Id: I35c636ee7c0b106323b3e4b90629f7262750f8bd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6114 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-14SPI: Split writes using spi_crop_chunk()Kyösti Mälkki
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14SPI flash: Fix alignment checks in Page Program commandsKyösti Mälkki
There are two separate restrictions to take into account: Page Program command must not cross address boundaries defined by the flash part's page size. Total number of bytes for any command sent to flash part is restricted by the SPI controller capabilities. Consider CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4. This write would be split at offset 64 for no reason. Consider CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4. This write would not be split at page boundary as required. We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT is a misnomer for the maximum payload length supported by the SPI controller and is removed in a followup. Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6162 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-01-28spi: Add support for Winbod W25Q64DWAaron Durbin
The W25Q64DW spi part is programatically equivalent to the other W25Q64 parts except it operates at 1.8V. Just add a new entry with the appropriate ID. BUG=chrome-os-partner:22292 BRANCH=None TEST=SPI controller can program the part. Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170011 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5077 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2012-12-12Claim the SPI bus before writes if the IMC ROM is presentMartin Roth
The SB800 and Hudson now support adding the IMC ROM which runs from the same chip as coreboot. When the IMC is running, write or erase commands sent to the spi bus will fail, and the IMC will die. To fix this, we send a request to the IMC to stop fetching from the SPI rom while we write to it. This process (in one form or another) is required for writes to the SPI bus while the IMC is running. Because the IMC can take up to 500ms to respond every time we claim the bus, this patch tries to keep the number of times we need to do that to a minimum. We only need to claim the bus on writes, and using a counter for the semaphore allows us to call in once to claim the bus at the beginning of a number of transactions and it will stay claimed until we release it at the end of the transactions. Claim() - takes up to 500ms hit claim() - no delay erase() release() claim() - no delay write() release() Release() Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed Signed-off-by: Martin Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1976 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-08Limit SPI device debug prints with CONFIG_DEBUG_SPI_FLASHMarc Jones
Fix debug printks which were not using CONFIG_DEBUG_SPI_FLASH, which would cause long delays durring boot when SPI devices were written. Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1965 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12SPI: Fix and enable Fast Read supportDuncan Laurie
- Fix handling of 5-byte Fast Read command in the ICH SPI driver. This fix is ported from the U-boot driver. - Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by defining a name for the bool in Kconfig and removing the forced select in southbridge config - Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers to use #if instead of #ifdef - Relocate flash functions in SMM so they are usable. This really only needs to happen for read function pointer since it uses a global function rather than a static one from the chip, but it is good to ensure the rest are set up correctly as well. Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1775 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-26Reduce default verbosity of SPI flash driversStefan Reinauer
Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1045 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-26Fix printk types in SPI flash driversStefan Reinauer
- use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1041 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10Add SPI flash driverStefan Reinauer
This driver is taken from u-boot and adapted to match coreboot. It still contains some hacks and is ICH specific at places. Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/997 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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