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Once coreboot is ready and payload has been loaded a bit inside the NC
FPGA needs to be set to notify this event. As there are NC FPGAs with
different PCI device IDs save the BAR0 address in a global variable once
the driver evaluates this address. It can then be used to access the
register from the boot state machine callback without the need of searching
for all possible PCI devices again.
As this driver is only used at ramstage there is no need of using
CAR_GLOBAL for the global variable. Use a Kconfig switch to make this
feature selectable from mainboard as not every mainboard may have a FPGA
with that capability.
Change-Id: I9cd09e7051edde30d144a7e020b84bb549e9e8b9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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For general use of this driver it is necessary to move some parameters
from init_fan_ctrl() to init_temp_mon(). This shift does not lead to any
functional change.
Change-Id: I6b8f770c768f3dacf96087eb0194cc99f0d11e17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The functionality of the FAN controller is extended to provide a
lowest startup speed of the FAN. Add the parameter "fanmin" to
the fan_ctrl_t structure and initialize the value.
Change-Id: Ib2e093ed6f5fc29bbea879779eb4777eb371b937
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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As "var" is not a pointer but a variable there is no need to cast it to
a pointer before using the value.
Change-Id: I7f8e3ceadaa4301c50c5f5480cccab2be904aa9a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The macro FPGA_SET_PARAM was introduced to make the setting of different
FPGA registers with the appropriate values from hwinfo more
transparent. The hwilib takes care about the size of the provided buffer
where the requested value should be stored in. The fields in hwinfo have
not always the same size as the matching registers in the FPGA. So to
avoid errors resulting in a too small buffer when calling hwilib_get_field()
the buffer is now fixed to 32 bit and will be casted to the destination
type when the value is written into the FPGA register.
Changing the field size in hwilib would be the wrong way as the defined
lengths are specified this way to be expandable in the future.
In addition the number of maximum supported temperature sensors is
increased to 8 as the FPGA now supports more.
Change-Id: I0c697106783158420708a973c3cff2be90fa4fce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The flag FF_FreezeDis marks if this feature is disabled. For a better
readability rename freeze_mode to freeze_disable and invert the meaning
of this information.
Change-Id: I648b2392d2c8046965479511fde485a9cb934378
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The siemens/mc_apl1 mainboard needs more functionality provided by
Siemens NC FPGA. The additional functionality contains backlight
brightness/PWM control and Dsave time for board reset.
Change-Id: I6b65b01f0d67afe598b7c005868f71b00dec56fd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add driver code to initialize Siemens NC FPGA as PCI device.
Beside some glue logic it contains a FAN controller and
temperature monitor.
Change-Id: I2cb722a60081028ee5a8251f51125f12ed38d824
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15543
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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