coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2012-11-27	Get rid of drivers class	Patrick Georgi
	The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24	Add BAR address debug information to Oxford PCIe serial driver	Marc Jones
	The Oxford PCIE Serial card has a hardcoded address at setup, which may be moved during PCI Init. The driver re-initializes after PCI init. Add a debug print for the new BAR address. Initializing Oxford OXPCIe952 OXPCIe952: Class=70002 Revision ID=0 OXPCIe952: 2 UARTs detected. OXPCIe952: Uart Bar: 0xe0800000 Change-Id: I1858d3eba09749cba3c3869060d00e621dca112a Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1327 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-29	Detect whether the OXPCIE card is really present while in the ROM stage.	Gabe Black
	Use an int in CAR global data to store whether or not the OXPCIE serial card is actually there. Also, time out if the card doesn't show up quickly enough, don't continue initialization if it's not there, and don't make the initialization routine default to a card if none is found. Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/728 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09	OXPCIe: Reinitialize UART after pci_dev_set_resources()	Stefan Reinauer
	... and only pull in early init code if the OXPCIe is used for console. Change-Id: I01feca3b9e8376a75c17554ba1bd200d523dff8d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/692 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-09	Add support for the Startech PEX1XS1PMINI	Stefan Reinauer
	It has a smaller footprint than the already supported MPEX2S952 Change-Id: Ie36b67f9628882d516ca34ff164f0e8918955a5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/690 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2011-11-01	remove trailing whitespace	Stefan Reinauer
	Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-04-26	Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as an	Stefan Reinauer
	example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1