Age | Commit message (Collapse) | Author |
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Rather than force the user to create the RW_MRC_CACHE FMAP region,
simply select CACHE_MRC_SETTINGS so it's done automatically for them.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Iaa1da6015c1bfafe8ea81ca34ef8851f0c689487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Coverity detects pointer fih as FORWARD_NULL. Add sanity check
for fih to prevent NULL pointer dereference.
BUG=CID 1401717
TEST=Built and boot up to kernel.
Change-Id: Ia6853e5302c87d9ffe52b942f067be56f6e77406
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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Change-Id: Iab8d20a385bde31b29fa7766a87753fcc2d759b8
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The code in cpu/intel/car/romstage.c Does most of the things like
setting up timestamps, stack guards, entering postcar.
A functional difference is that the FSP header is searched for twice
instead of passed from the CAR entry to the C code. When using
C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special
linker symbol kept across multiple stages is needed, which is likely
not worth the speedup).
Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Instead of dereferencing a null pointer, print a nice message and exit
cleanly if the FSP isn't found in the CBFS.
Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401467, 1401717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I3395715f9e2b03175089186ab2e57d9e508fc87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Setting up the console and entering postcar can be done in a common
place.
Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This gets rid of the boilerplate back and forward calls between the
SOC/FSP-driver code and mainboard code.
Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: Ic50b16916261abb8c63b8fe571819af5c830ff8d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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drivers/intel/fsp1_0/Kconfig is a better location than
cpu/x86/Kconfig.
Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This function is unused since POSTCAR_STAGE is used.
(be291e8 soc/intel/fsp1.1: Implement postcar stage)
Change-Id: Ia9ff5236295a0e1c4f7634d27cf0ae1d87029678
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This list is incorrect and not up to date. The FSP1.1 romstage
bootflow is unnecessarily clumsy and instead of trying to update this
comment effort is better spend making the bootflow more streamlined.
Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This moves FSP1.1 to use postcar stage to tear down CAR.
On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found
during the postcar stage so there is no need to push to save it
in CAR global variables.
On FSP1.1 platforms with an open source CAR implementation (Skylake,
even though it still runs the FSP-T), the
soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR.
This also uses common functions to set up the MTRR to use after
CAR is torn down.
Test: build/boot on google/celes (BSW) and google/chell (SKL)
Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Probably a copy/paste issue.
Change-Id: I0334bc1f5d145df5af0a307cf8e7c23cc0605f76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Previously cpu_index() always succeeded, but since commit 095c931
(src/arch/x86: Use core apic id to get cpu_index()) it is now possible
for it to indicate an error by returning -1. This commit adds error
handling for all calls to cpu_index(), and restores several checks that
were removed in commit 7c712bb (Fix code that would trip -Wtype-limits)
but are now needed.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5436eed4cb5675f916924eb9670db04592a8b927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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TEST=Able to build coreboot for CML.
Change-Id: I8a6a97d59277ebfc498c83bb039436ed7c89d2cd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.
TEST=Played tint on kontron/ktqm77. Score 606
Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Beside one tiny fix for framebuffer scaling, this contains a major
refactoring of libgfxinit's configuration infrastructure. With this,
we are finally able to detect CPUs at runtime and only have to confi-
gure a CPU/GPU generation.
Change-Id: Iccf4557453878536f527e4a1902439a1961ab701
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.
Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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These are part of a common concept and not SoC specific.
Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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It was only used locally.
Change-Id: Iaaad760e8ceca62655f5448c30846cf11959e8e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I5d155df1d589fc8d7462f46e87275bd6efae0a7f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Part of this checks whether tolum_base and cbmem_top are the same - however,
cbmem_top hasn't been initialised at the point where this call occurs.
Change the ordering to fix that.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.
Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Cosmetic change to reduce line length to 80 max.
BUG=NA
TEST=Build Portwell PQ7-M107
Change-Id: Ib537592c0a6a3fffc85622e6b74ad5ec8041e7dc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Now that support has been added for using the public FSP
repo for Braswell platform, clean up Kconfig options and
set sane defaults when using it.
The following changes have been made:
- add option to use the 3rdparty/fsp repo for Braswell platform
- reorder FSP 1.1 Kconfig entries for improved flow/readability
- set the default path for the FSP binary based on use of FSP
repo and platform
- set the CBFS location for the FSP binary based on platform
Change-Id: Ie2f732bf0ac4d4551908caa56360b8bb2869b4c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
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Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
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Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Since there is no standardized naming scheme for the
FSP binaries, the option USE_FSP_REPO can't be used
on some platforms, because some of the filenames differ
and the build process awaits "Fsp_*.fd" as filename.
As a workaround, add the option -n to SplitFspBin.py,
which defines the basename.
Change-Id: Idc684ad00033ffafd1090fc32b23549ce9603b4f
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30930
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.
Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.
BUG=N/A
TEST=LPC Post card on Intel Cherry Hill
Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
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This patch ensures to have same stack base for FSP and coreboot.
Feature added in FSP2.1
- Remove stack swapping from FSP.
- Stack will be shared between coreboot and FSP.
TEST=Build and boot FSP2.1 enable platform like dragonegg, iclrvp.
No car global variable corruption seen after enabling
this feature.
Change-Id: I673b4216d991d8ccad725c3931006a694184106c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32079
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add HrP 9560 module device ID (0x06F0) into device/pci_ids.h file.
TEST=HrP module is getting detected during PCI enumeration on CMLRVP
Change-Id: I8f6d89b1c6d03e2497f6b345a520323f45247d7e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32096
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the actual graphics init provided by libgfxinit into a sub package
`GMA.GFX_Init`. This way it can be compiled in individually.
Change-Id: Ib413a0d70c8dc305f4476c1d5aee6b81ff880bec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31456
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We might want to make use of libgfxinit functions without using it for
actual graphics init.
Change-Id: I29c3b19989acb678d0d447e83d38bad9d584caa9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31455
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch adds support for FSP2.1 Kconfig which is backward compatible
with FSP2.0 specification and added below coreboot impacted features as below:
1. Remove FSP stack switch and use the same stack with boot firmware
2. FSP should support external PPI interface pulled in via
FSP_PEIM_TO_PEIM_INTERFACE
Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30310
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to have below listed features:
1. All required APIs to create MP service structure.
2. Function to get MP service PPI status
MP specification here:
http://github.com/tianocore/edk2/blob/master/MdePkg/Include/Ppi/MpServices.h
coreboot design document here:
../Documentation/soc/intel/icelake/MultiProcessorInit.md
Supported platform will call fill mp_services structure so that FSP can
install the required PPI based on coreboot published structure.
BRANCH=none
BUG=b:74436746
TEST=Able to publish MP service PPI in coreboot.
Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25634
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0.
Allows to have a common entry after FSP-M.
Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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When VBOOT_STARTS_IN_BOOTBLOCK is selected, the tpm_setup call
in memory_init.c is not used.
When VBOOT_STARTS_IN_ROMSTAGE is selected, the tpm_setup call
in memory_init.c is triggered. However, when verstage runs,
tpm_setup is called yet again, and an error is triggered from
the multiple initialization calls.
Since there are currently no boards using
VBOOT_STARTS_IN_ROMSTAGE + FSP2_0_USES_TPM_MRC_HASH, disable
this combination via Kconfig, and remove the tpm_setup call
from Intel FSP memory initializion code.
* VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=y
vboot is enabled, and TPM is setup prior to Intel FSP memory
initialization. Allow FSP2_0_USES_TPM_MRC_HASH option.
* VBOOT=y VBOOT_STARTS_IN_BOOTBLOCK=n
vboot is enabled, but TPM is setup in romstage, after Intel
FSP memory initialization. Disallow FSP2_0_USES_TPM_MRC_HASH
option.
* VBOOT=n
vboot is disabled. Disallow FSP2_0_USES_TPM_MRC_HASH option.
See bug for more information:
https://bugs.chromium.org/p/chromium/issues/detail?id=940377
BUG=chromium:940377
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I4ba91c275c33245be61041cb592e52f861dbafe6
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31837
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds a generic provision into FSP2.0 driver to implement
dedicated PEIM to PEIM interface as per Intel FSP requirement.
Change-Id: I988d55890f8dd95ccf80c1f1ec2eba8196ddf9a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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We want to be able to specify the firmware variant suffix
in the devicetree.cb configuration for particular firmware
builds. This driver allows us to specify the firmware_variant
property in the device tree and have it populate a _DST table
in the SSDT ACPI table for the ISH device, thus making the
suffix available to the kernel (See crrev.com/c/1433482 for kernel
change that uses the value)
BUG=b:122722008
TEST=decompile DDST table and verify that new firmware-variant value
is present. Also verfied that kernel can access this new field using
the shim loader kernel CLs
Change-Id: Id8be986185282521aee574027503eaf8968e1508
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch adds few more required EFI return status into FSP2.0
drivers so that coreboot code can make use of those.
Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was
getting selected for cometlake soc also. Since FSP is not yet upstreamed
for cometlake, compilation was failing due to FSP was not found.
So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only
and excluding for cometlake.
Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit 3afb84a24583f5dee9fb407f11b32253d59392bf.
Reason for revert: This is causing issues with the PCIe link
and the system is unable to enter S0ix. Until it can be fixed
in coreboot revert the change here that is not working properly.
BUG=b:124264120
Change-Id: Ia20da9ab560ca35950b4a916667f51e0f541b382
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31559
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add HrP 9560 module device ID (0x02F0) into device/pci_ids.h file.
TEST=HrP module is getting detected during PCI enumeration
Change-Id: Id0a8a7a8cf7c665bd49f27b1c50d41d26a3274ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/31475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It is not mentioned in the FSP spec and doesn't seem to be implemented
for any other FSP than the Broadwell-DE one.
Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add maximum width and height options and set the default to 2560x1600
(WQXGA). The framebuffer will be scaled up to the displays' native
resolutions. So this should help with tiny fonts on high-DPI displays.
For laptops, reasonable defaults can be set at the mainboard level.
Change-Id: I47fba063629260c3a2854caf7a73f1a1e933d063
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I7a99d0dcbc8ea1362a12a68fa519c49058d30a05
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Does not fix 3rdparty/, *.S or *.ld or yet.
Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Default to FSP binary and headers shiped in 3rdparty/fsp.
* Drop headers and code from vendorcode/intel/fsp1_0/broadwell_de
* Select HAVE_FSP_BIN to build test the platform
* Fetch FSP repo as submodule
* Make FSP_HEADER_PATH known from FSP2.0 useable on FSP1.0
* Introduce FSP_SRC_PATH for FSP source file
* Add sane defaults for FSP_FILE
Tested on wedge100s.
Change-Id: I46f201218d19cf34c43a04f57458f474d8c3340d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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It was only hooked up for galileo board when using the obsolete
FSP1.1. I don't see how it can be useful...
Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30691
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I19e9038eb52922fa0c248936438f27789d00ddb5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Read back the stack guards after most of the romstage took place.
Change-Id: Ia7dc26c7ed1750d4ebbe7514ed87da57f9e34a89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Useful for debugging FSP.
Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.
BUG=B:117618636
BRANCH=None
TEST=Warm/cold reset for 10 times and didn't see unsupported request
related AER error messages & $lspci -vvs 00:1c.0|grep LTR and
ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68
and ensure bit10 is set.
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This allows to check if stack overflows the car globals.
Change-Id: I369b2d846f35914facb3e69cc762f7e555271bec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Have same usage of registers with romcc bootblock
and C_ENVIRONMENT_BOOTBLOCK.
Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I93cf734daefabe1f7cfaa5f49ba789ac04c8a635
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This adds a convenient helper function to add vbt binaries to cbfs.
Change-Id: I80d9b3421f6e539879ad4802119fe81d7ea1e234
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30430
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updates to current master.
This includes:
- A fix for textmode scaling on G45
- Refactor things to rely less on inline proving
- Increased width of modeline fields to 32 bits
Change-Id: Iab2915b747f6e4fa4e78eb28fea29bb3a9b3b687
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30311
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia42c1f8559667e7711fac919df8bfbee8455e3cc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Correct typo of 'Initialize'
BUG=N/A
TEST=N/A
Change-Id: I94cfd9c41bb5f9751ef4a18beaeba05108220bc8
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30016
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Backlight control of internal panels likely won't work as configuration
for that seems absent in coreboot. Also, libgfxinit doesn't support any
MIPI/DSI connections, yet, and neither Gemini Lake.
TEST=Booted work-in-progress port kontron/mal10 with VGA text and
linear framebuffer modes. DP display came up.
Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct typo of 'version'
BUG=N/A
TEST=N/A
Change-Id: I05d7856072042c79f9d7aafdfecc9b3635f1d0cc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Add support for updating microcodes on FSP 1.0 platforms
before memory is initialized. This is a requirement to
fill other FIT entries except for microcode updates.
Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29819
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct typo of 'compilation'
BUG=N/A
TEST=N/A
Change-Id: Iee6b8a8afc4d885d2d4ab9ee5d596e32e5e6d3f1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always.
This hob is only generated by FSP during non-S3 and MRC data is changed.
Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is
required.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
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It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.
Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.
TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
configs with and without this patch: binaries stay the same.
Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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soc/car_setup.S is included when SKIP_FSP_CAR is enabled,
but no chipset/SoC have car_setup.S available.
Remove include and post_code() call always solving build errors.
BUG=NA
TEST=NA
Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
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CONFIG_FSP_USES_UPD is not used by FSP 1.1.
Remove this config from this file.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If922b6cb2d39b10f6657b4d80e54b226d1386c76
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
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Returned status code FspTempRamInit() is not displayed when error occurs.
Move the printk() call before the check for status.
BUG=NA
TEST=Portwell PQ7-M107
Change-Id: Id87e5c765d09f4ab199db9eba07a949b031a709a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29695
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29303
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I801849fb31fe6958e3d9510da50e2e2dd351a98d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I405b79ee192317c86725f9bf0b1d166c045d30e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It's not Python 3 compatible.
Change-Id: Ibaad2c31bb6494652ce650ab7c1064728ec5fe80
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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