coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-06-30	src/drivers/intel: Avoid NULL pointer dereference	John Zhao
	Coverity detects dereferencing pointers that might be "NULL" when calling acpigen_write_scope and acpigen_write_device. Add sanity check for both of scope and name to prevent NULL pointer dereference. Found-by: Coverity CID 1429979, 1429982 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If17d12861f562dc0d6c98a5c91a9d3c0360ca2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42835 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26	drivers/intel/pmc_mux/con: Add new PMC MUX & CON chip drivers	Tim Wawrzynczak
	The Tiger Lake PMC device has a MUX device which is expected to be exposed in ACPI tables. The MUX device simply has a _HID and _DDN. The CON devices link the USB-2 and USB-3 port numbers (from SoC point of view) to the physical connector. They also have orientation options for the sideband (SBU) and USB High Speed signals (HSL), meaning that they can be fixed (i.e, another device besides the SoC controls the orientation, and effectively the SoC is following only CC1 or CC2 orientation), or they can follow the CC lines. BUG=b:151646486 TEST=Tested with next patch in series (see TEST line there) Change-Id: I8b5f275907601960410459aa669e257b80ff3dc2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>