coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2013-12-21	FUI: Fill in link_m and link_n values	Furquan Shaikh
	... based on the EDID detailed timing values for pixel_clock and link_clock. Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively. Calculations are based on the intel_link_compute_m_n from linux kernel. Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to hard-coded value. Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e Reviewed-on: https://gerrit.chromium.org/gerrit/62915 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-05	haswell: pull in the init code for FUI	Ronald G. Minnich
	Removed two unnecessary register sets, and did the power well a bit more correctly. Also, added a register definition include file so we can used constants instead of magic numbers. We also set registers to common initialized values that are needed for FUI, VBIOS, and kernel. This set of registers appears to be an absolute bare minimum. Since we're hoping to use FUI for all chipsets from this one forward, we unconditionally do the setting here. Signed-off-by: Ronald G. Minnich <rminnich@google.com> Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17 Reviewed-on: https://gerrit.chromium.org/gerrit/59988 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4328 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>