aboutsummaryrefslogtreecommitdiff
path: root/src/drivers/intel/fsp2_0
AgeCommit message (Collapse)Author
2016-07-19drivers/intel/fsp2_0: separate component validation from loadingAaron Durbin
The current FSP component loading mechanism doesn't handle all the requirements actually needed. Two things need to be added: 1. XIP support for MemoryInit component 2. Relocating SiliconInit component to not corrupt OS memory. In order to accommodate those requirements the validation and header initialization needs to be a separate function. Therefore, provide fsp_validate_component() to help achieve those requirements. BUG=chrome-os-partner:52679 Change-Id: I53525498b250033f3187c05db248e07b00cc934d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15740 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: implement common memory_init() tasksAaron Durbin
Instead of performing the same tasks in the chipset code move the common sequences into the FSP 2.0 driver. This handles the S3 paths as well as saving and restoring the memory data. The chipset code can always override the settings if needed. BUG=chrome-os-partner:52679 Change-Id: I098bf95139a0360f028a50aa50d16d264bede386 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15739 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: set BootLoaderTolumSize genericallyAaron Durbin
The amount of reserved memory just below the DRAM limit in 32-bit space is defined in the FSP 2.0 specification within the FSPM_ARCH_UPD structure. There's no need to make the chipset code set the same value as needed for coreboot. The chipset code can always change the value if it needs after the common setting being applied. Remove the call in soc/intel/apollolake as it's no longer needed. BUG=chrome-os-partner:52679 Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19drivers/intel/fsp2_0: fix hand-off-block types and sizeAaron Durbin
The gcc compiler treats sizeof(void) == 1. Therefore requesting a 1 byte reservation in cbmem and writing a pointer into the buffer returned is wrong. Fix the size of the request to be 32-bits because FSP 2.0 is in 32-bit space by definition. Also, since the access to the field happens across stage boundaries it's important to ensure fixed widths are used in case a later stage has a different pointer bit width. BUG=chrome-os-partner:52679 Change-Id: Ib4efc7d5369d44a995318aac6c4a7cfdc73e4a8c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15737 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-24drivers/intel/fsp2_0: Add simple reset handlerAndrey Petrov
Any FSP API call may request a reset. This is indicated in API function return code. Add trivial reset handler code. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: Ieb5e2d52ffdaf3c3ed416603f6dbb4f9c25a1a7b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-14drivers/intel/fsp2_0: Add FSP return types for resetAndrey Petrov
FSP methods may require reset under certain conditions. That is indicated by returning specific return code. Add the missing return status codes. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I460353c5f835548a98255bd3e11dbfd08260ea52 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15185 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09soc/intel/apollolake: Update FSP header filesBora Guvendik
Update autogenerated FSP 2.0 generic header files based on FSP release 136_30. Changes were made to avoid duplicating some of the structs for every SoC. BUG=chrome-os-partner:50765 TEST=Build coreboot Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7145 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7584 Reviewed-on: https://review.coreboot.org/15081 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h headerAlexandru Gagniuc
Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phaseHannah Williams
Change-Id: Ib39e828c6e3145957ecc2dacc1f72de793165514 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15020 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26drivers/intel/fsp2_0: Send post codes around calls to the blobsAlexandru Gagniuc
By design, FSP will send POST codes to port 80. In this case we have both coreboot and FSP pushing post codes, which may make debugging harder. In order to get a clear picture of where FSP execution begins and ends, send post codes before and after any call to the FSP blobs. Note that sending a post code both before and after is mostly useful on chromeec enabled boards, where the EC console will provide a historic list of post codes. Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFSAndrey Petrov
Add recipes that insert FSP blobs into CBFS and get rid of CBFS names hardcoding. Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-17drivers/intel/fsp2_0: Fix array indexing errorLee Leahy
Don't allow an array index of 2 to be processed by the code referencing the array. Found-by: Coverity CID 1353337 TEST=None Change-Id: I586ca14416a6e40971f8f6f4066fbdb4908ca688 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14868 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-05-12drivers/intel/fsp2_0: Add timestamps around all calls to the blobAlexandru Gagniuc
Change-Id: I384cef0f5b4b71dbd7ad6d1d508e7c6395bf3f2d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14759 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-06drivers/intel/fsp2_0: Update to FSP draft 9Andrey Petrov
Recent FSP draft slightly changed FSP_INFO_HEADER structure. This change keeps FSP driver code in sync with header changes. Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-19kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ schemeStefan Reinauer
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Also, fix up the following driver subdirectories by switching to the src/drivers/[X]/[Y]/ scheme as these are hard requirements for the main change: * drivers/intel * drivers/pc80 * drivers/dec Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14047 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08drivers/intel/fsp2_0: Add utility to recover MRC NV Storage dataHannah Williams
Change-Id: I08d3ba8b64459b1f84a5f1318e37c31010d7ae0f Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-08drivers/intel/fsp2_0: Add boot mode constantsAndrey Petrov
This adds boot mode constants. They match EDK2 found in PiBootMode.h constants but are part of FSP2.0 spec. Change-Id: I16ee90ff372d252ddc042ca89c1e5912ab041616 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14249 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-02lib/prog_loading: introduce prog_segment_loaded()Aaron Durbin
In order to not muddle arch vs chipset implementations provide a generic prog_segment_loaded() which calls platform_segment_loaded() and arch_segment_loaded() in that order. This allows the arch variants to live in src/arch while the chipset/platform code can implement their own. Change-Id: I17b6497219ec904d92bd286f18c9ec96b2b7af25 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14214 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-02drivers/intel/fsp2_0: signal that FSP components are loadedAaron Durbin
In order for the platform code to handle situations where special actions are required after a piece of code is loaded use arch_segment_loaded() to signal to the platform code that the component is fully loaded into memory. Change-Id: I119cfc9913f15eb4968fe5bf6a56589e2c53f2d1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: remove struct resource usageAaron Durbin
There's no need to use a struct resource type for fsp_find_reserved_memory(). struct resource is mainly associated with a device and that memory is added to cbmem after memory init. Other uses ins FSP 2.0 just use struct range_entry. Use that instead for consistency. Change-Id: Id7d39da1c2e23f97cdaafd7f5d281cefa6fee543 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13960 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: add TODOs to fix deficienciesAaron Durbin
The FSP 2.0 implementation doesn't handle FSP modules for SoCs that are required to be XIP. There is no notion of "loading" in that situation where one should be copying anything anywhere. Additionally, the loading code does not handle overlaps within the current running program which is doing the loading. Change-Id: Ide145581f1dd84efb73a28ae51b3313183fa127a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13959 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: don't leak resourcesAaron Durbin
rdev_mmap() was not followed by rdev_munmap(), thus leaking resources. Fix the leak. Change-Id: Ibdd30d6b64616038013b4bb748f2ad4a98db5472 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13958 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-08drivers/intel/fsp2_0: Add framebuffer graphics supportAlexandru Gagniuc
This adds a few helper functions that are intended to assist setting up framebuffer. Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13802 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add hand-off-block parsersAlexandru Gagniuc
FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13801 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add Notify Phase APIAndrey Petrov
This adds Notify Phase API. This is an important call that is used to inform FSP runtimes of different stages of SoC initializations by the coreboot. Change-Id: Icec770d0c1c4d239adb2ef342bf6cc9c35666e4d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13800 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add SiliconInit APIAndrey Petrov
This adds SiliconInit API that is needed to be called after memory has been trained. This call is needed to let the blob do various initialisations of IP blocks. Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08drivers/intel/fsp2_0: Add MemoryInit APIAndrey Petrov
This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13798 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-03drivers/intel/fsp2_0: Add utility functionsAndrey Petrov
This adds a set of utility functions that help load and identify FSP blobs. Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13797 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-03drivers/intel/fsp2_0: Add coreboot<->FSP header filesAndrey Petrov
This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13796 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-22 12:38:59 +0000