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path: root/src/drivers/intel/fsp2_0/util.c
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2018-10-22intel: Use CF9 reset (part 2)Patrick Rudolph
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also implement board_reset() as a "full reset" (aka. cold reset) as that is what was used here for hard_reset(). Drop soc_reset_prepare() thereby, as it was only used for APL. Also, move the global-reset logic. We leave some comments to remind us that a system_reset() should be enough, where a full_reset() is called now (to retain current behaviour) and looks suspicious. Note, as no global_reset() is implemented for Denverton-NS, we halt there now instead of issuing a non-global reset. This seems safer; a non-global reset might result in a reset loop. Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10drivers/intel/fsp2_0: Fix spacing issuesLee Leahy
Fix the following errors detected by checkpatch.pl: ERROR: space prohibited before that close parenthesis ')' ERROR: space required before the open parenthesis '(' ERROR: space prohibited before open square bracket '[' ERROR: spaces required around that ':' (ctx:VxE) TEST=Build and run on Galileo Gen2 Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18744 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API supportBrenton Dong
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Update the debug levelsLee Leahy
Choose appropriate debug levels for the various messages in the FSP driver. Change: * BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows builder to disable FSP driver output by selecting CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 * BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the payload from successfully booting TEST=Build and run on Galileo Gen2 Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16003 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03drivers/intel/fsp2_0: Disable display of FSP headerLee Leahy
Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16002 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28drivers/intel/fsp2_0: Update the copyrightsLee Leahy
Update the copyright dates in the FSP 2.0 files. Add a copyright to Kconfig. TEST=Build and run on Galileo Gen2 Change-Id: I0ad0c5650bde0e31d01a04bcc7d22a19273fe29b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-19drivers/intel/fsp2_0: Split reset handling logicAndrey Petrov
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The rest 6 codes are platform-specific and may vary. Modify helper function so that only basic resets are handled and let SoC deal with the rest. Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15730 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19drivers/intel/fsp2_0: remove unused fsp_load_binary()Aaron Durbin
Remove the now unused fsp_load_binary() function. BUG=chrome-os-partner:52679 Change-Id: I5667eb71689a69a9e05f7be05cb0c7e7795a55d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15743 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19drivers/intel/fsp2_0: separate component validation from loadingAaron Durbin
The current FSP component loading mechanism doesn't handle all the requirements actually needed. Two things need to be added: 1. XIP support for MemoryInit component 2. Relocating SiliconInit component to not corrupt OS memory. In order to accommodate those requirements the validation and header initialization needs to be a separate function. Therefore, provide fsp_validate_component() to help achieve those requirements. BUG=chrome-os-partner:52679 Change-Id: I53525498b250033f3187c05db248e07b00cc934d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15740 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24drivers/intel/fsp2_0: Add simple reset handlerAndrey Petrov
Any FSP API call may request a reset. This is indicated in API function return code. Add trivial reset handler code. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: Ieb5e2d52ffdaf3c3ed416603f6dbb4f9c25a1a7b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-06drivers/intel/fsp2_0: Update to FSP draft 9Andrey Petrov
Recent FSP draft slightly changed FSP_INFO_HEADER structure. This change keeps FSP driver code in sync with header changes. Change-Id: I3536f766a312b9eb73ab8940d91dc9b9dfa347f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14614 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-02lib/prog_loading: introduce prog_segment_loaded()Aaron Durbin
In order to not muddle arch vs chipset implementations provide a generic prog_segment_loaded() which calls platform_segment_loaded() and arch_segment_loaded() in that order. This allows the arch variants to live in src/arch while the chipset/platform code can implement their own. Change-Id: I17b6497219ec904d92bd286f18c9ec96b2b7af25 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14214 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-02drivers/intel/fsp2_0: signal that FSP components are loadedAaron Durbin
In order for the platform code to handle situations where special actions are required after a piece of code is loaded use arch_segment_loaded() to signal to the platform code that the component is fully loaded into memory. Change-Id: I119cfc9913f15eb4968fe5bf6a56589e2c53f2d1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: add TODOs to fix deficienciesAaron Durbin
The FSP 2.0 implementation doesn't handle FSP modules for SoCs that are required to be XIP. There is no notion of "loading" in that situation where one should be copying anything anywhere. Additionally, the loading code does not handle overlaps within the current running program which is doing the loading. Change-Id: Ide145581f1dd84efb73a28ae51b3313183fa127a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13959 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09drivers/intel/fsp2_0: don't leak resourcesAaron Durbin
rdev_mmap() was not followed by rdev_munmap(), thus leaking resources. Fix the leak. Change-Id: Ibdd30d6b64616038013b4bb748f2ad4a98db5472 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13958 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-03drivers/intel/fsp2_0: Add utility functionsAndrey Petrov
This adds a set of utility functions that help load and identify FSP blobs. Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13797 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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