Age | Commit message (Collapse) | Author |
|
Move all FSP error handling into the FSP 2.0 driver. This removes the
need to implement error handling within the SOC code.
TEST=Build and run on Galileo Gen2
Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15853
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Disable the chatty FSP behavior for normal builds. Use a Kconfig value
to enable the display of the FSP call entry points, the call parameters
and the returned status for MemoryInit, SiliconInit and FspNotify. The
debug code is placed into drivers/intel/fsp2_0/debug.c.
TEST=Build and run on Galileo Gen2
Change-Id: Iacae66f72bc5b4ba1469f53fcce4669726234441
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15989
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update the copyright dates in the FSP 2.0 files.
Add a copyright to Kconfig.
TEST=Build and run on Galileo Gen2
Change-Id: I0ad0c5650bde0e31d01a04bcc7d22a19273fe29b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15852
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The FSPS component can request resets. Handle those
generically.
BUG=chrome-os-partner:52679
Change-Id: I41c2da543420102d864e3c5e039fed13632225b4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15748
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The FSPS component loading was just loading to any memory address
listed in the header. That could be anywhere in the address space
including ramstage itself -- let alone corrupting the OS memory on
S3 resume. Remedy this by loading and relocating FSPS into cbmem.
The UEFI 2.4 header files include path are selected to provide the
types necessary for FSP relocation.
BUG=chrome-os-partner:52679
Change-Id: Iaba103190731fc229566a3b0231cf967522040db
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15742
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
|
|
By design, FSP will send POST codes to port 80. In this case we have
both coreboot and FSP pushing post codes, which may make debugging
harder. In order to get a clear picture of where FSP execution begins
and ends, send post codes before and after any call to the FSP blobs.
Note that sending a post code both before and after is mostly useful
on chromeec enabled boards, where the EC console will provide a
historic list of post codes.
Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add recipes that insert FSP blobs into CBFS and get rid of
CBFS names hardcoding.
Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Change-Id: I384cef0f5b4b71dbd7ad6d1d508e7c6395bf3f2d
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14759
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This adds SiliconInit API that is needed to be called after memory
has been trained. This call is needed to let the blob do various
initialisations of IP blocks.
Change-Id: I35e02f22174c8392e55ac869265a19c4309932e5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|