coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2016-07-19	drivers/intel/fsp2_0: handle XIP and non-XIP for FSPM component	Aaron Durbin
	The previously implementation for loading the FSPM component didn't handle platforms which expects FSPM to be XIP. For the non-XIP case, romstage's address space wasn't fully being checked for overlaps. Lastly, fixup the API as the range_entry isn't needed any longer. This API change requires a apollolake to be updated as well. BUG=chrome-os-partner:52679 Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15741 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19	drivers/intel/fsp2_0: implement common memory_init() tasks	Aaron Durbin
	Instead of performing the same tasks in the chipset code move the common sequences into the FSP 2.0 driver. This handles the S3 paths as well as saving and restoring the memory data. The chipset code can always override the settings if needed. BUG=chrome-os-partner:52679 Change-Id: I098bf95139a0360f028a50aa50d16d264bede386 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15739 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19	drivers/intel/fsp2_0: set BootLoaderTolumSize generically	Aaron Durbin
	The amount of reserved memory just below the DRAM limit in 32-bit space is defined in the FSP 2.0 specification within the FSPM_ARCH_UPD structure. There's no need to make the chipset code set the same value as needed for coreboot. The chipset code can always change the value if it needs after the common setting being applied. Remove the call in soc/intel/apollolake as it's no longer needed. BUG=chrome-os-partner:52679 Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-05-26	drivers/intel/fsp2_0: Send post codes around calls to the blobs	Alexandru Gagniuc
	By design, FSP will send POST codes to port 80. In this case we have both coreboot and FSP pushing post codes, which may make debugging harder. In order to get a clear picture of where FSP execution begins and ends, send post codes before and after any call to the FSP blobs. Note that sending a post code both before and after is mostly useful on chromeec enabled boards, where the EC console will provide a historic list of post codes. Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-18	drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFS	Andrey Petrov
	Add recipes that insert FSP blobs into CBFS and get rid of CBFS names hardcoding. Change-Id: I350abeffc4d23e45e339464d036716ecdb2ba83a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-08	drivers/intel/fsp2_0: Add MemoryInit API	Andrey Petrov
	This adds implementation of fsp_memory_init() that is used to train memory. Change-Id: I72268aaa91eea7e4d4f072d70a47871d74c2b979 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13798 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>