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path: root/src/drivers/intel/fsp1_1/romstage.c
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2017-07-17intel/fsp1_1: Don't consume FSP_SMBIOS_MEMORY_INFO_HOB in S3 resume pathSubrata Banik
FSP doesn't publish smbios_memory_info_guid during S3 resume path. Hence it's recommended to skip consuming this HOB in S3 resume. Bug=none Branch=none TEST=Build and boot Lars system with this patch. Change-Id: I321751523b1ea3326ffc23f4d4c53d5362482674 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-17drivers/intel/fsp1_1: Fix issues detected by checkpatchLee Leahy
Fix the following error and warnings detected by checkpatch.pl: ERROR: "foo * bar" should be "foo *bar" WARNING: line over 80 characters WARNING: else is not generally useful after a break or return WARNING: braces {} are not necessary for single statement blocks WARNING: suspect code indent for conditional statements (16, 32) WARNING: Comparisons should place the constant on the right side of the test TEST=Build and run on Galileo Gen2 Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18886 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-14drivers/intel/fsp1_1: Only display MMCONF address if supportedLee Leahy
Disable the display of the MMCONF_BASE_ADDRESS if it is not supported. TEST=Build and run on Galileo Gen2 Change-Id: Ie4f0fbf264662b5bc12ca923f25395e5e91defea Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18801 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-15soc/intel/common: remove mrc cache assumptionsAaron Durbin
Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: remove code duplicationAaron Durbin
The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17646 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-31src/drivers: Capitalize CPU, RAM and ACPIElyes HAOUAS
Change-Id: I720469ea1df75544f5b1e0cab718502d8a9cf197 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15983 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15drivers/intel/fsp1_1: align on using ACPI_Sx definitionsAaron Durbin
The SLEEP_STATE_x definitions in the chipsets utilizing FSP 1.1. driver have the exact same values as the ACPI_Sx definitions. The chipsets will be moved over subsequently, but updating this first allows the per-chipset patches to be isolated. BUG=chrome-os-partner:54977 Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15665 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03drivers/intel/fsp1_1: Make weak routines quietLee Leahy
Now that there is a better way of finding optional routines, make the weak routines quiet so that it may be used for the optional implementation. TEST=Build and run on Galileo Gen2 Change-Id: Ic58c7de216394f80aee3a78dd08bd4682783be42 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02drivers/intel/fsp1_1: Update weak MRC cache routinesLee Leahy
Update the weak functions for the MRC cache. TEST=Build and run on Galileo Gen2 Change-Id: I54a1252cfff1a2f68b163f0feb65e2bceb37f6a9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15042 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-04soc/intel/common/mrc_cache: Honor MRC data as a constant pointerAlexandru Gagniuc
The MRC cache API has absolutely no reason to modify the data it is asked to stash. Reflect that by taking all "data" parameters as const void *. Change-Id: I7a14ffd7d5726aa9aa5db81df82c06e7f87b9d9f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14250 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-03-29intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstageDuncan Laurie
For platforms that do verification of memory init (and have verstage execute before romstage) FSP should not attempt to re-initialize the TPM again in romstage as it has already been done. BUG=chrome-os-partner:50633 BRANCH=glados TEST=boot and resume on chell and ensure TPM is not re-initialized Change-Id: Ied6f39dc8dacdbc3d76070b6135de2308196ff53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fefd4d4b3fde4c7fe4b6de304790914b7a2f87d8 Original-Change-Id: I60a2e4e2d73270697218f094527e09d444e6ab56 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Previous-Reviewed-on: https://chromium-review.googlesource.com/332433 Original-(cherry picked from commit 2de1fd57fe1db7960e0bb86c64dccf827fa55742) Original-Reviewed-on: https://chromium-review.googlesource.com/332299 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14106 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-14Intel common: add microcode loading to romstage before fspmemoryinitrobbie zhang
The intend is to seek upgraded microcode in RW section and load it before Fsp memoryinit, to ensure any goodness in the microcode update, especially related to memory configuration, can be applied earlier. BUG=chrome-os-partner:50132 BRANCH=glados TEST=Built and boot on kunimintus. Verified microcode gets reloaded. Boot time impact is very minor. CQ-DEPEND=CL:327170 Change-Id: I1a5df1d1efa25fb256743dca6a661c828263ec7c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7f700c1876e53194748d1d1c66637b9419b7086 Original-Change-Id: I7083ec6305af9e14a57d7b0cb1bd800cd9e22f44 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/327193 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/13688 Tested-by: build bot (Jenkins) Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-01-28drivers/intel/fsp1_1: Remove extra include referencesLee Leahy
Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-27drivers/intel/fsp1_1: Enable builds without MRC cacheLee Leahy
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13437 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-11fsp1_1: supply fsp version to mrc_cache APIAaron Durbin
The memory init code needs to match the saved mrc data. To ensure that invariant holds supply the FSP version when using the mrc cache API. BUG=chrome-os-partner:46050 BRANCH=None TEST=Built and booted on glados. Verified version mismatch checking works. Change-Id: I3f6dd19cb15a18761d34509749adafc89a72ed2d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12701 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-27FSP 1.1: Move common FSP codeLee Leahy
Move the FSP common code from the src/soc/intel/common directory into the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values associated with this common code. BRANCH=none BUG=None TEST=Build and run on kunimitsu Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440 Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306350 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12156 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
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