Age | Commit message (Expand) | Author |
---|---|---|
2016-01-29 | intel/skylake: Implement native Cache-as-RAM (CAR) | Subrata Banik |
2015-12-03 | intel/fsp: Add post codes for FSP phases | Duncan Laurie |
2015-11-05 | fsp1_1: pass ROM_SIZE to FSP for cacheable RO region | Aaron Durbin |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-10-14 | fsp1_1: add verstage support | Aaron Durbin |
2015-10-11 | intel fsp1_1: prepare for romstage vboot verification split | Aaron Durbin |
2015-10-11 | intel: update common and FSP cache-as-ram parameters | Aaron Durbin |
2015-09-10 | FSP: Pass FSP image base address to find_fsp | Lee Leahy |
2015-08-31 | drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs | Alexandru Gagniuc |
2015-06-24 | FSP 1.1: Bring source up-to-date | Lee Leahy |
2015-05-23 | drivers/intel: Update FSP 1.1 Driver | Lee Leahy |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2015-05-12 | FSP 1.1 Comparison Base | Lee Leahy |