summaryrefslogtreecommitdiff
path: root/src/drivers/intel/dptf/dptf.c
AgeCommit message (Collapse)Author
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-21drivers/intel/dptf: Add DCFG supportSumeet Pawnikar
After final production, it's possible by setting particular bit using DCFG the OEM/ODM locks down thermal tuning beyond what is usually done on the given platform. In that case user space calibration tools should not try to adjust the thermal configuration of the system. By adding new DCFG (Device Configuration) it allows the OEM/ODM to control this thermal tuning mechanism. They can configure it by adding dcfg config under overridetree.cb file. The default value for all bits is 0 to ensure default behavior and backwards compatibility. For an example if Bit 0 being set represents Generic DTT UI access control is disabled and Bit 2 being set represents DTT shell access control is disabled. Each bit represents different configuration access control for DTT as per BIOS specification document #640237. It also gives the provision for user space to check the current mode. This mode value is based on BIOS specification document number #640237. BUG=b:272382080 TEST=Build, boot on rex board and dump SSDT to check DCFG value. Also, verified the newly added sysfs attribute "production_mode" present under /sys/bus/platform/devices/INTC1042:00 path. Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78386 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard
Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-14acpi: Comply with ACPI specification by making _STR unicode stringsCliff Huang
_STR should return Unicode string. From ACPI spec: 6.1.10 _STR (String) The _STR object evaluates to an Unicode string that describes the device or thermal zone. BUG=NA TEST=Check the changed _STR in SSDT to see if Unicode() macro is used Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I1f4b55a268c1dadbae456afe5821ae161b8e15a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77695 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-09-08arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12Reland "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 4dba71fd25c91a9e610287c61238a8fe24452e4e. Add multiple fan support for dptf policies. This also fixes the Google Meet resolution drop issue as per b:246535768 comment#12. When system starts Google Meet video call, it uses the hardware accelerated encoder as expected. But, as soon as another system connects to the call, an immediate fallback is observed from hardware to software encoder. Due to this, Google Meet resolution dropped from 720p to 180p. This issue is observed on Alder Lake-N SoC based fanless platforms. This same issue was not seen on fan based systems. With the fix in dptf driver where fan configures appropriate setting for only fan participant, not for other device participants, able to see consistent 720p resolution. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alder Lake-P Redrix system for two fans support and on Alder Lake-N fanless systems. With this code change Google Meet resolution drop not observed. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: Id07d279ff962253c22be9d395ed7be0d732aeaa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73249 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23drivers/intel/dptf: Implement API to fill DPTF platform infoSubrata Banik
This patch fills in a generic platform info structure based on the inputs from the SoC dptf header file (soc/dptf.h). It will help to make things common and drop unnecessary back and forth call between common code and SoC code. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3521882495485cef686655abd65337515bae5faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71111 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22drivers/intel/dptf: Add `soc_` prefix for `get_dptf_platform_info()`Subrata Banik
This patch makes the SoC specific callback code more readable by adding `soc_` prefix into the `get_dptf_platform_info()`. In nutshell this patch renames `get_dptf_platform_info()` to `soc_get_dptf_platform_info()`. TEST=Able to build Google/Rex without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-10-20Revert "drivers/intel/dptf: Add multiple fan support under dptf"Sumeet Pawnikar
This reverts commit 672bd9bee5c0045694ef20fe3e2f7a003bef0edd. Reason for revert: Gmeet resolution dropped. When system starts Gmeet video call, it uses the hardware accelerated encoder as per the expectation. But, as soon as another system connects to the call, the immediate fallback observed from hardware to software encoder. Due to this, Gmeet resolution dropped from 720p to 180p. Currently, this issue observed on AlderLake-N SoC based fanless platforms. This issue is not seen on fan based systems. BUG=b:246535768,b:235254828 BRANCH=None TEST=Built and tested on Alderlake-N systems. With this revert Gmeet resolution drop not observed. Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2022-09-04drivers/intel/dptf: Add multiple fan support under dptfSumeet Pawnikar
Add multiple fan support for dptf policies BUG=b:235254828 BRANCH=None TEST=Built and tested on Redrix system for two fans Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-16drivers/intel/dptf: Correct UID for TBAT deviceVarshit B Pandya
As per Intel Dynamic Tuning Spec revision 1.3.13, section 14.1.2 TBAT _UID should match the _UID implemented for battery device ACPI object for OS _UID for TBAT is currently set to "TBAT" but should be 1. Battery device is define at src/ec/google/chromeec/acpi/battery.asl Setting _UID to 1 because right now ChromeOS is the only user of DPTF driver TEST: Build and boot brya0 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I1e4474e59cf01f937fbd51e5b674a609f0c47625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20drivers/intel/dptf: Add support for PROP methodVarshit B Pandya
Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of platform power in miliWatts. This value is static, which has to configured from devicetree of overridetree for each platform BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check PROP method Scope (\_SB) { Device (DPTF) { Device (TPWR) { Method (PROP, 0, Serialized) { Return (XXXX) } } } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-05drivers/intel/dptf: Add support for Battery participantVarshit B Pandya
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add support for TBAT device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TBAT device Device (TBAT) { Name (_HID, "INTC1061") // _HID: Hardware ID Name (_UID, "TBAT") // _UID: Unique ID Name (_STR, "Battery Participant") // _STR: Description String Name (PTYP, 0xC) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-04-01drivers/intel/dptf: Add support for Power participantVarshit B Pandya
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) Add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "INTC1060") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-26dptf: Add support for one more temperature sensorTim Wawrzynczak
Some boards may use more than 4 temperature sensors for DPTF thermal control, so this patch adds support for one more temperature sensor. BUG=b:207585491 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-10-11drivers/intel/dptf: return package with valueSumeet Pawnikar
Return the package with a value for the dptf user space service. This is required in write tpch method for pch device under dptf driver. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-11drivers/intel/dptf: Add support for PCH methodsSumeet Pawnikar
Add various methods support for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-05drivers/intel/dptf: Add new thermal control mechanism for pch deviceSumeet Pawnikar
Add new thermal control mechanism for pch device under dptf driver. This provides support of different control knobs for FIVR. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08IMOK: Add IMOK method support for DPTFSumeet Pawnikar
Add IMOK method support for DPTF BRANCH=None BUG=b:187797417 TEST=Built and tested on dedede board Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01drivers/intel/dptf: Add OEM variables supportSumeet R Pawnikar
This adds OEM variables feature under DPTF as per BWG doc #541817. Using this, platform vendors can expose an array of OEM-specific values as OEM variables to be used in determining DPTF policy. These are obtained via the ODVP method, and then simply exposed under sysfs. In addition, these gets updated when a notification is received or when the DPTF policy is changed by userspace. BRANCH=None BUG=b:187253038 TEST=Built and tested on dedede board Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-13dptf: Move platform-specific information to `struct dptf_platform_info`Tim Wawrzynczak
DPTF HIDs are different per-platform going forward, so refactor these into SoC-specific structures which the DPTF driver can query at runtime for platform-specific information. Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-01acpi: Move PCI functions to separate fileTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26drivers/intel/dptf: Add missing Scope operator for _FIFTim Wawrzynczak
Missed one other scope operator in the DPTF cleanup. This one is for the fan device, and without this fix, the kernel isn't able to properly control the fan (it gets confused about whether it's ACPI 4+ compatible or not). BUG=b:149722146 TEST=verify /sys/class/thermal/cooling_zone0/max_state returns > 1, and /sys/class/thermal/cooling_zone0/cur_state is writable, and writing the value of `max_state` causes the fan to spin faster. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7bd83967ace761ddd17eaeae9c25abb0b2cbe413 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-18drivers/intel/dptf: Add missing scope operator around TSR optionsTim Wawrzynczak
The previous DPTF patch train missed the proper scope operator around all of the TSR options. Without this, the optional GTSH and/or _STR Methods end up in the wrong scope. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9298c442c047c5f7f606574d900057a7c004b47f Reviewed-on: https://review.coreboot.org/c/coreboot/+/43458 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18dptf: Fix scope of TCPU deviceTim Wawrzynczak
In the initial DPTF refactor, the scope of the TCPU device was incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the way that the acpi_inject_dsdt() callback currently works (it injects contents before the dsdt.aml file), the Scope where the TCPU device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing games with *when* things are defined in the DSDT, switch to defining all of the DPTF devices in the SSDT. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07dptf: Add support for IDSPTim Wawrzynczak
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the implementation supports. Added a new acpigen function to figure out which policies are used, and fills out IDSP appropriately. Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan and TSR optionsTim Wawrzynczak
DPTF has several options on how to control the fan (fine-grained speed control, minimum speed change in percentage points, and whether or not the DPTF device should notify the Fan if it detects low speed). Individual TSRs can also set GTSH, which is the amount of hysteresis inherent in the measurement, either from circuitry (if analog), or in firmware (if digital). BUG=b:143539650 TEST=compiles Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Running Average Power LimitsTim Wawrzynczak
This change adds support for emitting the PPCC table, which describes the ranges available as knobs for DPTF to tune. It can support min/max power, min/max time window for averaging, and the minimum adjustment size (granularity or step size) of each power limit. The current implementation only supports PL1 and PL2. BUG=b:143539650 TEST=compiles Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Fan Performance StatesTim Wawrzynczak
This change adds support for generating the _FPS table for the DPTF Fan object. The table describes different levels of fan activity that may be applied to the system in order to actively cool it. The information includes fan speed at a (rough) percentage level, fan speed in RPM, potential noise level in centibels, and power in mA. BUG=b:143539650 TEST=compiles Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Charger Performance StatesTim Wawrzynczak
This change generates the DPTF TCHG.PPSS table in the SSDT. This table describes different charging rates which are available to use. DPTF can pick different rates in order to passively cool (or not) the system. BUG=b:143539650 TEST=compiles Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Critical PoliciesTim Wawrzynczak
This patch adds support for DPTF Critical Policies, which are consist of Method definitions only. They are `_CRT` and `_HOT`, which are defined as temperature thresholds that, when exceeded, will execute a graceful suspend or a graceful shutdown, respectively. BUG=b:143539650 TEST=compiles Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for Passive PoliciesTim Wawrzynczak
This patch adds support for emitting the Thermal Relationship Table, as well as _PSV Methods, which together form the basis for DPTF Passive Policies. BUG=b:143539650 TEST=compiles Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07dptf: Add support for generation of Active PoliciesTim Wawrzynczak
This change adds support for generating the different pieces of DPTF Active Policies. This includes the Active Relationship Table, in addition to _ACx methods. BUG=b:143539650 TEST=compiles Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-07-07drivers/intel/dptf: Add current participant Devices to DSDTTim Wawrzynczak
In this DPTF implementation, the participant device objects are written into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID, PTYP, and _STR). All other Methods & Names will be written into the SSDT. If a device is not used in any policy, then its _STA is set to return 0 ("off"). BUG=b:143539650 TEST=Compiles. Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-14dptf: Introduce new paradigm for configuring DPTF parametersTim Wawrzynczak
Currently, configuring and reviewing DPTF parameters is difficult because DPTF tables and methods are defined in static ASL files, and are littered with #ifdefs which both define parameters and influence behavior (e.g., whether a method is included or not). This patch train is an effort to bring DPTF support to our ACPI DSDT/SSDT generation framework. This first patch is very minimal, and includes only creation of the DPTF device (in the DSDT). BUG=b:143539650 TEST=compiles (later tests get more comprehensive). Change-Id: I14df9f422c911677aeea25552ac1822a9462c58a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41883 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 16:16:02 +0000