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<device/device.h> is supposed to provide <device/{path,resource}.h>
Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.
BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.
Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Martin L Roth <martinroth@google.com>
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Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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By default, the HS400 mode of GL9763E is slow mode (150MHz).
Therefore, the slow mode is disabled for HS400 running at 200MHz.
For eMMCs such as Hynix (H26M74002HMR) on HS400, adjust the internal
Rx latch dealy of HS400 to have better compatibility.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I84844c2432d4223d9929182c5c430915e52875b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Booting on Kingston (EMMC64G-TA29/TX29-HP) and Hynix (H26M74002HMR) eMMC
currently fails due to R/W error. This is a workaround to finetune the
data latch timing by verdor-specific setting of GL9763E. For improving
the compatibility of GL9763E with these two eMMC.
Signed-off-by: Renius Chen <reniuschengl@gmail.com>
Change-Id: Iddb145ed6a9edb2d7a50248e64659cda78b88ae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The device is a PCIe to eMMC bridge controller to be used in the
Chromebook as the boot disk. The datasheet name is GL9763E and
the revision is 02.
The patch sets single request AXI, disables ASPM L0s and enables SSC.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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