coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-12-10	drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM	Duncan Laurie
	Configure the CFG2 register to set the latency to <64us in order to ensure the L1 exit latency is consistent across devices and that L1 ASPM is always enabled. This moves the setup code from device init to device enable so it executes before coreboot does ASPM configuration, and removes the call to pci_dev_init() as that is just for VGA Option ROMs. BUG=b:173207454 TEST=Verify the device and link capability and control for L1: DevCap: Latency L1 <64us LnkCap: Latency L1 <64us LnkCtl: ASPM L1 Enabled Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-18	drivers/genesyslogic/gl9755: Add driver for Genesys Logic GL9755	Ben Chuang
	The device is a PCIe Gen2 to SD 4.0 card reader controller to be used in the Chromebook. The datasheet name is GL9755S and the revision is 05. The patch sets LTR value. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I16048dde348be248c748d50ca4a8a62c8a781430 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>