| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-02-26 | During DRAM initialization on certain ASpeed devices, an incorrect | Timothy Pearson | |
| bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13807 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> | |||
| 2015-10-24 | drivers/aspeed: Add native text mode VGA support for the AST2050 | Timothy Pearson | |
| Change-Id: I37763a59d2546cd0c0e57b31fdb7aa77c2c50bee Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11937 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins) | |||
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |