summaryrefslogtreecommitdiff
path: root/src/device
AgeCommit message (Collapse)Author
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-10-23{device,drivers}: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: Iebb043a6fbc5803fbb7cad2f35b43917e10d09d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28700 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22reset: Provide new single-function reset APINico Huber
board_reset() replaces the existing common reset API. There is no common distinction between reset types across platforms, hence, common code could never decide which one to call. Currently only hard_reset() is used by common code. We replace these calls and provide a fall-back to the current hard_reset() implemen- tation. The fall-back will be removed along with hard_reset() after the transition of all boards. Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-19src/device/device.c: Don't use device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I3d1bdefd00c91a98116ede5dc03c3ce253d1f0ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-09-14device/ddr3: Prevent overflow when adding SMBUS Table 17 entriesNico Huber
Change-Id: If84c6849011106b2a50e504b79cda9cd6a3a9cc3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/28588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-11src/device/dram: Fix typoElyes HAOUAS
Change-Id: I5d8e5f978c538d2b9f74b29e21eb39ce6455315f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-21nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.cPatrick Rudolph
There's nothing Sandy Bridge specific in this code. Make it available on all platforms to reduce code duplication. Tested on Lenovo T430: SMBIOS entry 17 is still valid. Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20nb/intel/sandybridge: Fill in DIMM serial numberPatrick Rudolph
Fill in SMBIOS type 17 DIMM serial number, read from SPD. Fixes FWTS SMBIOS type 17 test. Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-09src/device: Fix typoElyes HAOUAS
Change-Id: I65e57b37db9649b30ca25b2150f21ebffee73105 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/device/pci_rom.c: Remove double initializationRichard Spiegel
In procedure pci_rom_probe(), variable vendev is initialized twice. Remove one initialization. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I8a71aa1aea2047ab2d98e09d1d6610de552b6cb4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27949 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08device/pci_device.c: Remove unused variable attr settingRichard Spiegel
In procedure pci_get_resource, when setting an IO mapped base address, variable attr is &= with PCI_BASE_ADDRESS_IO_ATTR_MASK. However, in this particular code flow variable attr is not used later. Remove the line. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: Ia4fdda1be92d22017a7a913a911db15aaa440b69 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-29pnp_device: don't treat missing PNP_MSC devicetree entry as errorFelix Held
Change-Id: I8da01cd462225b633bf2043ab33b35aeddc8d55a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29device/pnp_device: rewrite pnp_get_ioresourceFelix Held
The rewrite simplifies the code and fixes the limit on the case of IO resources with the length of 1 byte. This patch is inspired by the comment of Nico Huber on Ia99b785dcd9cf56fb236ad7ade54656851f88a5e If the ones in the mask aren't a continuous block, now a warning message gets printed. Change-Id: I0089278f5adf65e8f084580bc5bc1eb2f77b87f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-26device: add child traversal helper functionAaron Durbin
Add a function, dev_bus_each_child(), which walks through all the children for a given bus of a device. This helper allows one to walk through all the children of a given device's bus. BUG=b:111808427,b:111743717 TEST=built Change-Id: Iedceb0d19c05b7abd5a48f8dc30f85461bef5ec6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-19device/pci: Add MSI-X helper functionsPatrick Rudolph
Basic PCI MSI-X table helper functions. Imported from GNU/Linux kernel PCI subsystem. To be used on Cavium to configure MSI-X tables. Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26329 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17pnp_device: improve readabilityFelix Held
Add comments on the ops handling in pnp_enable_devices function and the pnp_info struct. Also remove the negation in the check if an LDN-specific override is used. This patch doesn't change the logic though. Change-Id: I3e80dbce1f29ee3e95e3b1d71c9b8479561d5c1a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-09src/{device,drivers}: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ic1c9b1edd8d3206a68854107ddcbc5c51cb487c3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-29src/device: Add check for existence and validity of PCIE base address configAamir Bohra
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e958518d Reviewed-on: https://review.coreboot.org/27263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06drivers/intel/gma: Include mainboard data.vbtArthur Heymans
This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path to point to the mainboard dir and to select INTEL_GMA_ADD_VBT_DATA_FILE by default. Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-04device: Only expose VGA_ROM_RUN on supported architecturesPatrick Rudolph
The yabel emulator depends on IO ports, that aren't available on ARM and MIPS. Add additional dependencies to fix compilation errors with the default configuration. Change-Id: If0e28b356c01cb3ae0739a54aa3531a2acedbfbb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26754 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25device: Move find_dev_path() to device_const.cKyösti Mälkki
Change-Id: I8a27aa7157b5706623272ba9354ed8dff9b8184f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-25device: Move dev_find_path() to device_const.cNico Huber
Make it available early and use it in dev_find_next_pci_device(). Change-Id: I1d0ad07f37ea79dae2b9a592fcccba5e03fd86d5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-25device: Rename device_simple.c --> device_const.cNico Huber
In early stages (pre ramstage), we have two notions of devices. To access the hardware, "simple device" handles are used. These are plain numbers. To access the static information of the device tree, we use `struct device` pointers. This is referred to as DEVTREE_EARLY in the code. This file is about the latter and its name reflects that the tree remains unmodified. Change-Id: I31aeb118615e86026f7111f83a7866d4e7426170 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-24device: Always build device_simple.c for less code duplicationNico Huber
Change-Id: Iec0a11d67d7641996f26b3a01352be762006ebb6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-22src/device: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. The function prototype for "struct device *add_cpu_device" is already correct and doesn't need to be fixed. Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26067 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22device/device_util.c: Remove space after sizeofElyes HAOUAS
Change-Id: Ic8b77c78739badbea398053944484a55f715d03d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11devicetree: Add USB device typeDuncan Laurie
This commit adds support for describing USB ports in devicetree.cb. It allows a USB port location to be described in the tree with configuration information, and ACPI code to be generated that provides this information to the OS. A new scan_usb_bus() is added that will scan bridges for devices so a tree of ports and hubs can be created. The device address is computed with a 'port type' and a 'port id' which is flexible for SOC to handle depending on their specific USB setup and allows USB2 and USB3 ports to be described separately. For example a board may have devices on two ports, one with a USB2 device and one with a USB3 device, both of which are connected to an xHCI controller with a root hub: xHCI | RootHub | | USB2[0] USB3[2] device pci 14.0 on chip drivers/usb/acpi register "name" = ""Root Hub"" device usb 0.0 on chip drivers/usb/acpi register "name" = ""USB 2.0 Port 0"" device usb 2.0 on end end chip drivers/usb/acpi register "name" = ""USB 3.0 Port 2"" device usb 3.2 on end end end end end Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08Move `pci_ops_mmconf` from arch/x86/ to device/Nico Huber
MMConf is not architecture specific. We also always provide a pci_bus_default_ops() now if MMCONF_SUPPORT is selected. Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26062 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08device/pci_ops: Remove unnecessary weak implementationNico Huber
I doubt this is or will ever be referenced anywhere. And if, we probably shouldn't return. Change-Id: I3704fec694c5e5a9d5ff7d78d8bf2f23cf463e3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04device/root_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ia25c5097d4cfa979c18a855e656ad794c2f0260c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pci_class.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I839533a33aa54df4efed3f372c6f88e79b0b559b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pcix_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I14c0db71ffa5faa8321c88c9c75c0c18a70910e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/smbus_ops.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I5eb858df7b69a7177564c883b81177ffadc63691 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/cardbus_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I6f3efd8c9be7f9fb83b373fbee311b06cde54181 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pciexp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pnp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ic25d1eb3c7f0ed5b65aa1cf9e16c39415b7cd3c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-02src/device: Fix discarded-qualifiers compilation issueSubrata Banik
coreboot build is broken due to CL: I6830a65bc9cea2907f4209bb97a53ccebcbf248d This patch ensures to build coreboot successfully. Change-Id: I4c9dfc9b19ce159ce1abcfbb287be4ce273cbaf1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-02pci: Fix MMCONF_SUPPORT on non x86Patrick Rudolph
Move x86 specific pci_bus_default_ops into arch/x86 folder. Fixes compilation on platforms that do neither have MMCONF_SUPPORT nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI. Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02software_i2c: Improve error behaviorJulius Werner
This patch fixes a bug in the software_i2c (bitbang) framework where it would previously not return an error when receiving a NACK on a write transaction (deviating behavior from our hardware I2C drivers). It also adds explicit error codes to be returned for the different kinds of failure conditions so they are more useful for debugging when dumped. Change-Id: Ie63bf35123d89dcd99a1f9c079d4cae6a33b0b09 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-04-30device: constify some variablesLubomir Rintel
Change-Id: I6830a65bc9cea2907f4209bb97a53ccebcbf248d Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25873 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-26device: Add flag to disable PCIe ASPMNico Huber
For broken devices that spuriously advertise ASPM, make it possible to decide ASPM activation in the device driver. Change-Id: I491aa32a3ec954be87a474478609f0f3971d0fdf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25617 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-23device/oprom/yabel: Fix spelling of *successful*Paul Menzel
Remove one *l* at the end. Change-Id: Ife5af64b380dc5d31f22873f1639382d2bf9a5d9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-20device/oprom/yabel: Fix vbe-buffer index in vbe.cHal Tsai
There's a issue about {VbeSignature to "VBE2" to indicate VBE 2.0+ request}, these indexes are counted wrong. Change-Id: I8ec85df60076162518aa55a94fa7b66c0c2391ab Signed-off-by: Hal Tsai <hal_tsai@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-04-16device/dram/ddr3: improve XMP supportDan Elkouby
- Fix offsets for supported CAS latencies - Add support for reading CWL and CMD rate from the profile Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649 Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com> Reviewed-on: https://review.coreboot.org/25663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-09device/dram/ddr2.c: Add methods to compute to identify dramArthur Heymans
DDR2 DIMMs are uniquely defined by SPD byte 64 till 72 and 93 till 98. Compute a crc16 over that data to provide a solid way to check DIMM identify. Reuse the crc16 function from ddr3.c to do this. Change-Id: I3c0c42786197f9b4eb3e42261c10ff5e4266120f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-03-14src/device/dram/ddr2: Fix supported burst lengthsElyes HAOUAS
Supported burst lengths are described at byte 16 Change-Id: I502710bdac7eec715b29febefd64be88e5a1b80a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-08timestamps: Add timestamps around the vbios load & initMartin Roth
Add timestamps before and after the vBIOS load and after the vBIOS run. This lets us see exactly how long it took to load it from the ROM chip, and how long it takes to run. BUG=b:64549506 TEST=Build & boot Grunt, see vBIOS load & initialization times. Change-Id: I878ba653eb086ad6c6614aa08a6d3fe216a9323e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25018 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22device/ddr2,ddr3: Rename and move a few thingsArthur Heymans
In order for ddr2.h and ddr3.h to be included in the same file it cannot have conflicting definitions, therefore rename a few things and move some things to a common header. Change-Id: I6056148872076048e055f1d20a60ac31afd7cde6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-02-22device: Include devicetree in SMM stageSubrata Banik
Allow bootblock to get access to the entire static device tree as other stages can access independently. TEST=SMM code now can access devicetree.cb variables. Change-Id: I59537c16f0a459e48d8b1efb5c1b196302f13381 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01Add a default path for vbt.binArthur Heymans
FSP_GOP needs a vbt.bin to work but before this patch it was able to build with the default configuration which was an empty path for vbt.bin. To make Jenkins happy don't select FSP_GOP by default, at least until all boards have the proper vbt blobs in the blobs repo. Change-Id: Ibc36d6d4dd1a56c53819b169e6f4799ce3c23e03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-02-01device: add ALWAYS_RUN_OPROM optionAaron Durbin
Certain platforms require that the option rom always needs to be ran in order for display to work correctly. Therefore, provide this ability for the platform to select such that we force option rom loading. BUG=b:72400950 Change-Id: I597bc8af7ac8b68fe8505aac5f1c7e1ccd34ac27 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23505 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-01device/pci_device: remove #if/#endif in oprom logicAaron Durbin
Use C if conditions instead of preprocessor macros. BUG=b:72400950 Change-Id: I8107f94b9ecb6f32c569cad0bcb3d51ab39aa35c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23504 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31device/pci_rom: Write _ROM method for VGA devicesPatrick Rudolph
Write _ROM method and store PCI Option ROM in CBMEM. Allows an EFI compatible OS to retrieve the Option ROM without the need to access the PCI BAR. As the Option ROM is no longer present in the legacy VGA area it's required for mobile platforms. On hybrid devices, like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to map. Tested on: * Lenovo T530 * Linux Kernel 4.13.7 * nouveau Change-Id: I548b730fb64833083cc05af5b21dd6959804224b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25sconfig: Add a new mmio resource typeJustin TerAvest
Add support for a mmio resource in the devicetree to allow memory-mapped IO addresses to be assigned to given values. AMD platforms perform a significant amount of configuration through these MMIO addresses, including I2C bus configuration. BUG=b:72121803 Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24device/i2c_bus: allow i2c_bus and i2c_simple to coexistAaron Durbin
If one wants to implement both i2c_bus.h and i2c_simple.h APIs the compilation unit needs to be guarded or coordinated carefully with different compilation units. Instead, name the i2c_bus functions with _dev such that it indicates that they operate on struct device. One other change to allow i2c_bus.h to be built in non-ramstage environments is to ensure DEVTREE_CONST is used for the dev field in struct bus. BUG=b:72121803 Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-15Intel i82830 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/intel/socket_mFCBGA479 northbridge/intel/i82830 Mainboards: mainboard/rca/rm4100 mainboard/thomson/ip1000 Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-20device/dram/ddr2.c: Store the checksum in the decoded SPD structArthur Heymans
Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-12-13device: Make pci_dev_ops_pci structure globalSubrata Banik
This patch makes pci_dev_ops_pci structure global so that caller can make use of this structure using extern. Change-Id: I8de919aacccbc062475fb04f59ffb4957d3460b9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-08device/pciexp_device: Set values numerically instead of as bitmaskPatrick Georgi
As noted on linux-pci, we have a weird way to handling "value" and "scale" fields that are supposed to contain numerical values: we encode them as a bitfield. Instead define the two fields (offset and mask) and use numbers. Another issue, not fixed in this CL, is that we write hard-coded values while these fields really need to contain the max() of acceptable delays of the downstream devices. That way the controller can decide whether or not to enter a deeper power management state. It's noted as a TODO. Change-Id: I895b9fe2ee438d3958c2d787e70a84d73eaa49d2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-on: https://review.coreboot.org/22740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-15device: further untangle device_t from struct deviceAaron Durbin
This further allows compilation units to be re-used without having to add macro guards because of declarations not being around in the __SIMPLE_DEVICE__ case. These declarations are for functions that operate on struct device. struct device is a known type so just expose the functions using the correct type. Also, DEVTREE_CONST is empty while in ramstage so there's no reason to separate the declarations. Lastly, fix up device_util.c to use the proper types. It's only compiled in ramstage and it only operates on struct device. Change-Id: I306e0ad220cdab738cb727dda4a93bdec77c5521 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07device/device_util: Add string for DEVICE_PATH_NONEPatrick Rudolph
Add string for DEVICE_PATH_NONE in dev_path. The enum DEVICE_PATH_NONE can be translated to string and shouldn't be translated by "Unknown device path type: 0". Makes console output a lot prettier and readable. Note: DEVICE_PATH_NONE is used on dummy devices for hotpluggable slots. Change-Id: I08d471d8217f966e80daefe2d9971e357defde62 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13src/device: Update LTR configuration schemeAamir Bohra
This patch moves out LTR programming under L1 substate to pchexp_tune_device function, as substate programming and LTR programming are independent. LTR programming scheme is updated to scan through entire tree and enable LTR mechanism on pci device if LTR mechanism is supported by device. BRANCH=none BUG=b:66722364 TEST=Verify LTR is configured for end point devices and max snoop latency gets configured. Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/21868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26device/dram/ddr2.c: fix a hidden syntax error introduced earlierBill XIE
A regression is hidden in commit 7eb0157fca33865783c1cc3c8e5cb2e327e551d7 (device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag ), which breaks the build procedure when CONFIG_DEBUG_RAM_SETUP is set. Maybe it had better implement "printram" and the like as inline functions instead of macros. Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21673 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-22device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flagArthur Heymans
"Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note 4 says bit7 of byte 12 indicates whether the assembly supports self refresh. This patch decodes this and modifies decoding tRR accordingly. Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-22device/dram/ddr2: Add break to several case statements that lack itPatrick Georgi
For all valid SPD values the same decoded tRR was returned. Change-Id: Iec43f8c7460dfcf68f7c92dfdf333b004f368b65 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Coverity Scan #1381369, #1381370, 1381371, 1381372, 1381373 Reviewed-on: https://review.coreboot.org/21642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-22arch/x86: Enable ebda library for romstage and postcarSubrata Banik
This patch provides a kconfig option as EARLY_EBDA_INIT to ensures user can make use of EBDA library even during early boot stages like romstage, postcar. Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20device/dram/ddr2.c: Improve error returning and debug outputArthur Heymans
This patch outputs decoding errors with BIOS_WARNING instead of depending on CONFIG_DEBUG_RAM_SETUP. Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK and doesn't try to create a valid setting if an invalid setting is detected. Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-16device/dram/ddr2: Fix decoding tRRArthur Heymans
Bit 7 is set on all options so only the default option in the switch statement is returned. Change-Id: I6a698ec9c15a2611a34c5965edf93638553775f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06device/dram/ddr2: Add a function to normalize tCLKArthur Heymans
Also make most significant bit function accessible outside the scope of this file. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-04Kconfig: Move and rename ADD_VBT_DATA_FILEPatrick Rudolph
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to INTEL_GMA_ADD_VBT_DATA_FILE. Depend on Intel platforms to avoid confusing users of non-Intel platforms. The Intel GMA driver will use the vbt.bin, if present, to fill the ACPI OpRegion. Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-31cpu/x86 asm: Just use the correct op suffixEdward O'Callaghan
LLVM AS doesn't support as much GNU junk extensions, data16/32 is almost never needed in truth if we just use the correct op suffix. So do that here, fixes clang/llvm builds with the integrated-as toggled on. Change-Id: I6095d03d0289b418a49a10f135de5eb0e117cae0 Also-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18device/smbus: Reuse I2C bus operations where applicableNico Huber
Reuse generic I2C functions that work for SMBus operations as well. Change-Id: I5a93f17b905de38752254891aa4347ba4ed3b205 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18Reinvent I2C opsNico Huber
Do not use the global platform_i2c_transfer() function that can only be implemented by a single driver. Instead, make a `struct device` aware transfer() function the only interface function for I2C controller dri- vers to implement. To not force the slave device drivers to be implemented either above generic I2C or specialized SMBus operations, we support SMBus control- lers in the slave device interface too. We start with four simple slave functions: i2c_readb(), i2c_writeb(), i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec- tive SMBus functions. But we keep aliases because it would be weird to force e.g. an I2C EEPROM driver to call smbus_read_byte(). Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15device/smbus: Drop some never used boilerplateNico Huber
It was added with the words "Update the device header files" and we maintained it for nearly 13 years :) These functions are part of the SMBus spec but they are rarely used and keeping them just in case increases the maintenance burden. Change-Id: I69a1ea155a21463fc09b7b2c5b7302515a0030b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
Our current struct for I2C segments `i2c_seg` was close to being compa- tible to the Linux version `i2c_msg`, close to being compatible to SMBus and close to being readable (e.g. what was `chip` supposed to mean?) but turned out to be hard to fix. Instead of extending it in a backwards compatible way (and not touching current controller drivers), replace it with a Linux source compatible `struct i2c_msg` and patch all the drivers and users with Coccinelle. The new `struct i2c_msg` should ease porting drivers from Linux and help to write SMBus compatible controller drivers. Beside integer type changes, the field `read` is replaced with a generic field `flags` and `chip` is renamed to `slave`. Patched with Coccinelle using the clumsy spatch below and some manual changes: * Nested struct initializers and one field access skipped by Coccinelle. * Removed assumption in the code that I2C_M_RD is 1. * In `i2c.h`, changed all occurences of `chip` to `slave`. @@ @@ -struct i2c_seg +struct i2c_msg @@ identifier msg; expression e; @@ ( struct i2c_msg msg = { - .read = 0, + .flags = 0, }; | struct i2c_msg msg = { - .read = 1, + .flags = I2C_M_RD, }; | struct i2c_msg msg = { - .chip = e, + .slave = e, }; ) @@ struct i2c_msg msg; statement S1, S2; @@ ( -if (msg.read) +if (msg.flags & I2C_M_RD) S1 else S2 | -if (msg.read) +if (msg.flags & I2C_M_RD) S1 ) @@ struct i2c_msg *msg; statement S1, S2; @@ ( -if (msg->read) +if (msg->flags & I2C_M_RD) S1 else S2 | -if (msg->read) +if (msg->flags & I2C_M_RD) S1 ) @@ struct i2c_msg msg; expression e; @@ ( -msg.read = 0; +msg.flags = 0; | -msg.read = 1; +msg.flags = I2C_M_RD; | -msg.read = e; +msg.flags = e ? I2C_M_RD : 0; | -!!(msg.read) +(msg.flags & I2C_M_RD) | -(msg.read) +(msg.flags & I2C_M_RD) ) @@ struct i2c_msg *msg; expression e; @@ ( -msg->read = 0; +msg->flags = 0; | -msg->read = 1; +msg->flags = I2C_M_RD; | -msg->read = e; +msg->flags = e ? I2C_M_RD : 0; | -!!(msg->read) +(msg->flags & I2C_M_RD) | -(msg->read) +(msg->flags & I2C_M_RD) ) @@ struct i2c_msg msg; @@ -msg.chip +msg.slave @@ struct i2c_msg *msg; expression e; @@ -msg[e].chip +msg[e].slave @ slave disable ptr_to_array @ struct i2c_msg *msg; @@ -msg->chip +msg->slave Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-09device/pci: untangle struct device and device_tAaron Durbin
This patch uses struct device explicitly for the ramstage functions as that's the actual type it's working on. Additionally, the declarations for types and functions are fully exposed so that compliation units don't have to guard certain functions from use because it's being compiled for multiple stages. Change-Id: I8db23ed400a59073e1e66522d020a5928f71f3a6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-01src/device: Add guards on all header filesMartin Roth
Change-Id: I8641f32ed2221f1d6e6dac884912251f64424f4d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-07-25src/device: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
This excludes some files in the device/oprom/x86emu folder which are mostly spaces, and which I felt should be handled separately. debug.c, decode.c, fpu.c, ops.c, ops2.c, & prim_ops.c Change-Id: I5c12d3fc942c9ad99bbe6e6e54db93e5a8402392 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-15device/pciexp_device.c: Terminate CLK PM message with newlineArthur Heymans
Change-Id: I746e2cc47a83cb04fd404851d3644b8341761022 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20544 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-28src/device: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28device/oprom/yabel: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Some of these can be changed from #if to if(), but that will happen in a follow-on commmit. Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-13device/pnp: remove struct io_infoSamuel Holland
The 'set' field was not used anywhere. Replace the struct with a simple integer representing the mask. initializer updates performed with: sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \ src/ec/*/*/ec.c sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \ src/ec/*/*/ec_lpc.c \ src/superio/*/*/superio.c \ src/superio/smsc/fdc37n972/fdc37n972.c \ src/superio/smsc/sio10n268/sio10n268.c \ src/superio/via/vt1211/vt1211.c src/ec/kontron/it8516e/ec.c was manually updated. The previous value for IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and had a zero bit in the middle of the mask. Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Myles Watson <mylesgw@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-09pciexp_device: Remove useless write on a read-only registerYouness Alaoui
The Role-Based Error Reporting is not a configurable field, it's a read only field in the Device Capability register. This code was old and comes from commit f6eb88ad but evidently is not useful in any way. The PCIe Specification [1] states that it's read-only and must always be set to 1. I have also done tests on purism/librem13 hardware, trying to change that value, without any success. [1]: PCI Express Base Specification Revision 3.0 Page 612 Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09pciexp_device: Prevent race condition with retrain linkYouness Alaoui
The PCIe specification[1] describes a race condition that can occur when using the Retrain Link bit in the Link Control Register. The race condition is avoided by checking the retrain link bit in the link status register and waiting until it is set to 0, before initiating a new link retraining. [1] PCI Express Base Specification Revision 3.0 Page 633 Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-09device/dram/ddr2.c: Fix is_registered_ddr2Arthur Heymans
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD specifications. Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Put gfx init methods into a `choice`Nico Huber
Provide all gfx init methods as a Kconfig `choice`. This elimates the option to select native gfx init along with running a Video BIOS. It's been only theoretically useful in one corner case: Hybrid graphics where only one controller is supported by native gfx init. Though I suppose in that case it's fair to assume that one would use SeaBIOS to run the VBIOS. For the case that we want the payload to initialize graphics or no pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the choice. If multiple options are available, the default is chosen as follows: * NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS, * VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS, * NATIVE_VGA_INIT, if we don't add a Video BIOS. As a side effect, libgfxinit is now an independent choice. Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 12:42:29 +0000