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Calculating the CRC of a SPD may be useful by itself, so split that
part of the code in a separate function.
Change-Id: I6c20d3db380551865126fd890e89de6b06359207
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4537
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I53a40d114aa2da76398c5b97443d4096809dcf36
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3730
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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MRS commands are used to tell the DRAM chip what timing and what
termination and drive strength to use, along with other parameters.
The MRS commands are defined by the DDR3 specification [1]. This
makes MRS commands hardware-independent.
MRS command creation is duplicated in various shapes and forms in any
chipset that does DDR3. This is an effort to create a generic MRS API
that can be used with any chipset.
This is used in the VX900 branch.
[1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf
Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3354
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Add convenience utilities for decoding DDR3 SPDs and printing the
information to the console. These have proven invaluable when writing the
VX900 memory initialization.
These are used in the VX900 branch
Information printed has the following format:
> SPD Data for DIMM 51
> Revision: 10
> Type : b
> Key : 2
> Banks : 8
> Capacity: 1 Gb
> Supported voltages: 1.5V
> SDRAM width : 8
> Bus extension : 0 bits
> Bus width : 64
> Optional features : DLL-Off_mode RZQ/7 RZQ/6
> Thermal features : ASR ext_temp_range
> Thermal sensor : no
> Standard SDRAM : no
> Row addr bits : 13
> Column addr bits : 10
> Number of ranks : 1
> DIMM Capacity : 1024 MB
> CAS latencies : 6 7 8 9
> tCKmin : 1.500 ns
> tAAmin : 13.125 ns
> tWRmin : 15.000 ns
> tRCDmin : 13.125 ns
> tRRDmin : 6.000 ns
> tRPmin : 13.125 ns
> tRASmin : 36.000 ns
> tRCmin : 49.125 ns
> tRFCmin : 110.000 ns
> tWTRmin : 7.500 ns
> tRTPmin : 7.500 ns
> tFAWmin : 30.000 ns
Change-Id: I30725a75caf74ac637db0a143344562bd9910466
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3267
Tested-by: build bot (Jenkins)
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