summaryrefslogtreecommitdiff
path: root/src/device/device_util.c
AgeCommit message (Collapse)Author
2019-07-19device/device_util.c: Correct format specifierJacob Garber
path.mmio.addr is a uintptr_t, which is an unsigned long. Change-Id: I5e43e0ab65cf59819abe1dde43143ff98e4553b0 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-13device/device_util: Fix encoding the USB device pathKarthikeyan Ramasubramanian
USB device id does not get included because of the logical OR operation. Fix encoding the USB device path. BUG=None BRANCH=None TEST=Boot to ChromeOS. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I79317da6d9c7cd177bd7bbbba1f1ccebe076930a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34245 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28device: Tidy up add_more_links()Jacob Garber
- Add documentation comment - Use 'unsigned int' to make checkpatch happy - Return early if no more links need to be added - Add error handling if malloc fails - Clean up whitespace Change-Id: I70976ee2539b058721d0ae3c15edf279253cd9b7 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229634 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33238 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28device,nb/amd: Deduplicate add_more_links()Jacob Garber
This function is duplicated in many AMD northbridge files, and all the definitions have started to diverge somewhat. This moves a single copy into device utils and deletes the rest. The function definition from nb/amd/amdfam10 was chosen to be kept, since it contains several fixes from commit 59d609217b (AMD fam10: Fix add_more_links) that the others don't have. For the ease of diffing, the checkpatch lints and other small cleanups will be done in a follow-up patch. Change-Id: I5ea73126092449db3f18e19ac0660439313072de Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33237 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07device: ignore NONE devices behind bridgePatrick Rudolph
Ignore NONE devices in dev_is_active_bridge that are commonly used to indicate hotplug capable ports. Tested on Lenovo T520: The empty ExpressCard Slot is no longer marked as active bridge. Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-17resources: introduce io_resource()Subrata Banik
This patch creates new resource function to perform allocation of IO resource, similar to mmio_resource() function does for MMIO. Change-Id: I3fdcabb14302537d6074bfd6a362690c06b66bb5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-11-19src: Add required space after "switch"Elyes HAOUAS
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-25device: Move find_dev_path() to device_const.cKyösti Mälkki
Change-Id: I8a27aa7157b5706623272ba9354ed8dff9b8184f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-25device: Move dev_find_path() to device_const.cNico Huber
Make it available early and use it in dev_find_next_pci_device(). Change-Id: I1d0ad07f37ea79dae2b9a592fcccba5e03fd86d5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-24device: Always build device_simple.c for less code duplicationNico Huber
Change-Id: Iec0a11d67d7641996f26b3a01352be762006ebb6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-22src/device: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. The function prototype for "struct device *add_cpu_device" is already correct and doesn't need to be fixed. Change-Id: I7bd8b93922f113bdaf7ba460acf6a7d62c4df013 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26067 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22device/device_util.c: Remove space after sizeofElyes HAOUAS
Change-Id: Ic8b77c78739badbea398053944484a55f715d03d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11devicetree: Add USB device typeDuncan Laurie
This commit adds support for describing USB ports in devicetree.cb. It allows a USB port location to be described in the tree with configuration information, and ACPI code to be generated that provides this information to the OS. A new scan_usb_bus() is added that will scan bridges for devices so a tree of ports and hubs can be created. The device address is computed with a 'port type' and a 'port id' which is flexible for SOC to handle depending on their specific USB setup and allows USB2 and USB3 ports to be described separately. For example a board may have devices on two ports, one with a USB2 device and one with a USB3 device, both of which are connected to an xHCI controller with a root hub: xHCI | RootHub | | USB2[0] USB3[2] device pci 14.0 on chip drivers/usb/acpi register "name" = ""Root Hub"" device usb 0.0 on chip drivers/usb/acpi register "name" = ""USB 2.0 Port 0"" device usb 2.0 on end end chip drivers/usb/acpi register "name" = ""USB 3.0 Port 2"" device usb 3.2 on end end end end end Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-02src/device: Fix discarded-qualifiers compilation issueSubrata Banik
coreboot build is broken due to CL: I6830a65bc9cea2907f4209bb97a53ccebcbf248d This patch ensures to build coreboot successfully. Change-Id: I4c9dfc9b19ce159ce1abcfbb287be4ce273cbaf1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-30device: constify some variablesLubomir Rintel
Change-Id: I6830a65bc9cea2907f4209bb97a53ccebcbf248d Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25873 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25sconfig: Add a new mmio resource typeJustin TerAvest
Add support for a mmio resource in the devicetree to allow memory-mapped IO addresses to be assigned to given values. AMD platforms perform a significant amount of configuration through these MMIO addresses, including I2C bus configuration. BUG=b:72121803 Change-Id: I5608721c22c1b229f527815b5f17fff3a080c3c8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15device: further untangle device_t from struct deviceAaron Durbin
This further allows compilation units to be re-used without having to add macro guards because of declarations not being around in the __SIMPLE_DEVICE__ case. These declarations are for functions that operate on struct device. struct device is a known type so just expose the functions using the correct type. Also, DEVTREE_CONST is empty while in ramstage so there's no reason to separate the declarations. Lastly, fix up device_util.c to use the proper types. It's only compiled in ramstage and it only operates on struct device. Change-Id: I306e0ad220cdab738cb727dda4a93bdec77c5521 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07device/device_util: Add string for DEVICE_PATH_NONEPatrick Rudolph
Add string for DEVICE_PATH_NONE in dev_path. The enum DEVICE_PATH_NONE can be translated to string and shouldn't be translated by "Unknown device path type: 0". Makes console output a lot prettier and readable. Note: DEVICE_PATH_NONE is used on dummy devices for hotpluggable slots. Change-Id: I08d471d8217f966e80daefe2d9971e357defde62 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-25src/device: Fix checkpatch warning: no spaces at the start of a lineMartin Roth
This excludes some files in the device/oprom/x86emu folder which are mostly spaces, and which I felt should be handled separately. debug.c, decode.c, fpu.c, ops.c, ops2.c, & prim_ops.c Change-Id: I5c12d3fc942c9ad99bbe6e6e54db93e5a8402392 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-02device/device_util: Add function to determine bridge statePatrick Rudolph
Add a method to get the state of a bridge device. Return true if at least one enabled device on the secondary bus is found. Useful to disable non hotplugable bridges without any devices attached. Change-Id: Ic8fe539d233031d4d177b03dd2c03edb5ab8c88d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-16device: Add a new "SPI" device typeFurquan Shaikh
Add support for a new "SPI" device type in the devicetree to bind a device on the SPI bus. Allow device to provide chip select number for the device as a parameter. Add spi_bus_operations with operation dev_to_bus which allows SoCs to define a translation method for converting "struct device" into a unique SPI bus number. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18340 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-02-06devtree: Drop unused parameter show_devs_tree() callKyösti Mälkki
Change-Id: I14c044bb32713ef4133bce8a8238a2bc200c4959 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18085 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-07src/device: Get device structure by path typeSubrata Banik
Add helper function to find a device by path type in the device tree. Change-Id: I8846f63bd2488788ea3c7ab5154e7cf431a252bc Credits-to: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Dhaval V Sharma <dhaval.v.sharma@intel.com> Reviewed-on: https://review.coreboot.org/17731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-07MMCONF_SUPPORT: Consolidate resource registrationKyösti Mälkki
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-16sconfig: Add a new generic device typeDuncan Laurie
Add support for a basic generic device in the devicetree to bind to a device that does not have a specific bus, but may need to be described in tables for the operating system. For instance some chips may have various GPIO connections that need described but do not fall under any other device. In order to support this export the basic 'scan_static_bus()' that can be used in a device_operations->scan_bus() method to scan for the generic devices. It has been possible to get a semi-generic device by using a fake PNP device, but that isn't really appropriate for many devices. Also Re-generate the shipped files for sconfig. Use flex 2.6.0 to avoid everything being rewritten. Clean up the local paths that leak into the generated configs. Change-Id: If45a5b18825bdb2cf1e4ba4297ee426cbd1678e3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-16sconfig: Add 10bit addressing mode to i2c device typeDuncan Laurie
Use the second token for an i2c device entry in devicetree.cb to indicate if it should use 10-bit addressing or 7-bit. The default if not provided is to use 7-bit addressing, but it can be changed to 10-bit addressing with the ".1" suffix. For example: chip drivers/i2c/generic device i2c 3a.1 on end end Change-Id: I1d81a7e154fbc040def4d99ad07966fac242a472 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/14788 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-18device: Add device path display supportLee Leahy
Add an optional routine to translate the device path types into a string for display. TEST=Build and run on Galileo Change-Id: Iea5d0a2430d9a8546105324e2beda0955210dca9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-03-09AMD fam10: Drop PCI_BUS_SEGN_BITSKyösti Mälkki
All boards in tree use 0. Looks like this is all work that was never completed and tested. We also have static setting sysconf.segbit=0 which would conflict with PCI_BUS_SEGN_BITS>0. Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support to cover over 255 buses. Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-15device/device_util.c: Add space after ellipse for better legibilityPaul Menzel
Currently the coreboot console log contains messages in the following form. Show all devs...Before device enumeration. […] Show all devs...After init. Add a space after the ellipse, so it’s better readable and it does not look like a newline is missing. Show all devs... Before device enumeration. […] Show all devs... After init. Change-Id: Ifa2a37b8d60c433c219df7533a79fced03b6271a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8424 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-09-29Remove stale char[] initialization causing unaligned memory accessMarcelo Povoa
This throws an alignment fault when run in ARMv8 Foundation model and seems unnecessary, so remove it. Change-Id: I2e3aa54502c292958ba44ff4e2e71c27653f2e1a Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186744 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 57510d553c56ca5dfb4765836ddb901744e29e20) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6974 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-11device/device_util.c: Fix wording in comment of `new_resource()`Paul Menzel
Change-Id: Ieb0d5de37870a359f3a7ea1543640e26f86c1684 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5952 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-12PCI: Guard pci.h with CONFIG_PCIKyösti Mälkki
Adding PCI functions for romstage in pci.h breaks ARMv7 build without this. Also fix two related includes to use pci_def.h instead. Change-Id: I5291eaf6ddf5a584f50af29cf791d2ca4d9caa71 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5199 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-09device_util: Make device in dev_find_slot_pnp u16.Vladimir Serbinenko
LDN is 8-bit but coreboot squeezes unrelated info: VLDN in this field. Increase to 16-bit to handle this. Change-Id: I97af1b32dcfaed84980fa3aa4c317dfab6fad6d8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5165 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-07device_util: Add dev_find_slot_pnp.Vladimir Serbinenko
Change-Id: I5223c54c8ddbc60a176e4d718730e99decc772a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5112 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-10Replace all occurences of sprintf with snprintfVladimir Serbinenko
THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-26Add function to encode device path into integerDuncan Laurie
This function will encode the device path into 3 bytes of a dword which can be saved for debug. It will be used by subsequent commit to store the current device into CMOS for debugging BIOS hangs. Change-Id: I3a5155ea53c8d280806e610a0f8998dbabe15f3c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58103 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4228 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-07-10device: Fix spellingMartin Roth
Change-Id: I53a40d114aa2da76398c5b97443d4096809dcf36 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3730 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-14sconfig: rename lapic_cluster -> cpu_clusterStefan Reinauer
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14sconfig: rename pci_domain -> domainStefan Reinauer
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Rename devices -> deviceStefan Reinauer
to match src/include/device Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1960 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 21:18:16 +0000