| Age | Commit message (Collapse) | Author |
|---|
|
Change-Id: Ib1b761fc417f1bb000f408d3bed5e8666963f51d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I22241427d1405de2e2eb2b3cfb029f3ce2c8dace
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/22585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
There is currently no case where a struct cpu_device_id instance needs
to be modified. Thus, declare all instances as const.
Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
When using microcode header and updating the header (due to a new
release of microcode during early development) the build system
doesn't detect the header change. This commit fixes this by adding
the appropriate dependency.
Change-Id: I4211a3e39f67da727ef7cddbbee6d8c4718dee4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This socket is used by 2nd and 3rd generation mobile SKUs from 2011-2013.
select SSE2 per review suggestion
Change-Id: I9306a3364ae15530c99ca3379cfa2057c5879681
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Tested on Lenovo Thinkpad T500.
Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If the SSE2 Kconfig option is selected also select SSE.
Change-Id: I6ccba57d5ae13b8066f2f744cd739282ffd4fe73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
coreboot has a lapicid() function, so use it.
Change-Id: I7f536c229f271674c34d722b5db96ce665b720f1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This was moved out of northbridge/gm45 but was accidentally? commented
out in c5d972d073c "Move select UDELAY_LAPIC from nb/gm45/Kconfig to
cpu/model_1067x/Kconfig"
The intel eagleheights mainboard also uses UDELAY_LAPIC with this
change and is untested.
Change-Id: I70e51fa50935baf187cef60f2e636251b40d6475
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22172
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I3ef810ee59492c8d7147934e61523c8fd223863b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The code used to split up ranges >64MiB into 64MiB-aligned and
unaligned parts. However in its current state the next step,
calc_var_mtrr_range(), results in the same allocation, no mat-
ter if we split the range up before. So just drop the split-up.
Change-Id: I5481fbf3168cdf789879064077b63bbfcaf122c9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.
Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix boot regression after commit
d4955f0 AGESA: Move API interface under drivers/
Boards were left without cache-as-ram setup code
and appeared completely dead.
Change-Id: I53a58b817310e91566db3fd660a2c41556f3df5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
|
|
Ensure the stack is properly aligned in the SIPI handler. This
avoids an exception when an aligned instruction is performed on
stack data.
BUG=b:66003093
TEST=boot kahlee built with gcc 6.3
Change-Id: Ibdd8242494c6a2bc0c6ead7ac98be55149219d7c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I5e2affe337f7e61ca79530b3a77af963e8692ff1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.
Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Except for family15, all AGESA boards have moved
away from AGESA_LEGACY_WRAPPER, thus they all
have POSTCAR_STAGE now.
AGESA family15 boards remain at AGESA_LEGACY=y, but
those boards have per-board romstage.c files and
are not touched here.
Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move all boards that have moved away from AGESA_LEGACY_WRAPPER
or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE.
We use POSTCAR_STAGE as a conditional in CAR teardown to tell
our MTRR setup is prepared such that invalidation without
writeback is a valid operation.
Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
clang wont compile `cmp` asm opcode because it's ambiguous,
use the correct op suffix `cmpl`
Change-Id: I82da5a9065b382e182dc7d502c7dca2fc717543b
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Because cpu/intel/car/romstage.c assumes a 8KiB stack size
when setting up stack guards, and all Slot 1 compatible
CPUs have enough L1 cache available for the increase.
Adjust DCACHE_RAM_BASE to match.
Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz
Tualeron. The latter actually requires this patch to boot
successfully.
Change-Id: I5b440e7be4f3149378db88872872012c92049c20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE
and CONFIG_DCACHE_RAM_SIZE for consistency.
Do not set %ebp before and switch directly to stack returned by
romstage_main().
Remove an unneeded 4-byte gap in CAR stack.
The caching strategy for flash XIP area should be WRPROT.
Clarify the various comments in the file on the logic.
Together they lay the groundwork for bringing EARLY_CBMEM_INIT to
intel/slot_1 boards.
Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21503
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove CAR testing code currently blocked out by #if. Newer CAR code
don't even do it anymore.
Change-Id: I2d53b4e7a244824c7aa2c0f597ed91e17f6cc668
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21502
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove Hyperthreading related code that was missing setup of SIPI
vector and did not work.
Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21375
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The original purpose of adjust_cpu_apic_entry() was to set
up an APIC map. That map was effectively only used for mapping
*default* APIC id to CPU number in the SMM handler. The normal
AP startup path didn't need this mapping because it was whoever
won the race got the next cpu number. Instead of statically
calculating (and wrong) just initialize the default APIC id
map when the APs come online. Once the APs are online the SMM
handler is loaded and the mapping is utilized.
Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved
from romstage to ramstage, heapamanager in romstage
is no longer needed.
Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Followup removes inlined acpi_is_wakeup_s3() from PRE_RAM,
and new implementation depends of CAR_GLOBAL.
Change-Id: Iea1c5ab2175f8d496baa09bd6137cacc912df2cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Make sure guard placement is above CAR region.
Change-Id: I780cdc0b2a549e7ac4b23b0870619f5648a644e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21313
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fixed ACPI S3 support will use POSTCAR_STAGE and no longer
uses the code removed here.
Change-Id: I180adaaccce5f0caabcdcd67f3000a21295b0ecf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Iffa6cf495b4649f73a1095732509f195ac828248
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
It's arch specific, so no need to pollute non-x86 with it.
Change-Id: I99ec76d591789db186e8a33774565e5a04fc4e47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21392
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The addr32 prefix is required by binutils, because even when
given an explicit address which is greater than 64KiB, it will
throw a warning about truncation, and stupidly emit the opcode
with a 16-bit addressing mode and the wrong address.
However, in the case of LLVM, this doesn't happen, and is happy
to just use 32-bit addressing whenever it may require it. This
means that LLVM never really needs an explicit addr32 prefix to
use 32-bit addressing in 16-bit mode.
Change-Id: Ia160d3f7da6653ea24c8229dc26f265e5f15aabb
Also-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Change-Id: I18c62ad034249c5ad14e5d5e708b4f0d4bcbf400
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
LLVM AS doesn't support as much GNU junk extensions, data16/32
is almost never needed in truth if we just use the correct op
suffix. So do that here, fixes clang/llvm builds with the
integrated-as toggled on.
Change-Id: I6095d03d0289b418a49a10f135de5eb0e117cae0
Also-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Never selected in our tree.
Change-Id: I5065903ebf74d281ecccaf53e0cc9fa24317e1cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Never selected in our tree. The vendorcode source
for fam15 also includes fam10 support if required.
Change-Id: Ifff328ecdd8afa988f844b6fd631818b51bd5b5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.
Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Return to empty stack before making the switch.
Change-Id: I6d6f633933fac5bc08d9542c371715f737fb42cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
|
|
Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20573
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
|
|
Avoid conflicting disable_cache_as_ram() declaration and tidy
up include for inlined function.
Change-Id: Iba77c711f5eb023566b7d8ba148583948661bc99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Fail at build-time if one of the following happens:
Platform includes SMI handler setup function smm_init()
in the build when configuration has HAVE_SMI_HANDLER=n.
Platform does not implement smm_init_completion() when
HAVE_SMI_HANDLER=y.
Change-Id: I7d61c155d2b7c2d71987980db4c25d520452dabf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Fix low memory corruption on S3 resume path.
Affected platforms were sandy/ivybridge.
Change-Id: I7379e7396b61ee4dc2438276d530feffaa1bc8f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21100
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
SMM relocation code overwrite low memory owned by OS.
Change-Id: Ifa3d28bed3d3db65b0707bde62ae2b424a231f1a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19405
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I7c138758707f87c0d7a827b6887c7752d3714cde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I2d6fdfd0465fe5f558daa04c6f980f7226596b55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Due to low-memory corruptions S3 support has now been
(at least temporarily) removed from AGESA platfroms.
Should we bring it back one day, CAR teardown on S3 path
will happen with an empty stack so ugly backup/recovery
of the stack will no longer be used.
If S3 feature is brought back, resume path code for FCH
will also see partial rewrite and agesawrapper.c file
will not be part of that.
Change-Id: Ib38c04d0e74f600e0b719940d5e2530f4c726cfd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
|
struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
|
struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
|
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
|
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
|
-msg.read = 1;
+msg.flags = I2C_M_RD;
|
-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
|
-!!(msg.read)
+(msg.flags & I2C_M_RD)
|
-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
|
-msg->read = 1;
+msg->flags = I2C_M_RD;
|
-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
|
-!!(msg->read)
+(msg->flags & I2C_M_RD)
|
-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Also moves postcar stack to CBMEM.
Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Experiments on f14 f15tn and 16kb suggest that TSC
counter value shifts at end of raminit. To account
for this all previously stored values in timestamp
table are also divided by 4.
Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Boards without AGESA_LEGACY_WRAPPER gain EARLY_CBMEM_INIT.
This does not apply to family12 and family14 just yet, as
they do invalidate without write-back on CAR teardown.
Change-Id: I008356efa2bc3df0ed1f0720e225ecc7e9995127
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In AGESA specification AmdInitEnv() is to be called once
host memory allocator has started. In coreboot context this
could mean either availability of CBMEM or malloc heap.
As for AmdS3LateRestore(), there is no requirement to have
it run as part of the romstage either.
Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I13d8df330db925b2eced7c123ca9926fb259646d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20621
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Change-Id: I7c3af493b9189bb75a58eb322646694b5a712745
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix over 80 character line warnings, unncessary braces for single
statement blocks warnings, include space before and after =, <, >
warnings, spaces after open parantheses warnings
Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/19987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Fix remaining space prohibited between function name and open
parenthesis, line over 80 characters, unnecessary braces for single
statement blocks, space required before open brace errors and warnings
in subdirectories of src/cpu/amd/pi
Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Never reached and actual code was already wiped out.
Change-Id: Ic17cbc56e83d23e228e23578357843ac9cd77eda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20623
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Iabdaaaee49e8c5cead304cda66412aa36a2ffd19
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This chipset was just added and had a few places that needed to be
fixed.
Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20684
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
At a process _start, the stack is expected to be aligned to a
16-byte boundary. Upon entry to any function the stack frame
must have the end of any arguments also aligned. In other words
the value of %esp+4 or %rsp+8 is always a multiple of 16 (1).
Align the stack down inside _secondary_start and preserve proper
alignment for the call to secondary_cpu_init.
Although 4-byte alignment is the minimum requirement for i386,
some AMD platforms use SSE instructions which expect 16-byte.
1) http://wiki.osdev.org/System_V_ABI
See "Initial Stack and Register State" and "The Stack Frame"
in the supplements.
BUG=chrome-os-partner:62841664
Change-Id: I72b7a474013e5caf67aedfabeb8d8d2553499b73
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Essentially squashes following commits from AGESA side.
45ff9cb AGESA: Reduce typecasting in heapmanager calls
bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly
4240277 AGESA: Adjust heap location for S3 resume path
424c639 AGESA: Refactor S3 support functions
50e6daf AGESA: Log heap initialisation
da74041 AGESA: Move heap allocator declarations
c74b53f AGESA: Reduce SPI use by 24kB for S3 support
b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts
f728408 AGESA: Split S3 backup in CBMEM
82fbda7 AGESA: Use same HeapManager for all BiosCallOuts
Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change register preservations and fix comments about register
usage accordingly. Do this to avoid use of %mm0-2 registers inside
macros defined in gcccar.inc, as future implementation of
C_BOOTBLOCK_ENVIRONMENT will use them as well.
Adjust caller side accordingly.
Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Change-Id: I370285aa52776170a32b6dd36c0eef74eea9400c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
These sources are no longer part of build-tests and transition
to soc/ appears to be completed.
Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Fix undefined behavior found by clang's -Wshift-sign-overflow. Left
shifting an int where the right operand is >= the width of the type
is undefined. Add UL suffix since it's safe for unsigned types.
Change-Id: Ieacf83d052bf4abfad639ef8e592bd8de17d16e6
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that's not aligned to the size of access is undefined behavior.
Remove unnecessary memset().
Change-Id: I1362a3eb8c97f5c7e848d75f8d1a219968a7ef9e
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I9f4155285529ec28e826637a61436478f648704c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Needed to generate cpu entries.
Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
If SSE instructions are enabled in the build assume the SMM
modules are compiled with SSE instructions. As such enable
the SSE instructions in SMM mode by setting up the cr4 register.
In addition, provide a place to save and restore the SSE state
in both the relocation handler and permanent handler.
Change-Id: Ifa16876b57544919fde88fba5b8f18e4ca286841
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20244
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Code checked manually
Change-Id: I92f0b5d47c60c259171c4db90fb5003f4eb8580b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
With the do while loop, it can be avoided do use an infinite loop with a
break condition inside.
Change-Id: I030f6782ad618b55112a2f0bac8dda08b497a9f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Use the existing macros for CR0 to set the flags in the
SIPI vector code.
Change-Id: Iad231b7611b613512fd000a7013175e91542ac10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Use the existing macros for CR0 to set the flags in the
SMM stub.
Change-Id: I0f02fd6b0c14cee35ec33be2cac51057d18b82c0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20242
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
For sizes and dimensions use size_t. For pointer casts
use uintptr_t. Also, use the ALIGN_UP macro instead of
open coding the operation.
Change-Id: Id28968e60e51f46662c37249277454998afd5c0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20241
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Use define for SSA base address.
Move EM64T area to 0x7c00 and add reserved area of size 0x100,
as there's no indication that the address 0x7d00 exists on any
platform.
No functional change.
Change-Id: I38c405c8977f5dd571e0da3a44fcad4738b696b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The previous implementation was using a for loop. By it's
very definition the last statement in the for loop declaration
is done at the end of the loop. Therefore, if the conditional for
breaking out of the for loop because of a timeout would always
see a value of 0 for the number of APs accepted. Correct this
by changing to a while loop with an explicit timeout condition
at the end of the loop.
Change-Id: I503953c46c2a65f7e264ed49c94c0a46d6c41c57
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
If an MTRR solution exceeds the number of available MTRRs
don't attempt to commit the result. It will just GP fault
with the MSR write to an invalid MSR address.
Change-Id: I5c4912d5244526544c299c3953bca1bf884b34d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20163
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
AMD_FAM10H code enables early cbmem by default.
Change-Id: Ifad007f6604bb612d544cf1387938a8fef1cceb4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Fix line over 80 characters, spaces required around comparisons,space
required after close brace '}', comma ',', semicolon ';', space
prohibited after ')' errors and warnings
Change-Id: I5585f55a606d4f2149b17ac92cbdd832f242630e
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Fix line over 80 characters, unnecessary braces for single statement
blocks, spaces before close parantheses errors and warnings.
Signed-off-by: Evelyn Huang <evhuang@google.com>
Change-Id: I31b1932a2c1e401e56751e0c790bcc6287fb550d
Reviewed-on: https://review.coreboot.org/20097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Fix space prohibited between function name and open parenthesis, line
over 80 characters, unnecessary braces for single statement blocks,
space required before open brace errors and warnings
Change-Id: I66f1a8640ec5c9d8a1dd039088598f40e8d30f95
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Id88455f2c7c28e0b298675b9af2a39361759a34a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19120
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fix line over 80 characters warnings and space after function name
warning.
Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/19988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
