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2022-11-03Revert "cpu/x86/mp_init.c: Set a bogus initial lapic_id"Felix Held
This reverts commit 1bb9786da30e ("cpu/x86/mp_init.c: Set a bogus initial lapic_id"), since it breaks MP init on amd/mandolin: [INFO ] CPU #0 initialized [INFO ] Initializing CPU #3 [INFO ] Initializing CPU #1 [INFO ] Initializing CPU #2 [EMERG] CPU: missing CPU device structureCPU: vendor AMD device 810f81 [DEBUG] CPU: family 17, model 18, stepping 01 [DEBUG] microcode: patch id to apply = 0x08108109 [INFO ] microcode: being updated to patch id = 0x08108109 succeeded [INFO ] CPU #1 initialized [ERROR] MP record 3 timeout. [INFO ] bsp_do_flight_plan done after 1206 msecs. [ERROR] MP initialization failure. [EMERG] mp_init_with_smm failed. Halting. TEST=The board boots again with the revert applied Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic1cae88f7345f9ff79e8f6e574521095b57c8cb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69186 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-03cpu/x86/mp_init.c: Handle failed init_bsp()Arthur Heymans
Bail out of mp_init if this function fails. Change-Id: I7be5d6c32458ba98f4f8c5c9340790ff989c91e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69109 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03cpu/x86/mp_init.c: Set a bogus initial lapic_idArthur Heymans
This makes it easier to catch errors later if the ap_init code fails to properly set things up. Change-Id: I938faf042bfa4fe1fc39e78ab740c9b210bc105c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69108 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-28cpu/x86/mp_init.c: Use linked list data structuresArthur Heymans
There is no need to keep track of device structures separately. Change-Id: Ie728110fc8c60fec94ae4bedf74e17740cf78f67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-28cpu/intel/common: Fix typecasting issueSridhar Siricilla
The patch fixes the typecasting issue, that is conversion from 'int' to 'unsigned long long int'. This changes value from '0x8000 0000' to '0xFFFF FFFF 8000 0000'. During unit testing, the argument is getting changed to an unexpected number which is resulting to an exception when IA32_HWP_REQUEST MSR is updated. In this update, the MSR's reserved bits are getting updated, so this causes exception. TEST= Verified the code on the Gimble. No exception is seen after the fix. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I35d382c792b9df260381b7696f3bbff43d6c4dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-27cpu/x86/mp_init: adjust timeout for final SIPIJonathan Zhang
Adjust timeout for final SIPI to satisfy some to-be-launched server processors. Add a spew print to display how long it takes for the APs to be ready. This is intended to facilitate only troubleshooting and trend analysis. Change-Id: Id958f18bdcb34d76df8aa443161123252524328e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68262 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-27mb/lenovo/haswell: Enable VBOOT_VBNV_FLASHYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for Haswell. Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for CPU_INTEL_HASWELL (see [2]). However, there seems to be no particular reason on those platforms. Flashconsole works on Broadwell, at least, and it writes to flash as early as bootblock. Therefore, remove BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES, so that VBOOT_VBNV_FLASH can be enabled. [1] https://issuetracker.google.com/issues/235293589 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 (CB:45740) drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config BUG=b:235293589 TEST=./util/abuild/abuild -t LENOVO_THINKPAD_T440P -a (with VBOOT) Change-Id: If1430ffd6115a0bc151cbe0632cda7fc5f6c26a6 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-26cpu/x86: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I01c6651079333686cb0eb68e89e56d7907868124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26cpu/intel: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie760711916c49d275ca49d94b9597fd24b5e7628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NBArthur Heymans
Pre-sandy bridge hardware is likely affected by the sinkhole vulnerability. Intel sandy bridge and newer has hardware mitigations against this attack according to https://github.com/xoreaxeaxeax/sinkhole. Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-12cpu/x86/64bit: Fix building with -jxArthur Heymans
config.h is a dependency so add it. Change-Id: Iac87039dd43aa75d49766b9a239fbd841ca6850c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06cpu/x86/pae/pgtbl.c: Clean up includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0ab39ff20b0fb59026063e064e20ce901c2985fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/intel/common/fsb.c: Sorte includes and add <stdint.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9b85836ac21da5b885a97f05e3973fb23a052fd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/intel/car/romstage.c: Clean up includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I84639389ac1066468b82bb13d684e5423b909fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/x86/smm/smm_module_loader.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I36c54e62797e67c1732f8deaf8843daf35610e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h>Elyes Haouas
Remove <stdint.h>, <stddef.h> and add <stdbool.h>. All of them are included through <types.h>. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If5296988c68302896e3676d7b80d0f133d5d4264 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-29treewide: use is_enabled_cpu() on cycles over device listFabio Aiuto
use is_enabled_cpu() on cycles over device list to check whether the current device is enabled cpu. TEST: compile test and qemu run successfully with coreinfo payload Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-24cpu/x86/smm/smihandler: use lapicid()Felix Held
Replace nodeid() function in cpu/x86/smm/smihandler.c with calling lapicid() from include/cpu/x86/lapic.h. TEST=Timeless build for lenovo/g505s which includes this file in the build results in identical firmware image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I336ca9888e24e4d6f10a81cc4f3760c9d7c8f4bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/67777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-24cpu/x86/mp_init: drop unused MAX_APIC_IDS defineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I599e26a40ab584232614440612e95c91a698df27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-24include/cpu/x86/mtrr: define NUM_FIXED_MTRRS once in mtrr.hFelix Held
Instead of defining NUM_FIXED_MTRRS in both cpu/x86/mp_init.h and cpu/x86/mtrr/mtrr.c in two different ways that will evaluate to the same value, define it once in include/cpu/x86/mtrr.h which is included in both C files. TEST=Timeless build for amd/mandolin results in identical firmware image Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71cec61e22f5ce76baef21344c7427be29f193f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-23cpu/x86/smm/smihandler: use existing LAPIC ID register definitionFelix Held
Instead of redefining the register address in smihandler.c, use the existing definitions from include/cpu/x86/lapic_def.h. TEST=Timeless build for lenovo/g505s which includes this file in the build results in identical firmware image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id22f9b5ce53c7bced6bbcc3f5026d4c793b34f78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67776 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22cpu/x86/smm/smm_module_loader.c: Fix STM setupEugene Myers
CB:63475 inadvertently disabled the STM by moving its load point off of the MSEG boundry, which is a hardware requirement. In addition, the BIOS resource list cannot be located within the MSEG. This patch fixes the issue by moving the STM load point to the MSEG boundry and placing the bios resource list just below the MSEG where the STM setup functions can find it. Fixes: commit 5747f6c (cpu/x86/smm_module_loader.c Rewrite setup) Signed-off-by: Eugene Myers <edmyers@tycho.nsa.gov> Change-Id: I7359939063bb1a172fcb701551c099edebfbedd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67665 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-20cpu/intel/haswell: Update Broadwell ULT µcode updatesAngel Pons
The µcode updates for Broadwell come from coreboot's blobs submodule and have not been updated in at least 7 years. Use the µcode updates available in the intel-microcode submodule. This change forgoes some µcode updates for old Broadwell ULT/ULX steppings with CPUID 0x306d2 and 0x306d3, as well as an old µcode update for Haswell ULT/ULX CPUs with CPUID 0x40651 in favor of a newer intel-microcode revision that was already being used: when the µcode updates are concatenated into one file, the newer µcode update revision would be placed before the older revision, so the latter would never be used. Change-Id: I67f8a58552bd211095c183e6f7a219d60e3be162 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-20cpu/intel/haswell: Hook up Crystal Well µcode updatesAngel Pons
Commit 27126f135dad3c0e2f91394e7088b2ff50220146 (cpu/intel/haswell: add Crystal Well CPU IDs) introduced new Haswell CPUIDs but did not include any µcode updates for them. It is unknown how this could have worked as the initial µcode inside the CPU can be quite unstable. Intel CPUs with support for FIT (Firmware Interface Table) can have their µcode updated before the x86 reset vector is executed. The µcode updates for Crystal Well CPUID 0x40661 can be found inside the intel-microcode submodule. There are no publicly available µcode updates for Crystal Well CPUID 0x40660 as it is a pre-production stepping, which is not meant to be used anymore. Hook up the available µcode updates for Crystal Well CPUs. Change-Id: If5264f333e681171a2ca4a68be155ffd40a1043b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-20cpu/intel/haswell: Do not include useless µcode updatesAngel Pons
There are two types of Haswell/Broadwell platforms: Trad(itional) with separate CPU and PCH packages, and ULT/ULX where the CPU and PCH share one package. Mainboards can specify which platform type they are using the `INTEL_LYNXPOINT_LP` Kconfig option. There are so many differences between Trad and ULT/ULX that it's not worth doing runtime detection. The CPUIDs are different for Trad and ULT/ULX platforms, and so are the µcode updates. So, including Trad µcode updates in a coreboot image for an ULT/ULX mainboard makes no sense, and vice versa. Adapt the Makefile so that only relevant µcode updates are added. Also, add a few comments to indicate which updates correspond to which CPUs. TEST=Run binwalk on coreboot.rom to verify included µcode updates for: - Asrock B85M Pro4 (Haswell Trad) - HP Folio 9480M (Haswell ULT/ULX) - Purism Librem BDW (Broadwell ULT/ULX) Change-Id: I6dc9e94ce9fede15cbcbe6be577c48c197a9212a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-15soc/amd: Do SMM relocation via MSRArthur Heymans
AMD CPUs have a convenient MSR that allows to set the SMBASE in the save state without ever entering SMM (e.g. at the default 0x30000 address). This has been a feature in all AMD CPUs since at least AMD K8. This allows to do relocation in parallel in ramstage and without setting up a relocation handler, which likely results in a speedup. The more cores the higher the speedup as relocation was happening sequentially. On a 4 core AMD picasso system this results in 33ms boot speedup. TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM is correctly relocated with the BSP correctly entering the smihandler. Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15cpu/intel/haswell: Allow up to six microcodes in the FIT tableJeremy Compostella
Haswell and Broadwell platforms usually stitch six microcode patches. It has worked so far with the default value of four thanks a bug which is being fixed by `util/ifittool: Error out if microcodes do not fit the FIT table' commit. BUG=b:245380705 TEST=Jenkins build without failing on the FIT table size Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I23bf79a3e8918499f6c51e6ef829312d5872181a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-14soc/amd/common: Add common function to get cpu countArthur Heymans
This is the same for all supported AMD hardware. Change-Id: Ic6b954308dbb4c5a2050f1eb8f15acb41d0b81bd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67617 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-25arch/x86: Fix MAX_CPUS check proper for late X2APIC configSubrata Banik
The X2APIC_LATE_WORKAROUND kconfig allows bringing APs in XAPIC mode initially hence, it won't work if LAPIC ID is > 0xff. This patch ensures the MAX_CPUS logic is appropriate while selecting X2APIC_LATE_WORKAROUND kconfig from SoC. BUG=b:219061518, b:219053812 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I466e6cc568024a9dea80af21e0ebf3572e74a1f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-20treewide: Remove unused <cpu/x86/mtrr.h>Elyes Haouas
Change-Id: Ib852d0b2cf4d3cbdf7475bd5493bf2e585a5894a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-19cpu/amd: Reformat codeElyes Haouas
Most of these changes are suggested by clang-format(13.0-54) tool on Debian testing. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie4fe0e872e94f38079945970848fefd153ab7cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-18cpu/x86: Allow SoC to select the `X2APIC_LATE_WORKAROUND`Subrata Banik
Intel Meteor Lake SoC expects to select late x2APIC enablement where AP bring up will use xAPIC and later x2APIC gets enabled using CPU init. This patch provides an option where SoC code choose the correct LAPIC access mode using choice selection. BUG=b:219061518, b:219053812 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b50a0f5e39a95c25cd2c72219d2b402550a6fad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65786 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-18arch/x86: Add X2APIC_LATE_WORKAROUNDSubrata Banik
Add option to do AP bringup with LAPICs in XAPIC mode and switch to X2APIC later in CPU init. Change-Id: I94c9daa3bc7173628f84094a3d5ca59e699ad334 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65766 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-17cpu/amd/pi/00730F01/update_microcode.c: Fix some white spaces issuesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I420b9506381758c63b88435a915672507e8bc465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-17cpu: Get rid of unnecessary blank line {before,after} barceElyes HAOUAS
Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-14arch/x86: Mark prepare_and_run_postcar noreturnArthur Heymans
This moves the die() statement to a common place. Change-Id: I24c9f00bfee169b4ca57b469c089188ec62ddada Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-13cpu/amd: Add common helpers for TSEG and SMMArthur Heymans
Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-13cpu/x86/mp_init: retype do_smm element in mp_state struct to boolFelix Held
The do_smm struct element in the mp_state struct was an int even though it only had two possible states, so change it to bool to make this more obvious. Also change the return type of is_smm_enabled from int to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d2d95f0497649d67565243d14a5ab9c9cdda412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-26intel/microcode: Change log type from BIOS_ERR to BIOS_WARNINGSubrata Banik
This patch changes the serial message type to BIOS_WARNING as sometimes it may raise a wrong signal when microcode resides inside other part of the IFWI instead /CBFS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I714bf74a91c2d783982c5e5ca76a70deed872473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65316 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22microcode: Add error msg in case `intel_microcode_find()` return NULLSubrata Banik
This patch adds an error msg if intel_microcode_find() is unable to find a microcode for the CPU SKU. TEST=Able to see the error msg in coreboot serial log in case packed with wrong microcode binary. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib4865575a44d2c8c6c3a20c2823a546d8f261e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65285 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22cpu/intel/microcode: Create helper function to load microcode patchSubrata Banik
This patch refactors the microcode loading and reloading API with a helper function that perform the actual MSR write operation after taking the microcode pointer from the caller function. Also, convert the microcode loading failure msg type from `BIOS_INFO` to `BIOS_ERR` to catch the error in proper. TEST=Able to perform microcode loading on google/kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9a7cdc2d2c9211f1e0c7921015126f7a1be87761 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65249 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22cpu/intel/microcode: Have API to re-load microcode patchSubrata Banik
This patch introduces a newer API to reload the microcode patch when SoC selects RELOAD_MICROCODE_PATCH config. Expected to call this API being independent of CPU MP Init regular flow hence, doesn't regress the boot time. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If480e44b88d04e5cb25d7104961b70f7be041a23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-17cpu/intel/microcode: Fix `device enumeration` boot regressionSubrata Banik
Prior commit hash 0310d34c2 (cpu/intel/microcode: Have provision to re-load microcode patch) introduces an option to reload the microcode based on SoC selecting RELOAD_MICROCODE_PATCH config. This patch might potentially introduce a boot time regression (~30ms) when RELOAD_MICROCODE_PATCH kconfig is enabled as all cores might end up reloading the microcode without the proper need. Note: RELOAD_MICROCODE_PATCH kconfig is not yet selected by any SoC hence, it doesn't impact any coreboot project. The idea is reloading microcode depends on specific use case (for example: Skip FSP doing MP Init from Alder Lake onwards) hence, a follow up patch will create a newer API to allow reloading of microcode when RELOAD_MICROCODE_PATCH config is enabled. BUG=b:233199592 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie320153d25cefe153fc8a67db447384f1f20f31f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-17cpu/Makefile.inc: Fix rebuilding a new targetArthur Heymans
When switching to different board, 'make clean' needs to happen because not everything gets properly regenerated. Microcode updates are among those. You could end up with the microcode updates from the previous build which can be incorrect. Adding $(DOTCONFIG) as a dependency which gets updated when you change something in Kconfig fixes this. TESTED: swap between boards that use different microcode and see that the size changes. Change-Id: Id1edecc28d492838904e3659f1fe8c9df0a69134 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65148 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-06-15cpu/x86/smm/smm_module_loader.c: Fix formatted printElyes Haouas
This fixes following errors when building GA-945GCM-S2L with clang 14.0.5. CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:180:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_offset(&cpus[i].stub_code), i); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:184:20: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] __func__, region_offset(&cpus[0].stub_code), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:185:10: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_offset(&cpus[i].stub_code), size); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/cpu/x86/smm/smm_module_loader.c:349:52: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] printk(BIOS_DEBUG, "%-12s [0x%lx-0x%lx]\n", name, region_offset(&region), ~~~ ^~~~~~~~~~~~~~~~~~~~~~ %zx src/cpu/x86/smm/smm_module_loader.c:350:9: error: format specifies type 'unsigned long' but the argument has type 'size_t' (aka 'unsigned int') [-Werror,-Wformat] region_end(&region)); Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I59f20aacf91cb50fb194a84082a643b34c6c1ae5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65154 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-07arch/x86: Add a common romstage entryArthur Heymans
It might be possible to have this used for more than x86, but that will be for a later commit. Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-07cpu/intel/microcode: Have provision to re-load microcode patchSubrata Banik
This patch provides an option to reload the microcode patch a.k.a second microcode patch if SoC selects the required RELOAD_MICROCODE_PATCH config. There is a new feature requirement starting with ADL to re-load the microcode patch as per new Mcheck initialization flow. BUG=b:233199592 TEST=Build and boot google/taeko to ChromeOS. Able to re-load microcode patch as below: [INFO ] microcode: Re-load microcode patch [INFO ] microcode: updated to revision 0x41b date=2022-03-08 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a3c29b3c25fccd31280a2a5a8d4fb22a6cf53bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/64833 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-06-06cpu/amd/agesa: Use common MRC_CACHE code to save S3 dataArthur Heymans
Use the common code to save data for fast boot or S3 resume. An notable improvement that comes with this, is that the same 4K page is not rewritten all the time. This prolongs the hardware's life. TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44295 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-06-06drivers/amd/agesa: Don't save regular boot MTRR to flashArthur Heymans
Save the regular boot MTRRs that are restored on the S3 path during the CPU init in cbmem instead of storing them to the SPI flash. This was probably done because historically this code run with late cbmem init (in ramstage). TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: Ia58e7cd1afb785ba0c379ba75ef6090b56cb9dc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44294 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-06-03cpu/x86/smm_module_loader: Use struct region in cpu mapArthur Heymans
We use a region later on so we might as well use a region from the start. This simplifies the computations too. Change-Id: Iffa36ccb89c36401d3856b24364216e83ca35f91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64609 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-03cpu/x86/smm: Use struct region to check overlapping sectionsArthur Heymans
This allows for some runtime checks on all SMM elements and removes the need for manual checks. We can drop completely separate codepaths on SMM_TSEG & SMM_ASEG as the only difference is where permanent handler gets placed. TESTED on prodrive/hermes and qemu with SSM_ASEG with 4 cores & SMM_TSEG with 128 cores. This code figured out quite some problems with overlapping regions so I think this is the right approach. Change-Id: Ib7e2e3ae16c223ecfd8d5bce6ff6c17c53496925 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63602 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-06-03cpu/x86/smm_module_loader: Update loggingArthur Heymans
Some logging is superfluous and logging that code is being copied is 'SPEW' level. Change-Id: I84d49a394cc53d78f1e1d3936502ac16810daf9f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-02cpu/x86/mp_init.c: Prolong delay on synchronous APIArthur Heymans
When each AP needs to do a lot of printing 1 sec is not enough. Change-Id: I00f0a49bf60f3915547924c34a62dd0044b0c918 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64828 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
2022-06-02cpu/intel/model_fxx: Select SSE2Arthur Heymans
Starting from Intel Pentium 4, cpus featured SSE2. This will be used in the follow-up patches to determine whether to use mfence as this instruction was introduced with the SSE2 feature set. Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-02cpu/x86/smm_module_loader: Drop superfluous checksArthur Heymans
Checking if the stack encroaches on the entry points is done in other parts of the code. Change-Id: I275d5dda9c69cc89608450ae27dd5dbd581e3595 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-01cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verificationJulius Werner
The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier among CBFS files because it gets manipulated by a separate utility (ifittool) after cbfstool has already added it to the image. This will break file hashes created for CBFS verification. This is not actually a problem when booting, since coreboot never actually loads the FIT from CBFS -- instead, it's only in the image for use by platform-specific mechanisms that run before coreboot's bootblock. But having an invalid file hash in the CBFS image is confusing when you want to verify that the image is correctly built for verification. This patch adds a new CBFS file type "intel_fit" which is only used for the intel_fit (and intel_fit_ts, if applicable) file containing the FIT. cbfstool will avoid generating and verifying file hashes for this type, like it already does for the "bootblock" and "cbfs header" types. (Note that this means that any attempt to use the CBFS API to actually access this file from coreboot will result in a verification error when CBFS verification is enabled.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEGArthur Heymans
Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-01Revert "cpu/x86/mtrr: Make useful MTRR functions available for all boot stages"Arthur Heymans
This code is only meant to be used in early stages so move it back to earlymtrr.c. This reverts commit 3ad00d0c89c9e7a8e9ef13b6dc65bb338a191ec8. Change-Id: I9bc1ac4b863eb43d3e398e6462ee139a7751bf62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64804 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-01Revert "cpu/x86: Add function to set `put_back_original_solution` variable"Arthur Heymans
Now that mtrr_use_temp_range() can deal with multiple ranges there is no need to expose this to restore the MTRR solution. This reverts commit 00aaffaf470adfbaa0fbfa0ec3cc67311763810b. Change-Id: Ib77a0f52228cd2f19f3227824f704ac690be4aba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64803 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-01cpu/x86/mtrr: Allow for multiple TEMP MTRR rangesArthur Heymans
Temporary MTRR setup usually covers the memory mapped flash. On recent Intel hardware the mapping is not coherent. It uses an external window for parts of the BIOS region that exceed 16M. This now allows up to 10 temporary memory ranges. TESTED: Qemu with multiple MTRR temporary MTRR ranges sets up a valid and optimized temporary MTRR solution. Change-Id: I23442bd2ab7602e4c5cbd37d187a31413cf27ecc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-31cpu/x86/smm_module_load: Fix SMM stub paramsKyösti Mälkki
There is NULL dereference in adjust_apic_id_map() and updating apic_id_to_cpu[] array within SMM stub fails. Initial apic_id_to_cpu[] array may have worked for platforms where APIC IDs are consecutive. Change-Id: Ie59a731bfc883f8a47048b2ceacc66f44aa5b68c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-29cpu/x86: Allow SoC to select the LAPIC access modeSubrata Banik
Intel Meteor Lake SoC expects to select x2APIC for accessing LAPIC hence, this patch provides an option where SoC code choose the correct LAPIC access mode using choice selection. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I39c99ba13ad6e489c300bd0d4ef7274feeca9d4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-28cpu/x86/mp_init.c: Drop 'real' vs 'used' save stateArthur Heymans
Now that the save state size is handled properly inside the smm_loader there is no reason to make that distinction in the mp_init code anymore. Change-Id: Ia0002a33b6d0f792d8d78cf625fd7e830e3e50fc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28cpu/x86/smm_module_load: Rewrite setup_stubArthur Heymans
This code was hard to read as it did too much and had a lot of state to keep track of. It also looks like the staggered entry points were first copied and only later the parameters of the first stub were filled in. This means that only the BSP stub is actually jumping to the permanent smihandler. On the APs the stub would jump to wherever c_handler happens to point to, which is likely 0. This effectively means that on APs it's likely easy to have arbitrary code execution in SMM which is a security problem. Change-Id: I42ef9d6a30f3039f25e2cde975086a1365ca4182 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28cpu/x86/smm_module_loader: Add a convenient ss_topArthur Heymans
We don't want to keep track of the real smm size all the time. As a bonus now ss_start is now really the start of the save state instead of top - MAX(stub_size, save state size). Change-Id: I0981022e6c0df110d4a342ff06b1a3332911e2b7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28cpu/x86/smm_module_loader.c: Rewrite setupArthur Heymans
This code is much easier to read if one does not have to keep track of mutable variables. This also fixes the alignment code on the TSEG smihandler setup code. It was aligning the code upwards instead of downwards which would cause it to encroach a part of the save state. Change-Id: I310a232ced2ab15064bff99a39a26f745239f6b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28cpu/x86/smm: Drop 'entry' struct elementArthur Heymans
This is a duplicate of code_start. Change-Id: I38e8905e3ed940fb34280c939d6f2f1fce8480a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-05-28cpu/x86/smm: Refactor creating a stub/save state mapArthur Heymans
This code was very hard to read so rewrite it using as few mutable local variables as possible. Tested on qemu with 128 cores. Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-23cpu/x86/smm: Remove heapArthur Heymans
Currently no smihandler uses heap. coreboot's heap manager also is quite limited in what it will free (only the latest alloc). This makes it a bad idea to use it inside the smihandler, as depending on the alloc usage the heap might actually be full at some point, breaking the smihandler. This also reduces the ramstage by 448 bytes on google/vilboz. Change-Id: I70cd822be17c1efe13c94a9dbd2e1038808b9c56 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-16arch/x86/postcar_loader.c: Change prepare_and_run_postcar signatureArthur Heymans
The postcar frame can now be a local variable to that function. Change-Id: I873298970fff76b9ee1cae7da156613eb557ffbc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16arch/x86/postcar: Set up postcar MTRR in C codeArthur Heymans
Setting up postcar MTRRs is done when invd is already called so there is no reason to do this in assembly anymore. This also drops the custom code for Quark to set up MTRRs. TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set in postcar & ramstage. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16cpu/x86/mp_init.c: Add mp_run_on_all_cpus_synchronouslyKane Chen
MTRR is a core level register which means 2 threads in one core share same MTRR. There is a race condition could happen that AP overrides BSP MTRR unintentionally. In order to prevent such race condition between BSP and APs, this patch provides a function to let BSP assign tasks to all APs and wait them to complete the assigned tasks. BUG=b:225766934 Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63566 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16cpu/amd: Remove unused <cpu/x86/pae.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/) Change-Id: I4cab4b66c3d123dbb8a948a5596aa4975b31139b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-05cpu/intel/model_2065x: Drop unused function declarationAngel Pons
Looks like the `set_power_limits()` declaration is copy-pasta leftovers from `cpu/intel/model_206ax`. As it's unused, get rid of it. Change-Id: I81704e883e52fea42488f52be116b6fcc2c6af4b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-27cpu/intel/socket_p: Increase DCACHE_RAM_SIZEArthur Heymans
The lowest bound for L2 cache size on Socket P is 512 KiB. This allows the use of cbfs mcache on all platforms. This fixes building when some debug options are enabled. Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27nb/intel/pineview: Use cbfs mcacheArthur Heymans
There is plenty of cache available to increase DCACHE_RAM_SIZE to allow the use of cbfs mcache. Tested on Gigabyte GA-D510UD, still boots and resumes. Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-25cpu/x86/64bit: Generate static page tables from an assembly fileArthur Heymans
This removes the need for a tool to generate simple identity pages. Future patches will link this page table directly into the stages on some platforms so having an assembly file makes a lot of sense. This also optimizes the size of the page of each 4K page by placing the PDPE_table below the PDE. Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-25cpu/x86/64bit: Add a separate Makefile.incArthur Heymans
Follow-up patches will add more to this makefile. Change-Id: I8da6265b4c810e39a67f5ec27e26eeb26e3679a4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-04-24{arch,cpu}: Remove redundant <arch/cpu.h>Elyes HAOUAS
<arch/cpu.h> is chain included through <cpu/cpu.h>. Change-Id: I54a837394f67ac2a759907c7212ab947d07338dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24cpu/intel: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: If0e3ca8dccf18c016f56208c4ee6fc08719a634b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-22cpu/amd: Remove unused <cbmem.h>Elyes HAOUAS
Change-Id: Ie9344da411a86186fa161e82db3c3fd3ffb911f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-21cpu/x86/fpu_enable.inc: Remove file used by romccArthur Heymans
Change-Id: I530bb217bb9a944990232dcf4e08f160b5267512 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55008 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19cpu/x86/Kconfig*: Guard with ARCH_X86Arthur Heymans
None of these options make sense on different ARCH. Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63673 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14x86/mtrr: Print address ranges inclusive to be more consistentWerner Zeh
The printed address ranges in the tree (resource allocator and even some MTRR code) usually shows the range inclusive (meaning from start address to the real end address of the range). Though there is still some code in the MTRR context which prints the ranges with an exclusive end. This patch aligns the printing of ranges in the MTRR code to be consistent among the tree so that the shown end addresses are now inclusive. Change-Id: I0ca292f9cf272564cb5ef1c4ea38f5c483605c94 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2022-04-13cpu/x86/mtrr: Use `need_restore_mtrr` to set put_back_original_solutionSubrata Banik
This patch calls into need_restore_mtrr() from the mtrr_use_temp_range function to set `put_back_original_solution` to discard any temporary MTRR range prior to boot to payload. BUG=b:225766934 TEST=Able to build and boot google/brya to verify that `remove_temp_solution()` is able to discard any temporary MTRR range before booting to payload. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2e00ec593847e1eb173d5ac77b15b50342860f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-13cpu/x86: Add function to set `put_back_original_solution` variableKane Chen
`put_back_original_solution` variable in mtrr.c is static, but there is a need to set put_back_original_solution outside of mtrr.c in order to let `remove_temp_solution` to drop any temporary MTRRs being set outside `mtrr_use_temp_range()`, for example: `set_var_mtrr()` function is used to set MTRRs for the ROM caching. BUG=b:225766934 TEST=Able to build and boot google/redrix. Change-Id: Ic6b5683b2aa7398a5e141f710394ab772e9775e7 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-04-11cpu/x86/smm: Add sinkhole mitigation to relocatable smmstubArthur Heymans
The sinkhole exploit exists in placing the lapic base such that it messes with GDT. This can be mitigated by checking the lapic MSR against the current program counter. Change-Id: I49927c4f4218552b732bac8aae551d845ad7f079 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-11cpu/x86/smm_module_loader.c: Clean up printing the CPU mapArthur Heymans
There is no reason to do this in a separate loop. Change-Id: I7fe9f1004597602147aae72f4b754395b6b527cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-02cpu/x86/mtrr: Delay removing `temp` variable range MTRR snapshotSubrata Banik
This patch delays removing `temporary` MTRR snapshots to avoid conflicts with other operations attached with same `BS_PAYLOAD_BOOT/BS_ON_EXIT` boot state. BUG=b:225766934 TEST=Having variable MTRR snapshot using display_mtrrs() is able to list only the permanent MTRRs and all temporary MTRRs are removed prior to boot to payload. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I602dca989745159d013d6573191861b296f5d3ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/63220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02{cpu/x86, drivers/amd}: Use `get_var_mtrr_count()` to get MTRR countSubrata Banik
This patch replaces the implementation that is used to get the number of variable MTRRs with `get_var_mtrr_count()` function. BUG=b:225766934 TEST=Able to build and boot google/redrix board to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4751add9c45374e60b7a425df87d06f52e6fcb8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-02cpu/x86/mtrr: Make useful MTRR functions available for all boot stagesSubrata Banik
This patch migrates a few useful MTRR functions as below from `earlymtrr.c` file to newly created common stage file `mtrrlib.c`. 1. get_free_var_mtrr 2. set_var_mtrr 3. clear_all_var_mtrr These functions can be used to perform the MTRR programming from IA common code SPI driver as `fast_spi.c` without requiring two separate implementations for early boot stage (till romstage) and for ramstage onwards. BUG=b:225766934 TEST=Able to build and boot google/redrix board to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2c62a04a36d3169545c3128b4231992ad9b3699d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01cpu/intel/fit: Clear the FIT table when setting pointerArthur Heymans
When rebuilding coreboot the empty fit table added to added to CBFS stays the same so the build process sees no reason to update the file. In the meantime ifittool did update that file for instance to add microcode update entries. So each time coreboot is rebuilt the entries are appended to the FIT table which runs out of space at some point. One way to deal with this is to clear the fit table when setting the pointer inside the bootblock. TESTED: Now running 'make' again on prodrive/hermes does not report an error with a filled FIT table. Change-Id: Ia20a489dc90a4ae704e9ee6d532766899f83ffcc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63036 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10cpu/x86/smm: Add weak SoC init and exit methodsRaul E Rangel
This change provides hooks for the SoC so it can perform any initialization and cleanup in the SMM handler. For example, if we have a UART enabled firmware with DEBUG_SMI, the UART controller could have been powered off by the OS. In this case we need to power on the UART when entering SMM, and then power it off before we exit. If the OS had the UART enabled when entering SMM, we should snapshot the UART register state, and restore it on exit. Otherwise we risk clearing some interrupt enable bits. BUG=b:221231786, b:217968734 TEST=Build test guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-09cpu/intel/common: Add support for energy performance preference (EPP)Cliff Huang
This provides support to update energy performance preference value. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/62653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMIRaul E Rangel
This change will allow the SMI handler to write to the cbmem console buffer. Normally SMIs can only be debugged using some kind of serial port (UART). By storing the SMI logs into cbmem we can debug SMIs using `cbmem -1`. Now that these logs are available to the OS we could also verify there were no errors in the SMI handler. Since SMM can write to all of DRAM, we can't trust any pointers provided by cbmem after the OS has booted. For this reason we store the cbmem console pointer as part of the SMM runtime parameters. The cbmem console is implemented as a circular buffer so it will never write outside of this area. BUG=b:221231786 TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are visible when running `cbmem -1`. Perform a suspend/resume cycle and verify new SMI events are written to the cbmem console log. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28cpu/x86/smm: Support PARALLEL_MP with SMM_ASEGArthur Heymans
This will allow to migrate all platform to the parallel_mp init code and drop the old lapic_init code. Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58700 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic numberFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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