summaryrefslogtreecommitdiff
path: root/src/cpu
AgeCommit message (Collapse)Author
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27intel/i82801ix: new southbridge, ICH9Patrick Georgi
Add support for ICH9 southbridge Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-20Unify use of bool config variablesStefan Reinauer
e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-20secondary.S: Fix dropping ramstage.aStefan Reinauer
This unused code was not silently dropped as before. Change-Id: Ic76c58e233869a60c3a8a27c2efc2182b3a4442d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1863 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-20Make sure only one udelay function is availableStefan Reinauer
The Agesa wrapper and UDELAY_TIMER2 define their own timer functions, so don't shove in UDELAY_IO Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1864 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16Clean up KconfigStefan Reinauer
- move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Add spinlock to serialize Intel microcode updatesStefan Reinauer
Updating microcode on several threads in a core at once can be harmful. Hence add a spinlock to make sure that does not happen. Change-Id: I0c9526b6194202ae7ab5c66361fe04ce137372cc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1778 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Clean up stack checking codeStefan Reinauer
Several small improvements of the stack checking code: - move the CPU0 stack check right before jumping to the payload and out of hardwaremain (that file is too crowded anyways) - fix prototype in lib.h - print size of used stack - use checkstack function both on CPU0 and CPU1-x - print amount of stack used per core Signed-off-by: Stefan Reinauer <reinauer@google.com> Test: Boot coreboot on Link, see the following output: ... CPU1: stack: 00156000 - 00157000, lowest used address 00156c68, stack used: 920 bytes CPU2: stack: 00155000 - 00156000, lowest used address 00155c68, stack used: 920 bytes CPU3: stack: 00154000 - 00155000, lowest used address 00154c68, stack used: 920 bytes ... Jumping to boot code at 1110008 CPU0: stack: 00157000 - 00158000, lowest used address 00157af8, stack used: 1288 bytes Change-Id: I7b83eeee0186559a0a62daa12e3f7782990fd2df Reviewed-on: http://review.coreboot.org/1787 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13clean up lapic_cpu_init.cStefan Reinauer
- drop changelog and add license header instead - 80+ character fixes - make stacks array static because it's not used externally - rename copy_secondary_start_to_1m_below() Change-Id: I8b461bea21ee0ddd85ea3a3a923d1e15167f54f0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1821 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-13Pass the CPU index as a parameter to startup.Ronald G. Minnich
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-13Fix CONFIG_MAX_CPU set to 1 CPU build problemStefan Reinauer
There are some function dependancies that didn't work when MAX_CPU was set to 1 and the build would fail. Change-Id: I033a42056f7b48a40316e03772ed89ad9cb013fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1819 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-13Support better tracking of AP stack usage.Ronald G. Minnich
This change allows us to figure out how much of the AP stacks we are using, as well as to catch any case of an AP overrunning its stack. Also, the stack is poisoned, which is a good way to catch programming errors -- code should never count on auto variables being zerod. The stack bases are recorded in a new array, stacks. At the end, when all APs are initialized, the stacks are walked and the lowest level of the stack that is reached is printed. Build and boot and look for output like this: CPU1: stack allocated from 00148000 to 00148ff4:\ lowest stack address was 00148c4c CPU2: stack allocated from 00147000 to 00147ff4:\ lowest stack address was 00147c4c CPU3: stack allocated from 00146000 to 00146ff4:\ lowest stack address was 00146c4c Note that we used only about 1K of stack, even though in this case we allocated 4K (and in the main branch, we allocate 32K!) Change-Id: I99b7b9086848496feb3ecd207f64203fa69fadf5 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1818 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-12ivybridge: Catch unknown CPU revisionsStefan Reinauer
Adding an entry for 0x306a0 will make sure that all CPUs with CPUIDs 0x306aX will execute the driver (analog to Sandybridge behavior) Change-Id: I0353f3a48ecfd41274fdf6ee302c7d34482f1b5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12Fix gcc-4.7 building problem.Han Shen
Applied function attribute to function definition to avoid 'conflicting type' warning. Function declaration is in src/include/cpu.h void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); But function definition in lapic_cpu_init.c is missing the "__attribute__" part. Change-Id: Idb7cd00fda5a2d486893f9866920929c685d266e Signed-off-by: Han Shen <shenhan@google.com> Reviewed-on: http://review.coreboot.org/1784 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-12Initialize the VMX MSRMarc Jones
The VMX MSR may come up with random values and needs to be initialized to zero. This was done incorrectly in finalize_smm. It must be done on a per core basis in the general CPU init. This touches all Sandybridge and Ivybridge configs. Change-Id: I015352d0f8e2ebe55ac0a5e9c5bbff83bd2ff86b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12Revert "Remove code that enables/disables VMX in coreboot on chromebooks."Marc Jones
The MSR for VMX can start with a random value and needs to be cleared by coreboot. I am reverting this change, as it handles almost everything and doing a follow-on change to fix the improper clearing of the MSR. Change-Id: Ibad7a27b03f199241c52c1ebdd2b6d4e81a18a4e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12sandybridge: Correct reporting of cores and threadsStefan Reinauer
The reporting of cores and threads in the system was a bit ambiguous. This patch makes it clearer. Change-Id: Ia05838a53f696fbaf78a1762fc6f4bf348d4ff0e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1786 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-07Leave power control registers unlockedSameer Nanda
To allow easy experimentation with thermals, leave power control registers unlocked. Change-Id: Ia53065f3f220c2faed58e7d53e60c3f169ae58ec Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/1688 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-06cpu/intel/model_1067x: Add proper c-state/p-state/thermal supportNico Huber
Change-Id: I853454e8f5617fb7af5dddd7288bdeeacc7b1b8e Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-06intel/socket_BGA956: enable speedstep, CAR, MMX, SSEPatrick Georgi
All of these capabilities exist on all CPUs supported on this socket. Change-Id: I54f34e48e34bb6ab5b9954ab7ece8c2c3a1a8e67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1664 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05Overhaul speedstep codeNico Huber
This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-05Fix some indentation flaws and break very long linesNico Huber
Change-Id: I3efef6bc8f519382ffdd92eb10b4bcd1a4361ba9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1657 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-02AMD agesa: add enable cache at the end of disable_cache_as_ramSiyuan Wang
add this code according to src/include/cpu/x86/cache.h ,line 92, functin enable_cache() Change-Id: Ida96a98397eeed98dd61ca979e8c5a33bf00f9e5 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1662 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-02Correct FSB reading in speedstep ACPINico Huber
We parsed the MSR the wrong way, and didn't support some valid values. Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-01Merge cpu/intel/acpi.h into cpu/intel/speedstep.hNico Huber
We had only some MSR definitions in there, which are used in speedstep related code. I think speedstep.h is the better and less confusing place for these. Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1655 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-30Add support for socket LGA775Stefan Tauner
Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1581 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-07Fix typo in mPGA603 socketKyösti Mälkki
Change-Id: I7a49d5fc13fb605a47c3c1662758ebd5935e7780 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1564 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-10-07Remove chip.h files without config structureKyösti Mälkki
Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1473 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-19C32 legacy code: change CONFIG_CPU_AMD_SOCKET_C32 to ↵Siyuan Wang
CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them. CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before. But it is not a good idea, so we change the code as follows: So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code, and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code. Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1497 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-05VIA Nano: Add support for VIA Nano CPUsAlexandru Gagniuc
Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1257 Tested-by: build bot (Jenkins)
2012-09-05buildsystem: Make CPU microcode updating more configurableAlexandru Gagniuc
This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. Choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c MICROCODE_IN_CBFS should, in the future, be eliminated. Right now it is needed by intel microcode updating. Once all intel cpus are converted to cbfs updating, this variable can go away. These files are then compiled and assembled into a binary CBFS file. The advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) Gives user more control over if and how to include microcode blobs 3) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/1245 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-08-27Intel model_106cx: change CAR to HT-capableKyösti Mälkki
There are hyper-threading Atom CPUs, those would not enable L2 cache with model_6ex CAR code. Switch to code that can handle different number of threads and cores. Change-Id: I57328c231f8998f45f7b0d26c63b24585f8476dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1384 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: James Laird <jhl@mafipulation.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-22Auto-declare chip_operationsKyösti Mälkki
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-09Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPUKyösti Mälkki
The search loop for UMA resource was only used to check for the highest RAM address below 4GB. The cached values from BSP CPU can now be used for the replication. Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1388 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-09AMD northbridge: copy TOP_MEM and TOP_MEM2 for distributionKyösti Mälkki
Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed to AP CPUs and factor out the debugging info from setup_uma_memory(). Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1387 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-09Synchronize rdtsc instructionsStefan Reinauer
The CPU can arbitrarily reorder calls to rdtsc, significantly reducing the precision of timing using the CPUs time stamp counter. Unfortunately the method of synchronizing rdtsc is different on AMD and Intel CPUs. There is a generic method, using the cpuid instruction, but that uses up a lot of registers, and is very slow. Hence, use the correct lfence/mfence instructions (for CPUs that we know support it) Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1422 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-08-07Move cpus_ready_for_init() to AMD K8Kyösti Mälkki
The function is a noop for all but amd/serengeti_cheetah. Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1184 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-05AMD S3: Remove the hardcoded volatile positionzbao
Change-Id: I4bcf3f3435f0ba487955d14ed1b010fd94b9f625 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1408 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-04Make the device tree available in the rom stageStefan Reinauer
We thought about two ways to do this change. The way we decided to try was to 1. drop all ops from devices in romstage 2. constify all devices in romstage (make them read-only) so we can compile static.c into romstage 3. the device tree "devices" can be used to read configuration from the device tree (and nothing else, really) 4. the device tree devices are accessed through struct device * in romstage only. device_t stays the typedef to int in romstage 5. Use the same static.c file in ramstage and romstage We declare structs as follows: ROMSTAGE_CONST struct bus dev_root_links[]; ROMSTAGE_CONST is const in romstage and empty in ramstage; This forces all of the device tree into the text area. So a struct looks like this: static ROMSTAGE_CONST struct device _dev21 = { #ifndef __PRE_RAM__ .ops = 0, #endif .bus = &_dev7_links[0], .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}}, .enabled = 0, .on_mainboard = 1, .subsystem_vendor = 0x1ae0, .subsystem_device = 0xc000, .link_list = NULL, .sibling = &_dev22, #ifndef __PRE_RAM__ .chip_ops = &southbridge_intel_bd82x6x_ops, #endif .chip_info = &southbridge_intel_bd82x6x_info_10, .next=&_dev22 }; Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727 Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1398 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-03Intel CPUs: Fix counting of CPU coresKyösti Mälkki
Detection for a hyper-threading CPU was not compatible with multicore CPUs. When using CPUID eax==4, also need to set ecx=0. CAR init tested on real hardware with hyper-threading model_f25 and under qemu 0.15.1 with multicore CPU. Change-Id: I28ac8790f94652e4ba8ff88fe7812c812f967608 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1172 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-01Intel Sandybridge: add reserved memory as resourcesKyösti Mälkki
Reserved memory resources will get removed from memory table at the end of write_coreboot_table(), Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1372 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-07-31Revert "Use broadcast SIPI to startup siblings"Sven Schnelle
This reverts commit 042c1461fb777e583e5de48edf9326e47ee5595f. It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I7dd1cba5a4c1e4b0af366b20e8263b1f6f4b9714 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1381 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-31Revert "remove CONFIG_SERIAL_CPU_INIT"Sven Schnelle
This reverts commit 78efc4c36c68b51b3e73acdb721a12ec23ed0369. The broadcast patch was reverted, so this commit should also be reverted. The reason for reverting the broadcast patch: It turned out that sending IPIs via broadcast doesn't work on Sandybridge. We tried to come up with a solution, but didn't found any so far. So revert the code for now until we have a working solution. Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1380 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26CPU: Add option to set TCC activation offsetDuncan Laurie
The default TCC activation offset is 0, which means TCC activation starts at Tj_max. For devices with limited cooling ability it may be desired to lower TCC activation. This adds an option that can be declared in the devicetree to set the TCC activation to a non-zero value. Enable tcc_offset=15 in devicetree.cb and build/boot the BIOS and check that the value is set in the MSR: > and $(shr $(rdmsr 0 0x1a2) 24) 0xf 0xf Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1343 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26ACPI: Add a method to notify OS to re-read _PPCDuncan Laurie
Split this behavior out from PNOT() so the OS can update _PPC limit without re-reading C-state tables. Change-Id: I81b9111a4866f6b9916f74ac57a3caefaa77c565 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1342 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26ACPI: Add function to write _PPC using NVSDuncan Laurie
The existing NVS variable for PPCM will be used to select a dynamic max P-state. By itself this does not change existing behavior because the NVS PPCM variable is initialized to zero. PPCM can be tested by building and booting a modified BIOS that sets gnvs->ppcm to a value greater than 1 and checking from the OS that the P-state is limited to that value. Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1341 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26USBDEBUG: buffer up to 8 bytesSven Schnelle
EHCI debug allows to send message with 8 bytes length, but we're only sending one byte in each transaction. Buffer up to 8 bytes to speed up debug output. Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1357 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2012-07-26Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logsStefan Reinauer
On SandyBridge systems configured to work with Panther Point the CPU would wrongly be described as IvyBridge. Fix this issue and drop an unneeded Kconfig variable at the same time. Change-Id: I501a4fa00613e589cd315cfee61b2f9561dfcb4d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1335 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-26Enable Microcode in CBFS for all SandyBridge/IvyBridge systemsStefan Reinauer
Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1332 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25SMM: Fix state table for Intel Core2 CPUsStefan Reinauer
When fixing the SMM state table for SandyBridge/IvyBridge CPUs the wrong table was used for older 64bit capable CPUs. Change-Id: Ia7dff21aa3f0e5aa61575634fc839777de6bef10 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1353 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-25Fix comment to reference IvyBridge, tooStefan Reinauer
On both SandyBridge and IvyBridge BCLK is fixed at 100MHz. Have the comment reflect that. Change-Id: Ia81c3501dc3e68cf3143c3bc864dfbf88901f9f9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1336 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25Include SandyBridge Microcode when IvyBridge is enabledStefan Reinauer
.. in case the system has pluggable CPUs or might come in different SKUs. Change-Id: I7a7cd95b4de5dd78370355f448688e8d000434c1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1333 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25Fix date output in Microcode updateStefan Reinauer
Date and time are mixed up: microcode: updated to revision 0x12 date=2012-12-04 should be microcode: updated to revision 0x12 date=2012-04-12 Change-Id: I85f9100f31d88bb831bef07131f361c92c7ef34e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1334 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2012-07-25Fix LAPIC timer on Ivy Bridge systemsStefan Reinauer
The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy Bridge systems. However, the current timer code assumed that the clock would run at 200MHz instead. This made all delays twice as long as needed. Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1330 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
CPUs with configurable TDP will run the TSC at the max non-turbo ratio for the maximum TDP value, which can cause issues if another TDP is desired. To deal with this we set the flex ratio to the nominal TDP ratio early in the boot and then configure the Soft Reset Data registers so the PCH can tell the CPU what frequency to run at after a reset. This is done very early in the bootblock because it is necessary to reset the system after setting a flex ratio. The end result is that the TSC will now increment at the max non-turbo frequency for the nominal TDP. On some system with 1.8GHz CPU ensure that the kernel detects the CPU speed as ~1800mhz rather than ~2300mhz: > dmesg | grep "MHz processor" [ 0.004000] Detected 1795.801 MHz processor. Change-Id: I8436dced9199003b6423186a2b041e3f7b84ab8c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1309 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24SMM: Add heap region and move C handler higher in regionDuncan Laurie
In order to support SPI and ELOG drivers the SMM region needs to be able to be larger than the previous allocation below 0x7400. Now that we have support for 4M TSEG we do not need to live in this region. This change adds a 16KB heap region abofe the save state area at TSEG+64KB and moves the C handler above this. The heap region is then available for malloc and the C handler can grow to support flash and event log features. While updating the memory map comment in assembly stub I also added a pause instruction to the cpu spin lock as this was added to the C code in latest upstream rebase. Dump sympbols from smm.elf binary to see the new regions: 00010000 B _heap 00014000 B _eheap 00014000 T _smm_c_handler_start 0001b240 T _smm_c_handler_end Change-Id: I45f0ab4df1fdef3b626f877094a58587476ac634 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1308 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24CPU: Update ivybridge PP1 current limit valueDuncan Laurie
The BWG says ivybridge current limit for PP1 is 50A. Verify the PP1 current limit value on link device: > echo $(( ( $(rdmsr 0 0x602) & 0x1fff ) >> 3 )) 50 Change-Id: I946269d21ef605f2525fe03993f569d69128294b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1305 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24CPU: Add basic support for Nominal Configurable TDPDuncan Laurie
Ivybridge B0+ CPUs are capable of supporting multiple TDP levels. This complicates the default case because now the registers that were reporting max non-turbo ratio are reporting that value for the highest possible TDP level. For now this change just forces everything to use the Nominal TDP values instead of the higher (or lower) levels. - When building P-state tables, determine the P[1] (max non turbo) ratio based on the Nominal ratio if available. - Set the turbo activation ratio to the Nominal max ratio. - Mirror the power level settings in new MCHBAR register after they are written, which happens after BIOS_RESET_CPL is set. - Set the current ratio to Nominal ratio at boot. 1) Verify that P-state table is generated properly with P[0]=1801MHz (ratio 0x1C) and P[1]=1800MHz (ratio 0x12) PSS: 1801MHz power 17000 control 0x1c00 status 0x1c00 PSS: 1800MHz power 17000 control 0x1200 status 0x1200 2) Verify power limits in MCHBAR match PKG_POWER_LIMIT: > rdmsr 0 0x610 0x800080aa00dc8088 > mmio_read32 0xfed159a4 0x000080aa > mmio_read32 0xfed159a0 0x00dc8088 3) Verify turbo activation ratio is set to nominal ratio: > rdmsr 0 0x64c 0x0000000000000012 4) Check that proper ratio was set at boot on one core only: > grep 'frequency set to' /sys/firmware/log model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 model_x06ax: frequency set to 1800 Change-Id: I592e60a7740f31b140986a8269dca91b4adbb270 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1304 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Rename cache_lbmem() to cache_ramstage()Stefan Reinauer
... and don't require it to specify a cache type. This function is only used on romcc boards, and should go away (because all boards should be switched to CAR) Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1288 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Config changes to support microcode in CBFSVadim Bendebury
Nothing is yet enabled, this is just a config skeleton change. The MICROCODE_INCLUDE_PATH definition is going to be used by the Makefile building the microcode blob for CBFS inclusion. Change-Id: I7868db3cfd4b181500e361706e5f4dc08ca1c87d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1292 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Add microcode blob processingVadim Bendebury
When microcode storage in CBFS is enabled, the make system is supposed to generate the microcode blob and place it into the generated ROM image as a CBFS component. The microcode source representation does not change: it is still an array of 32 bit constants. This new addition compiles the array into a separate object file and then strips all sections but data. The raw data section is then included into CBFS as a file named 'microcode_blob.bin' of type 0x53, which is assigned to microcode storage. Change-Id: I84ae040be52f520b106e3471c7e391e64d7847d9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1295 Tested-by: build bot (Jenkins)
2012-07-24Add code to read Intel microcode from CBFSVadim Bendebury
When CONFIG_MICROCODE_IN_CBFS is enabled, find the microcode blob in CBFS and pass it to intel_update_microcode() instead of using the compiled in array. CBFS accesses in pre-RAM and 'normal' environments are provided through different API. Change-Id: I35c1480edf87e550a7b88c4aadf079cf3ff86b5d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1296 Tested-by: build bot (Jenkins)
2012-07-24Make MAX_PHYSICAL_CPUS invisible on non-AMD boardsStefan Reinauer
It's only used on AMD based boards. Hence drop it, so we don't accidently start using it by mistake instead of MAX_CPUS Change-Id: Id8f522f24283129874d56e70bd00df92abe9c3cf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1325 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Rename microcode include file to be model agnosticVadim Bendebury
In preparation to support CBFS hosted microcode blobs, this change renames the wrapper include file containing the microcode to be independent of CPU model. Change-Id: If1a4963a52e5037a3a3495b90708ffc08b23f4c1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1294 Tested-by: build bot (Jenkins)
2012-07-24Properly identify ACPI C3 states in _CST table.Duncan Laurie
Dump and disassemble ACPI tables and look in _CST. In the last entry the state was getting set to 0: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000000, // State 0x0000005A, // Latency 0x000000C8 // Power } Now it is properly identifed as state 3: Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x01, // Access Size ) }, 0x00000003, // State 0x0000005A, // Latency 0x000000C8 // Power } Change-Id: Ie0a68606c5a43ac5fb5ba7bb9a3fef933ad67b64 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1297 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-24Remove code that enables/disables VMX in coreboot on chromebooks.Ronald G. Minnich
There are several reasons for this: 1. It's a core setting, not a platform setting, which is bizarre. But, we disable vmx via an SMI, and that only happens on core 0. Hence, the code did not correctly make the same settings on all cores- one had them disabled, the others were in an unknown state. When (e.g.) kvm started on a vmx-enabled core, then moved to a vmx-disabled core, the processor would reset *very* quickly. Changing this would be messy. 2. On the CPU on link, there is something about trying to set the lock bit that is getting a GPF. 3. It's the wrong place and time to set it. Once controlled, they can't be changed in the kernel. The kernel is what should control this feature, not the BIOS, as we have learned time and time again. If somebody is in as root and can start a VM, you have a lot more to worry about than someone starting a guest virtual machine. Change-Id: I4f36093f1b68207251584066ccb9a6bcfeec767e Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1276 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24MTRR: drop repetetive debug messageStefan Reinauer
It's not really useful anymore I guess, and it makes the log files harder to read. Hence dropping it. Change-Id: If4c3e8b40ae491ca527ef62f8145206960f6579d Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-23Re-initialize Local APIC timer on APsStefan Reinauer
In order to be able to use udelay in code running on AP cores the timer has to be initialized on the according local APICs or the system will just hang when udelay is used. Change-Id: I776bc96aa6d876ff2582d0c05cbc9c7611cb06b5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1267 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-22AMD CPUs: Updated CPU list in powernow_acpi.cJukka Rantala
Updated P state table to make frequency scaling work. Added these CPUs: http://support.amd.com/us/Processor_TechDocs/30430.pdf Also wrote a Python script for parsing AMD docs, but not sure where to put it: http://pastebin.com/1dSvkXwc Change-Id: I8f08111b73b9be551f3f59d2acb15051ccf36c1e Signed-off-by: Jukka Rantala <jukka.rantala@gmail.com> Reviewed-on: http://review.coreboot.org/1244 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-18AMD northbridges: drop dead codeKyösti Mälkki
Change-Id: I03949722ac3a127319a0ad3f812d77ba7b8f139f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1187 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16AMD: Fix GFXUMA with 4GB or more RAMKyösti Mälkki
Northbridge code incorrectly adjusted the last cacheable memory resource to accomodate room for UMA framebuffer. If system had 4GB or more memory that last resource is not below 4GB and not the one where UMA is located. There are three consequences: The last entry in coreboot memory table is reduced by uma_memory_size. Due the incorrect code in northbridge code state.tomk, end of last resource below 4GB, had not been adjusted. Incrementing that by uma_memory_size diverts a region possibly claimed for MMIO to RAM, as TOP_MEM is written. Since the UMA framebuffer did not have IORESOURCE_CACHEABLE, it was ignored from the MTRR setup and not set uncacheable. The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs, should be copied from BSP to all APs instead of deriving the data separately for each Logical CPU. Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1217 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16AMD MTRR: fix rounding and renamesKyösti Mälkki
Use state.tomk to refer TOP_MEM, largest RAM address below 4GB. Use state.tom2k to refer TOP_MEM2, largest RAM address above 4GB. When setting either TOP_MEM or TOP_MEM2, any RAM resource found must fit below the set value. Thus, round register value upwards, not downwards. Change-Id: I436c1b3234c911680ce8b095052f8d71f40113e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1216 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Check for IORESOURCE_UMA_FB in MTRR setupKyösti Mälkki
If northbridge called uma_resource() a resource of this type should be found when walking the resources list. For now, be rude and don't even try to combine it with neighboring regions. As the type is un-cacheable it is dominant over other MTRR setups claiming the same region. Change-Id: I57805e7e7da0709f8ed78d8df62c2abf22172a06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14Remove useless file from building.zbao
Change-Id: I09c695347c04d7db9add2cbb687d59c829175cfc Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1224 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-12Drop Kconfig VAR_MTRR_HOLE optionKyösti Mälkki
All but one board use the default value of enabled. Disabling this can only increase the number of MTRR registers used. Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-12Fix stack assignment during CPU initializationSven Schnelle
There are two errors in the code. The first one is a missing $ sign in mov _stack, %esp. Thanks to Ronald G Minnich for catching that bug. The second bug is the 'incl %eax', which shouldn't be there, as there's no secondary CPU with index 0. CPU0 uses always the stack below _estack. Change-Id: Id267a654ba95b0e898eeaaafb2403b438250a563 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1212 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2012-07-05Only copy real-mode section of SIPI vectorKyösti Mälkki
The SIPI vector copy can use a static location below 1MB, aligned to 4kB. Jump out of the copy once in protected mode. Change-Id: I6299aa3448270663941cf2c4113efee74bcc7993 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1165 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-05Fix the CPU index parameter passed to secondary_cpu_init().Kyösti Mälkki
Count 0,1,2,3,... instead of 0,2,3,4,... Change-Id: I3c6b85e5e71b32deac5470809e1618d28f19c00f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1173 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel cpus: Extend cache to cover complete Flash DeviceKyösti Mälkki
CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup would not cover the bottom 4 MB when ramstage is decompressed. Verify CACHE_ROM_SIZE is power of two. One may set CACHE_ROM_SIZE==0 to disable this cache. Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1146 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel model_106cx: change CAR to model_6exKyösti Mälkki
Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/642 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel cpus: delete dead CAR code and whitespace fixesKyösti Mälkki
A diff from model_6fx to model_106cx suggests there is little CORE2 specific code that was once considered useful to have. In its current status however, sockets supporting model_6fx use model_6ex CAR init, so that specific code is actually never used. Deletes file: model_6fx/cache_as_ram.inc Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/640 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-04Intel cpus: use CPU_ADDR_BITS from Kconfig during CARKyösti Mälkki
Default CPU_ADDR_BITS is 36. For Atom (model_106cx) use 32. This model is known to fail execution-in-place (XIP) with the default 36. Pentium M should use 32, but doesn't even with this patch. Some Xeon and CORE(2) models should use 38 or 40. Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/639 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2012-07-03AGESA F15 wrapper for Trinityzbao
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-02remove CONFIG_SERIAL_CPU_INITSven Schnelle
The new broadcast code doesn't support serial init - if a CPU needs serial init, this should be handled in the model specific CPU init code. Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1140 Tested-by: build bot (Jenkins)
2012-07-02Use broadcast SIPI to startup siblingsSven Schnelle
The current code for initializing AP cpus has several shortcomings: - it assumes APIC IDs are sequential - it uses only the BSP for determining the AP count, which is bad if there's more than one physical CPU, and CPUs are of different type Note that the new code call cpu->ops->init() in parallel, and therefore some CPU code needs to be changed to address that. One example are old Intel HT enabled CPUs which can't do microcode update in parallel. Change-Id: Ic48a1ebab6a7c52aa76765f497268af09fa38c25 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1139 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-02Intel CPUs: execute microcode update only once per coreKyösti Mälkki
Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1142 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-19Enable Intel PECI on Model 6fx CPUsSven Schnelle
Those CPUs support the PECI (Platform Environment Control Interface), so enable it. This interface is commonly used for tasks like fan control. Change-Id: Id2dadc4821de8cc0b579e77235aa36892e57fd02 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1104 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-06-12udelay: add missing bus frequencySven Schnelle
commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1099 Tested-by: build bot (Jenkins)
2012-05-30Fix the location of "Setting variable MTRR" printk.Denis 'GNUtoo' Carikli
Without that fix the debugging is harder because the person debugging coreboot will see the following twice(note the repeated MTRR number): Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 4096MB, range: 512MB, type WB Setting variable MTRR 1, base: 4608MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC instead of the following twice: Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea: May 25 23:57:17 <kmalkki> I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs() Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/1058 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-05-29Drop config variable CPU_MODEL_INDEXStefan Reinauer
It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs and the code can easily be changed to not rely on any Kconfig magic. Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1047 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-08Some more #if cleanupPatrick Georgi
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} + (manual tweak since it hit a false positive) Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} + Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-03Fix register corruption during Intel Microcode updateStefan Reinauer
Another bug in the Intel microcode update code that existed since we switched to LinuxBIOSv2 in 2004: The inline assembly code that reads the CPU revision from an MSR after running cpuid(1) trashes registers EBX and ECX. Only ECX was mentioned in the clobber list. C code running after this function could silently access completely wrong data, which resulted in the wrong date being printed on microcode updates (and potentially other issues happening until the C code writes to EBX again) Change-Id: Ida733fa1747565ec9824d3a37d08b1a73cd8355f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/996 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-02Don't include console.h in microcode.c when compiling with ROMCCStefan Reinauer
If microcode.c is built by romcc, this indicates that we are running microcode updates in the bootblock (e.g. before enabling cache as ram). In this case we did not enable any consoles yet, so we don't output anything. This patch removes inclusion of the unnecessary console/console.h for that case, which was breaking with certain configurations. Change-Id: Iebb57794d7b1e84cac253d249d47b88de4dd28a3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/988 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01Drop CONFIG_MAX_PHYSICAL_CPUS on non-AMD boardsStefan Reinauer
CONFIG_MAX_PHYSICAL_CPUS is defined by quite a number of mainboards whithout any code actually using the variable. Hence, drop MAX_PHYSICAL_CPUS from Kconfig for those boards. In the long run we should drop CONFIG_MAX_PHYSICAL_CPUS use completely and make the code dynamic or depend on CONFIG_MAX_CPUS instead. Change-Id: I37dcc74d245ddba5186b96bd82220dacb6f4d323 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/984 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-01Move VSA support from x86 to GeodePatrick Georgi
Instead of the special case in the generic Makefile.inc, use cbfs-files in the CPU directories. Change-Id: I71d9c8dff906c9a516ac0dd09a315f8956075592 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/962 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-05-01Make geode_lx use the vsa from blobs repositoryPatrick Georgi
... or fail if repository is not enabled. Change-Id: I0a1e6d6fed852ec7edf96ace8346ae6b23838a56 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/959 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-04-30Fix up Sandybridge C state generation codeStefan Reinauer
This code fixes the sandybridge C state generation code to work with the current version of the ACPI code generator. Change-Id: I56ae1185dc0694c06976236523fdcbe5c1795b01 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/950 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 20:13:42 +0000