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path: root/src/cpu
AgeCommit message (Expand)Author
2012-01-23post code: Replaced hard-coded post code with macroVikram Narayanan
2012-01-21trivial: spelling fixes in commentsVikram Narayanan
2012-01-20Leave SSE and MMX instructions enabled in corebootStefan Reinauer
2012-01-10MTRR: get physical address size from CPUIDSven Schnelle
2012-01-09Fix Geode GX2 + LX caching for tiny bootblock.Nils Jacobs
2012-01-09ACPI: mark empty get_cst_entries() weakSven Schnelle
2011-12-26Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.Marc Jones
2011-12-13Use MMCONF for all AMD family 10 CPUs.Marc Jones
2011-12-05Bootblock does not need a unique boot_cpu()Kyösti Mälkki
2011-11-24Remove unused code files and cosmetic changesKyösti Mälkki
2011-11-22k8 raminit: add workaround for erratum #181 on non-fam-fFlorian Zumbiehl
2011-11-22Fix post_code in 16bit entryKyösti Mälkki
2011-11-01remove trailing whitespaceStefan Reinauer
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
2011-10-30Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
2011-10-18Activate older Xeon P4 microcodesKyösti Mälkki
2011-10-17Fixes several issues with amd k8 SSDT P-state generationOskar Enoksson
2011-10-15SMM: Move wbinvd after pmode jumpStefan Reinauer
2011-10-13Load an IDT with NULL limitStefan Reinauer
2011-10-11Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=EOskar Enoksson
2011-09-24Add AMD Family 10h PH-E0 supportQingPei Wang
2011-09-12Miscellaneous AMD F14 warning fixesefdesign98
2011-09-09Crank up CPU speed on Intel Core and Core2 CPUsPatrick Georgi
2011-09-07AMD F14 Rev C0 updateKerry She
2011-08-06Update AMD F14 Agesa to support Rev C0 cpusefdesign98
2011-08-04cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.Keith Hui
2011-07-22Add SSE3 dependent codeefdesign98
2011-07-22Update AMD SR5650 and SB700efdesign98
2011-07-18Add AMD Family 10 support to cpu folderefdesign98
2011-07-13Make AMD SMM SMP awareRudolf Marek
2011-07-04Small SMM fixupsRudolf Marek
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
2011-05-15Cosmetic cleanup.Scott Duplichan
2011-05-15Correct the number of MCA error reporting banks cleared.Scott Duplichan
2011-05-151) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.Scott Duplichan
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
2011-05-10This replaces the fixed shift values in the apic timer init with macros.Vikram Narayanan
2011-05-03Enable caching for ROM area in model_6ex/cache_as_ram.incSven Schnelle
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
2011-04-21more ifdef -> if fixes.Stefan Reinauer
2011-04-21more ifdef -> if fixesStefan Reinauer
2011-04-19Fix some more misuses of ifdef/if definedStefan Reinauer
2011-04-14drop half an uart8250 implementation from smiutil and use the common code Stefan Reinauer
2011-04-14earlymtrr.c: wipe some dead code, use names instead of numbers and someStefan Reinauer
2011-04-14drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCHStefan Reinauer
2011-04-14Use symbolic names for some MTRR bits instead of numbers in CAR codeStefan Reinauer
2011-04-11Unify use of post_codeAlexandru Gagniuc
2011-03-28Add AMD C32 support.Zheng Bao
2011-03-17Fix breaking the build after removing files in tthe previous checkin. Marc Jones
2011-03-04Add P-states for select Socket 754 processors.Jonathan Kollasch
2011-03-03Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code.Jonathan Kollasch
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-28Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-27Prepare for next patches (Improving BKDG implementation of P-states,Xavi Drudis Ferran
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
2011-02-26It adds support for automatic PSS object generation for AMD pre fam Fh CPU. T...Rudolf Marek
2011-02-24Add compile-time defaults to some K8 CMOS options in case they're absent in CMOSJosef Kellermann
2011-02-14Add AMD cpu wrapper code. Patch 4 of 8.Frank Vibrans
2011-02-10According to AMD documentation, cache type WP should be used forScott Duplichan
2011-02-10Implemented workaround for erratum 169, obsoleting erratum 131.Alexandru Gagniuc
2011-02-10Fix a potential system hang by handling AMD Model F Erratum 89Josef Kellermann
2011-01-27oops. this is weird. CAR addresses should be specified in the socket and not inStefan Reinauer
2011-01-19Revert r5902 to make code more readable again. At least three people like toStefan Reinauer
2011-01-19Now that the VIA code is run above 1Meg (like other boards), it shouldKevin O'Connor
2011-01-12drop unused filesStefan Reinauer
2011-01-01Add AMD SB800 southbridge CIMx code.Kerry She
2010-12-30Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge codeNils Jacobs
2010-12-26Remove dead and unused Geode GX2 codeNils Jacobs
2010-12-26Replace Geode GX2 MSR addresses for GLCP on GLIU1 with namesNils Jacobs
2010-12-26Clean up Geode GX2 comments, whitespace and coding style. Trivial.Nils Jacobs
2010-12-18SMM on AMD K8 Part 2/2Rudolf Marek
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
2010-12-18Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 boardPatrick Georgi
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